JPH0869855A - Manufacture of test socket of semiconductor device package - Google Patents

Manufacture of test socket of semiconductor device package

Info

Publication number
JPH0869855A
JPH0869855A JP22884594A JP22884594A JPH0869855A JP H0869855 A JPH0869855 A JP H0869855A JP 22884594 A JP22884594 A JP 22884594A JP 22884594 A JP22884594 A JP 22884594A JP H0869855 A JPH0869855 A JP H0869855A
Authority
JP
Japan
Prior art keywords
terminals
semiconductor device
resin
package
device package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22884594A
Other languages
Japanese (ja)
Inventor
Hirotaka Ueda
弘孝 上田
Tokuo Torisu
徳夫 鳥巣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP22884594A priority Critical patent/JPH0869855A/en
Publication of JPH0869855A publication Critical patent/JPH0869855A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enhance productivity without causing a twist and deformation even if receiving terminals to engage with external terminals are put at a fine pitch by layering engaging parts with the external terminals of a package and the receiving terminals having a deriving pin through a calking part, and molding the layered body by resin. CONSTITUTION: External terminals 2a of a semiconductor device package 2 are inserted in receiving terminals 1, or contact engaging parts 3 are provided, and the intermediate part becomes a socket holder slit corresponding part 5, and a calking part 6 is formed on the tip. When the receiving terminals 1 are punched, calked and layered, a dummy 10 is interposed so that an interval between the adjacent terminals l corresponds to a pitch of the external terminals 2a of the package 2. After the terminals 1 are layered, the slit corresponding part 5 of an intermediate part of deriving pins 4 is formed as a resin block as a resin mold 11. Therefore, the receiving terminals 1 are fixed at intervals in a file shape with insulating performance. Afterwards, when the resin block of the terminals 1 is installed on a holder 12, a test socket 13 where the engaging parts 3 into which the external terminals 2a of the package 2 enter are juxtapoed at prescribed intervals on the obverse side and the pins 4 are juxtapoed at prescribed intervals on the reverse side, is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置パッケージの
電気的特性をテストするテストソケットの製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a test socket for testing the electrical characteristics of a semiconductor device package.

【0002】[0002]

【従来の技術】半導体装置パッケージは、例えばリード
フレームのパッドに半導体チップ(以下 チップとい
う)を搭載し、チップ端子とインナーリードをボンディ
ングワイヤ−で接続し、樹脂等でインナーリード以内の
部分を封止して製造され、当該パッケージから突出し外
部端子のアウターリードが所定形状に成形される。
2. Description of the Related Art In a semiconductor device package, for example, a semiconductor chip (hereinafter referred to as a chip) is mounted on a pad of a lead frame, a chip terminal and an inner lead are connected by a bonding wire, and a portion inside the inner lead is sealed with a resin or the like. The outer lead of the external terminal is formed into a predetermined shape by protruding from the package.

【0003】半導体装置は高機能、多機能及び小型化等
により、入出力信号ピンは多数で且つ、その間隔(ピッ
チ)が狭くなっている。
The semiconductor device has a large number of input / output signal pins and a narrow interval (pitch) due to high functionality, multi-function, miniaturization and the like.

【0004】これらの半導体装置パッケージは製造途中
あるいは製造後に、品質保証や管理等のために電気的特
性試験が行われる。該試験は半導体装置パッケージの外
部端子をテストソケットに挿入してなされる。
These semiconductor device packages are subjected to an electrical characteristic test for quality assurance and control during or after manufacturing. The test is performed by inserting the external terminals of the semiconductor device package into the test socket.

【0005】半導体装置は前述のように多ピンで小ピッ
チとなり、例えば外部端子のピッチは0.25mm程度
と非常に微細となっている。このような半導体装置パッ
ケ−ジの電気的特性試験では、テストソケットの受け端
子は同様に微細ピッチとせねばならない。
As described above, the semiconductor device has a large number of pins and a small pitch. For example, the pitch of external terminals is extremely fine, about 0.25 mm. In the electrical characteristic test of such a semiconductor device package, the receiving terminals of the test socket must also have a fine pitch.

【0006】[0006]

【この発明が解決しようとする課題】テストソケットに
は半導体装置パッケージの外部端子が係合する受け端子
が植設されている。該受け端子はプレス加工あるいはエ
ッチング加工で成形され、この1枚1枚を人手でソケッ
トホルダ−の端子挿入スリットの隙間に差し込み、前記
テストソケットが製造される。
A receiving terminal with which an external terminal of a semiconductor device package engages is implanted in the test socket. The receiving terminals are formed by pressing or etching, and each of the terminals is manually inserted into the gap of the terminal insertion slit of the socket holder to manufacture the test socket.

【0007】テストソケットの製造では、ソケットホル
ダ−の端子挿入スリットへの受け端子の差し込みが人手
でなされるから、受け端子にねじれや変形が生じること
があり、その組み立て作業に熟練と時間を要している。
特に、最近の半導体装置の多ピン化に伴い前記受け端子
の植設は微細なピッチでなさねばならないので、その製
造が難しくコスト高になる等の問題がある。
In the manufacture of the test socket, since the receiving terminal is manually inserted into the terminal insertion slit of the socket holder, the receiving terminal may be twisted or deformed, which requires skill and time to assemble. are doing.
In particular, with the recent increase in the number of pins of semiconductor devices, the receiving terminals must be planted at a fine pitch, which makes it difficult to manufacture them, resulting in a high cost.

【0008】本発明は被検査半導体装置パッケージの外
部端子と係合する受け端子の設置が微細ピッチであって
もねじれ、変形等を生じることなく、且つ熟練を要さず
生産性高くできる半導体装置パッケージのテストソケッ
トを得ることを目的とする。
According to the present invention, a semiconductor device can be manufactured without twisting or deforming even if a receiving terminal which engages with an external terminal of a semiconductor device package to be inspected is installed with a fine pitch and without requiring skill and with high productivity. The purpose is to get a test socket for the package.

【0009】[0009]

【課題を解決するための手段】本発明の要旨は、被検査
半導体パッケージの外部端子との係合部と導出ピンを有
するとともにかしめ部を形成した受け端子を打抜き、該
受け端子を所定間隔をおいてかしめ積層し、該かしめ積
層した受け端子の導出ピン中間部のソケットホルダ−ス
リット相当部を樹脂モ−ルドして樹脂ブロックとし、該
樹脂モ−ルドより先端側のかしめ部を除去し、ソケット
ホルダ−に装着することを特徴とする半導体装置パッケ
ージのテストソケット製造方法にある。
DISCLOSURE OF THE INVENTION The gist of the present invention is to punch out a receiving terminal having an engaging portion for engaging an external terminal of a semiconductor package to be inspected and a lead-out pin and having a crimped portion, and to place the receiving terminal at a predetermined interval. After caulking and laminating, the portion corresponding to the socket holder-slit in the middle of the lead-out pin of the caulking-laminating receiving terminal is resin-molded into a resin block, and the caulking portion on the tip side of the resin-mold is removed, A method for manufacturing a test socket for a semiconductor device package, characterized in that the test socket is mounted on a socket holder.

【0010】[0010]

【作用】本発明は、被検査半導体装置パッケージの外部
端子との係合部と導出ピン及びかしめ部を有する受け端
子を、所定間隔をおいて前記かしめ部を介して積層し、
前記導出ピン中間部のソケットホルダ−スリット相当部
を樹脂モ−ルドとして固定するので、受け端子はねじれ
や変形することなく、且つ容易に樹脂ブロックされる。
その後、樹脂モ−ルドより先端側にあるかしめ部を除去
し、当該樹脂ブロックをソケットホルダ−に装着するこ
とで、熟練を要することなく精度よく、また短時間で半
導体パッケージのテストソケットが製造できる。
According to the present invention, a receiving terminal having an engaging portion with an external terminal of a semiconductor device package to be inspected, a lead-out pin and a caulking portion is laminated with the caulking portion at predetermined intervals,
Since the socket holder-corresponding to the slit in the middle portion of the lead-out pin is fixed as a resin mold, the receiving terminal is easily resin-blocked without being twisted or deformed.
After that, by removing the caulking portion on the tip side of the resin mold and mounting the resin block on the socket holder, a test socket for a semiconductor package can be manufactured accurately and in a short time without requiring skill. .

【0011】[0011]

【実施例】図面において、1は受け端子で、半導体装置
パッケージ2の外部端子2aが挿入あるいは当接する係
合部3が形成される。4は導出ピンで、前記係合部3の
反対側に突出して形成され、その中間部はソケットホル
ダースリット相当部5となり、先端部分にかしめ部6が
形成される。導出ピン4は図2の(A)(B)(C)に
示すように形成位置を周期的に変えることが、多ピンの
半導体装置パッケージ2をテストするのに好ましい。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the drawings, reference numeral 1 is a receiving terminal, on which an engaging portion 3 into which an external terminal 2a of a semiconductor device package 2 is inserted or abuts is formed. Reference numeral 4 denotes a lead-out pin, which is formed so as to project to the opposite side of the engaging portion 3, an intermediate portion thereof serves as a socket holder slit-corresponding portion 5, and a caulking portion 6 is formed at the tip portion. It is preferable to test the multi-pin semiconductor device package 2 by periodically changing the formation position of the lead-out pin 4 as shown in FIGS. 2A, 2B and 2C.

【0012】かしめ部6は、例えば図3に示すように積
層1枚目の受け端子1には貫通孔7が、それ以降の受け
端子1には切起し突起8が形成され、該切起し突起8が
前の貫通孔7あるいは切起し突起背面孔9に入り込ん積
層されるようになっている。かしめ部6の形状はこの実
施例に限らずV字状等の任意にできる。
In the caulking portion 6, for example, as shown in FIG. 3, a through hole 7 is formed in the receiving terminal 1 of the first laminated sheet, and a cut-and-raised protrusion 8 is formed in the subsequent receiving terminal 1. The projection 8 is inserted into the front through hole 7 or the cut-raised projection rear hole 9 to be laminated. The shape of the caulking portion 6 is not limited to this embodiment, but may be any V shape or the like.

【0013】前記係合部3、導出ピン4及びかしめ部6
の打抜き形成はプレス加工によりなされる。また、かし
め部6の貫通孔7と切起し突起8形成の切り替えは、ポ
ンチのダイ側への進退深さを変えることで容易になされ
る。
The engaging portion 3, the lead-out pin 4 and the caulking portion 6
The punching and forming is performed by pressing. Further, switching between formation of the through hole 7 of the caulking portion 6 and the cut-and-raised protrusion 8 can be easily performed by changing the depth of advance / retreat of the punch toward the die side.

【0014】受け端子1を打抜きかしめて積層する際
は、隣り合う受け端子1の間隔が被検査半導体装置パッ
ケージ2の外部端子2aのピッチに相当するようにダミ
−10を図3のように介在させる。半導体装置の多ピン
化で前記ピッチが狭まったもののテストソケットを製造
する場合は、ダミ−10を薄ものとすることで精度よく
且つ容易に対応できる。
When the receiving terminals 1 are punched and caulked to be stacked, the dummy 10 is interposed as shown in FIG. 3 so that the interval between the adjacent receiving terminals 1 corresponds to the pitch of the external terminals 2a of the semiconductor device package 2 to be inspected. Let When manufacturing a test socket whose pitch is narrowed due to the increase in the number of pins of a semiconductor device, it is possible to accurately and easily deal with it by making the dummy 10 thin.

【0015】前記受け端子1をテストソケットの一辺の
長さに応じて積層した後、導出ピン4の中間部のソケッ
トホルダ−スリット相当部5を樹脂モ−ルド11して樹
脂ブロックとする。これにより、受け端子1は所定間隔
で且つ絶縁性を有して隊列状に固定される。
After stacking the receiving terminals 1 according to the length of one side of the test socket, the socket holder-slit corresponding portion 5 in the middle of the lead-out pin 4 is made into a resin block 11 to form a resin block. As a result, the receiving terminals 1 are fixed in a row at a predetermined interval and with an insulating property.

【0016】前記樹脂ブロックされた受け端子1の積層
体は、導出ピン4の先端部分のかしめ部6で互いに接続
しているので、樹脂モ−ルド11部より先端側のかしめ
部6を除去し、各受け端子1をそれぞれ電気的に非接続
とし、その先端がピン先端となる。
Since the resin-blocked laminated body of the receiving terminals 1 is connected to each other at the caulking portion 6 at the tip of the lead-out pin 4, the caulking portion 6 on the tip side of the resin mold 11 is removed. , The receiving terminals 1 are not electrically connected to each other, and the tips of the receiving terminals 1 are pin tips.

【0017】その後、該受け端子1の樹脂ブロックをソ
ケットホルダ−12に装着すると、表側には被検査半導
体装置パッケージ2の外部端子2aが入り込む係合部3
が所定間隔で並び、裏側には導出ピン4が所定間隔で並
んだテストソケット13が得られる。
After that, when the resin block of the receiving terminal 1 is mounted on the socket holder 12, the engaging portion 3 into which the external terminal 2a of the semiconductor device package 2 to be inspected enters the front side.
Is arranged at a predetermined interval, and the lead-out pins 4 are arranged at a predetermined interval on the back side to obtain a test socket 13.

【0018】[0018]

【発明の効果】本発明は前述のように、半導体装置パッ
ケージの外部端子との係合部と、導出ピンを有する受け
端子がかしめ部を介して積層され、その積層体が樹脂モ
−ルドされるから、所定間隔をもって当該受け端子が微
細なピッチで配設ものであっても、ねじれや変形を生じ
ることなく隊列状に固定されたテストソケットが熟練を
要さず容易に得られる。
As described above, according to the present invention, the engaging portion with the external terminal of the semiconductor device package and the receiving terminal having the lead-out pin are laminated through the caulking portion, and the laminated body is resin-molded. Therefore, even if the receiving terminals are arranged at a predetermined pitch at a fine pitch, a test socket fixed in a row without twisting or deforming can be easily obtained without requiring any skill.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の1実施例においてテストソケットを示
す図。
FIG. 1 is a diagram showing a test socket according to an embodiment of the present invention.

【図2】本発明の1実施例においてテストソケットの受
け端子を示す図。
FIG. 2 is a diagram showing a receiving terminal of a test socket in one embodiment of the present invention.

【図3】本発明の1実施例においてかしめ積層された受
け端子の隊列を示す図
FIG. 3 is a diagram showing an array of receiving terminals that are caulked and laminated in one embodiment of the present invention.

【図4】本発明の1実施例におけるテストソケットの製
造を示す図。
FIG. 4 is a diagram showing the manufacture of a test socket according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 受け端子 2 半導体装置パッケージ 3 係合部 4 導出ピン 5 ソケットホルダ−スリット相当部 6 かしめ部 7 貫通孔 8 切起し突起 9 切起し突起背面孔 10 ダミ− 11 樹脂モ−ルド 12 ソケットホルダ− 13 テストソケット 1 Receiving Terminal 2 Semiconductor Device Package 3 Engagement Part 4 Outlet Pin 5 Socket Holder-Slit Corresponding Part 6 Caulking Part 7 Through Hole 8 Cut-and-raised Protrusion 9 Cut-and-raised Protrusion Rear Hole 10 Dam 11 Resin Mold 12 Socket Holder -13 Test socket

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 被検査半導体装置パッケージの外部端子
との係合部と導出ピンを形成するとともにかしめ部を設
けた受け端子を打抜き、該受け端子を所定間隔をおいて
かしめ積層し、該かしめ積層した受け端子の導出ピン中
間部のソケットホルダ−スリット相当部を樹脂モ−ルド
して樹脂ブロックとし、前記樹脂モ−ルドより先端側の
かしめ部を除去し、ソケットホルダ−に装着することを
特徴とする半導体装置パッケージのテストソケット製造
方法。
Claim: What is claimed is: 1. A receiving terminal, which forms an engaging portion with an external terminal of a semiconductor device package to be inspected and a lead-out pin and is provided with a caulking portion, is punched out, the receiving terminal is caulked and laminated at a predetermined interval, and the caulking is performed. The socket holder in the middle of the lead-out pin of the laminated receiving terminals-a portion corresponding to the slit is resin-molded to form a resin block, and the caulking portion on the tip side of the resin mold is removed and then mounted on the socket holder. A method for manufacturing a test socket for a semiconductor device package having a feature.
JP22884594A 1994-08-29 1994-08-29 Manufacture of test socket of semiconductor device package Pending JPH0869855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22884594A JPH0869855A (en) 1994-08-29 1994-08-29 Manufacture of test socket of semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22884594A JPH0869855A (en) 1994-08-29 1994-08-29 Manufacture of test socket of semiconductor device package

Publications (1)

Publication Number Publication Date
JPH0869855A true JPH0869855A (en) 1996-03-12

Family

ID=16882776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22884594A Pending JPH0869855A (en) 1994-08-29 1994-08-29 Manufacture of test socket of semiconductor device package

Country Status (1)

Country Link
JP (1) JPH0869855A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7307443B2 (en) 2005-05-17 2007-12-11 Infineon Technologies Ag Test socket for an integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7307443B2 (en) 2005-05-17 2007-12-11 Infineon Technologies Ag Test socket for an integrated circuit

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