JPH0869408A - Extended storage data transfer control system - Google Patents

Abstract

PURPOSE: To provide the extended storage data transfer control system which reduces a hardware constitution quantity and facilitates transfer control. CONSTITUTION: This extended storage data transfer control system consists of an arithmetic processor 100 including a transfer instruction register 101, a page border address generating circuit 102, a page conversion buffer index circuit 103, a page conversion buffer 104, a decomposed data transfer length generating circuit 105, a decomposition extended storage address generating circuit 106, and a transfer address sending-out circuit 107, an extended storage transfer controller 200 including a data transfer processing circuit 201, a main storage device 300, and an extended storage device 400; and the constitution hardware quantity is reduced and the extended storage data transfer control is facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an extended storage data transfer control system, and more particularly to an extended storage data transfer control system for controlling data transfer between a main storage device and an extended storage device.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of an example of a conventional extended storage data transfer control system. As shown in FIG. 3, in the conventional example, the transfer instruction register 1
01, a page conversion buffer index circuit 103 and a page conversion buffer 104, a data transfer processing circuit 202, a page conversion buffer 203, a page conversion buffer index circuit 204, and an instruction execution unit 20.
Extended storage transfer control device 200 including the main storage device 3 and the main storage device 3
00 and an extended storage device 400.

As shown in FIG. 3, in this conventional example, a page conversion buffer 203 is also provided inside the extended storage transfer control device 200 included in the extended storage data transfer control system, and arithmetic processing is performed. The extended storage data transfer instruction is sent from the device 100 to the transfer instruction register 101.
When the data is sent to the extended storage transfer control device 200 via the, the sequential addresses are calculated from the start address and the data transfer length designated by the extended storage data transfer instruction, and the page conversion buffer 203 determines the start address and the page boundary address. After being converted into a real address, the data transfer processing circuit 202 causes the main storage device 300 and the extension storage device 40 to operate.
Data is being transferred to and from 0. (Prior Art 1) FIG. 4 is a block diagram showing the configuration of another example of the conventional extended storage data transfer control system. As shown in FIG. 4, the transfer instruction register 101,
An arithmetic processing unit 100 including a page conversion buffer index circuit 103, a page conversion buffer 104, and an extended storage instruction address conversion circuit 108, and a data transfer processing circuit 20.
2, an extended storage transfer control device 20 including an instruction execution unit 205, an extended storage instruction main storage address synthesis circuit 206, a transfer length generation circuit 207, and an extended storage address generation circuit 208.
0, a main storage device 300, and an extended storage device 400.

As shown in FIG. 4, in this conventional example, the page conversion buffer is not provided inside the extended storage transfer control device 200, but is provided inside the arithmetic processing device 100. In this case, when the extended storage data transfer control device 200 receives an extended storage data transfer instruction sent from the arithmetic processing device 100 via the transfer instruction register 101, the extension storage data transfer instruction is sent via the instruction execution unit 205. Addresses are sequentially calculated from the start address specified by the storage data transfer instruction and the data transfer length, and the address is the extended storage instruction main storage address generation circuit 2
It is sent to the arithmetic processing unit 100 via 06 and is converted into a real address by the page conversion buffer 104 in the arithmetic processing unit 100. In the extended storage transfer control device 200, by the real address sent back from the arithmetic processing device 100 via the extended storage instruction address conversion circuit 108 and the data transfer information held in the extended storage transfer control device 200, The data transfer processing circuit 202 is transferring data between the main storage device 300 and the extended storage device 400 (prior art 2).

[0005]

In the above-mentioned conventional extended storage data transfer control system (prior art 1),
Since the page conversion data registration control unit for registering the page conversion data in the page conversion buffer is required because the page conversion buffer is provided in the extended storage transfer control device, the amount of hardware increases. There is.

Further, in the conventional extended storage data transfer control system (prior art 2), when the extended storage transfer control device indexes the page conversion buffer in the arithmetic processing device, the extension storage data transfer control device and the arithmetic processing device are connected to each other. However, there is a drawback in that the communication becomes necessary, the control action therefor becomes complicated, and the hardware amount of the page conversion unit and the control bus increase.

Further, there is a disadvantage that it takes time to convert a page and the processing time of the extended storage data transfer instruction is prolonged.

[0008]

An extended storage data transfer control system of the present invention comprises a main storage device and an extension storage device, and an extension storage device for controlling data transfer between the main storage device and the extension storage device. In the data transfer system, transfer address information for controlling data transfer between the main storage device and the extended storage device includes predetermined real page address information, disassembled extended storage address information, and disassembled transfer length address information. An arithmetic processing device that generates and outputs information, and transfer address information output from the arithmetic processing device are input, and data transfer between the main storage device and the extension storage device is performed based on the transfer address information. And an extended storage transfer control device for processing.

The arithmetic processing unit includes a transfer instruction register for holding head main memory virtual address information, head extended storage address information and data transfer length information, the head main memory virtual address information and the head extended storage address information. And a page translation buffer index information that receives page boundary virtual address information sequentially generated by the page boundary address generation circuit and page boundary address generation circuit that sequentially generates page boundary virtual address information from the address information. And a page conversion buffer index circuit for sequentially reading real page address information from the page conversion buffer, the page boundary virtual address information and page size information sequentially generated in the page boundary address generation circuit, and the transfer instruction register Is held in From the serial head extended storage address information,
The page boundary virtual address is generated from the decomposed extended memory address generation circuit that sequentially generates the decomposed extended memory address information to be accessed, the page boundary virtual address information that is sequentially generated in the page boundary address generation circuit, and the data transfer length information. The disassembled data transfer length generating circuit for sequentially generating disassembled data transfer length information between information, the address conversion buffer index circuit, the disassembled extended storage address generating circuit, and the disassembled data transfer length generating circuit. The extended storage is configured by including a real page address information, the decomposed extended storage address information, and a transfer address sending circuit for sequentially sending the decomposed data transfer length information as the transfer address information to the expanded storage transfer control device. The transfer control device uses the arithmetic processing as the transfer address information. A data transfer processing circuit that processes data transfer between the main storage device and the extended storage device based on the real page address information sent from the storage device, the split extended storage address information, and the split data transfer length information. May be provided.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. As shown in FIG. 1, the transfer instruction register 101 and the page boundary address generation circuit 1 are used in this embodiment.
02, a page conversion buffer index circuit 103, a page conversion buffer 104, a decomposition data transfer length generation circuit 105, a decomposition extended storage address generation circuit 106 and a transfer address transmission circuit 107, and a data transfer processing circuit 201. Extended storage transfer control device 200
And a main storage device 300 and an extended storage device 400.

FIG. 2 is an exploded schematic diagram of the extended storage data transfer instruction used for explaining the operation of this embodiment. Data transfer is started from the head main storage address (hereinafter referred to as VAO) on the main storage device 300. Read long L bytes of data,
The first extended storage address on the extended storage device 400 (hereinafter,
(Hereinafter referred to as XAO), an extended storage data transfer image in which data is written in an area having a data transfer length of L bytes.

In FIG. 2, page boundary addresses between the head main memory address VAO on the main memory 300 and the data transfer length L are VA1, VA2, and VA3, respectively, and a final main memory address is VAE, and a final main memory is set. The address VAE is assumed to exist between the page boundary address VA3 and the next page boundary. Further, the inter-address data length between the head main memory address VAO and the page boundary address VA1 is set to L1, and similarly, the inter-address data length between the page boundary addresses VA1, VA2 and VA3 is set to L2 and L3, and the page boundary address VA3 is set. The inter-address data length between the last main memory address VAE and LAE is L4. At this time, the data length between addresses L2 and L3 is
It becomes equal to the page size (denoted as S). Furthermore, as the extended storage address on the write destination extended storage device 400, the decomposed extended storage address on the extended storage device 400 corresponding to the page boundary addresses VA1, VA2, VA3 is
Let them be XA1, XA2, and XA3, respectively.

The head main memory address VA0 and the page boundary addresses VA1, VA2, VA3 are virtual addresses,
In the data transfer of the data transfer length L bytes, it is necessary to perform page conversion every time a page boundary is crossed and convert the head main memory address and the page boundary address into real addresses to access the main memory device 300. There is. In the present embodiment, this data transfer with a data transfer length of L bytes is performed for each page boundary address by the inter-address data length of L1 byte, L2 byte, L3 byte and (L-L1).
-L2 -L3) disassembled into four bytes, and the main memory 30
The operation of performing data transfer while translating the address on 0 will be described.

The operation of this embodiment will be described below with reference to FIGS. 1 and 2.

When data transfer is performed between the main storage device 300 and the extended storage device 400, the transfer instruction register 101 stores the head main storage address VA0 in the virtual space managed by the arithmetic processing unit 100, The head extended storage address XA0 on the extended storage processing device 400 and the data transfer length L bytes are set and held, and the data line 1
The head main memory address VA0 is transmitted from 0, the data transfer length L is transmitted from the data line 11, and the head extended memory address XA0 is transmitted from the data line 12.

The page boundary address generation circuit 102 divides the virtual address in the main memory device 300 for each page boundary managed by the arithmetic processing device 100 within the range from the head main memory address VAO to the data transfer length L. Is a circuit that generates an inter-address transfer length between divided page boundary addresses,
When the head main memory address VA0 sent from the transfer instruction register 101 is received via the data line 10, the head main memory address VA0 is sent out from the data line 20 at the first time, and the head main memory address VA0 is sent at the second time. A page boundary address VA1 is generated by generating a head page boundary address VA0 'of a page including the head main memory address VA0 from the storage address VA0 and adding the page size S to the head page boundary address VA0'. , From the data line 20. Then, even after the third time, page boundary addresses VA2 and VA3 are generated and transmitted from the data line 20 in the same manner as the case of the page boundary address VA1. When the page boundary address VA1 is generated, the page boundary address XA1 is generated.
The head main memory address VA0 is subtracted from the head main memory address VA0 to generate an inter-address transfer length L1 corresponding to the head main memory address VA0, which is sent out from the data line 21. Then, after that, the page size S is transmitted from the data line 20.
Here, for convenience of explanation, this is referred to as L2, L3.
And L4. When the page boundary address generation circuit 102 receives the decomposition end signal sent from the decomposition data transfer length generation circuit 105 via the data line 51,
Ends generation of page boundary address.

The page conversion buffer index circuit 103 receives and holds a virtual address via the data line 20, generates a page conversion buffer index address from the logical page address of the virtual address, and sends it to the data line 30. , The real page address sent via the data line 40 is received, and the real page address is combined with the in-page address of the virtual address held so far to generate the real address. Send out.
Then, the head main memory address VA0 sent from the data line 31 and the real addresses corresponding to the page boundary addresses VA1, VA2 and VA3 are respectively RA0 and RA.
1, RA2 and RA3.

The decomposed data transfer length generation circuit 105 includes a data transfer length L sent via the data line 11 and inter-address data transfer lengths L1, L2, L3 sent sequentially via the data line 21. From L4, the remaining data transfer length of the data transfer decomposed up to the previous time and the inter-address transfer lengths L1, L2, L3 and L4 are sequentially compared, and if "remaining data transfer length ≥ inter-address transfer length", ,
Data line 5 with inter-address transfer length as disassembled data transfer length
0 is sent and the inter-address transfer length is subtracted from the remaining data transfer length to obtain the remaining data transfer length. When "remaining data transfer length <inter-address transfer length", the remaining data transfer length is disassembled and transferred. It is a circuit for transmitting the data as a length through the data line 50, generating a decomposition end signal, and transmitting it through the data line 51.

The operation of the decomposed data transfer length generation circuit 105 will be described below.

When the data transfer length L sent via the data line 11 and the inter-address transfer lengths L1, L2, L3 and L4 sent sequentially via the data line 21 are received, the data transfer length L becomes Transfer length between page boundary addresses L1
Then, since "L>L1" is satisfied, the inter-page boundary address transfer length L1 is output from the data line 50 as the decomposed data transfer length L1 and the remaining transfer length is (L-L1). Next, the remaining transfer length (L-L1) is compared with the transfer length between page boundary addresses L2, and "(L-L1)>L2"
Therefore, the transfer length L2 between page boundary addresses is sent out from the data line 50 as the disassembled data transfer length L2, and the remaining transfer length is (L-L1-L2). Similarly, the disassembled data transfer length L3 is also generated, and the remaining transfer length is (LL
1-L2-L3). L4, which is the final disaggregated data transfer length, is the remaining transfer length (L-L1-L2-L3) <L4 "
Therefore, the remaining transfer length (L-L1-L2-L3) is set as the disassembled data transfer length.

The decomposition extended storage address generation circuit 106 is
The page size S managed by the arithmetic processing unit 100 divides the virtual address in the main storage device 300 into page boundary units to process the transfer. It is a circuit that divides according to the page boundary of memory. In the decomposed extended storage address generation circuit 106, the head extended storage address XA0 and the data line 2 sent via the data line 12 are sent.
Transfer lengths L1 and L between addresses sequentially sent via 1
2 and L3, the head extended storage address information XA
Add the transfer length information L1 between page boundary addresses to 0,
The decomposed extended storage address information XA1 is generated, and the data line 6
Send by 0. Similarly, by adding the transfer length between page boundary addresses, the decomposed extended storage address information XA2 and XA3 is generated and sent out through the data line 60.

The transfer address sending circuit 107 generates transfer address information decomposed into page boundary unit transfers managed by the arithmetic processing unit 100 from the real address, the decomposed data transfer length, and the decomposed extended storage address to generate data. This is a circuit for sending to the extended storage transfer control device 200 by a line 70. In the transfer address sending circuit 107, the real addresses RA0, RA1, RA2 and RA3, which are sequentially sent via the data line 31, the data line 50 and the data line 60, and the decomposed data transfer lengths L1, L2, L3, L-. L1
-L2-L3 and decomposition extended storage addresses XA0, XA
When sequentially receiving 1, XA2, and XA3, first, the real address RA0, the decomposed data transfer length L1 corresponding to the real address RA0, and the extended storage address information XA05 are collectively generated as transfer address information (called RQ1). Then, the data is transmitted through the data line 70. Thereafter, the real addresses RA1, RA2, and RA3 are sequentially arranged, and the disassembled data transfer length L is set.
2, L3, L-L1-L2-L3 and decomposed extended storage addresses XA1, XA2 and XA3 are also grouped respectively, and transfer address information (RQ2, RQ3 and R
Q4) is generated and sequentially transmitted from the data line 70.

The data transfer processing circuit 201 includes a data line 7
This is a circuit for processing data transfer between the main memory device 300 and the extended memory device 400 by the transfer address information sent from the transfer address sending circuit 107 via 0. In the data transfer processing circuit 201, the data line 7
0 through the transfer address information RQ1 sent from the main memory device 30 based on the real address RA0 indicated by the transfer address information RQ1 and the disassembled data transfer length L1.
The address on 0 is generated, and the read request and the address are sent to the main memory device 300 via the data line 80. The read data is sent via the data line 81 and stored in the buffer in the data transfer processing circuit 201. An address on the extended storage device 400 is generated from the leading extended storage address XA0 in synchronization with the timing at which the leading read data is returned from the main storage device 300, and a write request and address are sent to the extended storage device 400 via the data line 82. The stored data read out from the buffer is sent out via the data line 83 in accordance with the timing of the write request and the address. After that, transfer address information (RQ2, RQ3 and R
Similarly, Q4) is also read from the main storage device 300 in units of partial space pages and written to the extended storage device 400.

[0025]

As described above, according to the present invention, the page conversion buffer is shared by the arithmetic processing unit having the respective means for decomposing the extended storage data transfer instruction, performing the address conversion, and generating the decomposing instruction. You can
The extended storage data transfer instruction can be processed without providing an address translation mechanism in the extended storage device, which has the effect of reducing the amount of hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a data transfer operation in this embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional example.

FIG. 4 is a block diagram showing the configuration of another conventional example.

[Explanation of symbols]

 100 arithmetic processing unit 101 instruction register 102 page conversion address generation circuit 103, 204 page conversion puffer index circuit 104, 203 page conversion buffer 105 decomposition data transfer length generation circuit 106 decomposition extended storage address generation circuit 107 transfer address transmission circuit 108 extended storage instruction Address conversion circuit 200 Extended storage transfer control device 201, 202 Data transfer processing circuit 205 Instruction execution unit 206 Extended storage instruction main storage address generation circuit 207 Transfer length generation circuit 208 Extended storage address generation circuit 300 Main storage device 400 Extended storage device

Claims (2)

[Claims] 1. An extended storage data transfer system, comprising: a main storage device and an extension storage device; and controlling data transfer between the main storage device and the extension storage device, wherein the main storage device and the extension storage device are provided. An arithmetic processing unit that generates and outputs information including predetermined real page address information, disassembly extended storage address information, and disassembly transfer length address information as transfer address information for controlling data transfer between An extended storage transfer control device for inputting transfer address information output from the device, and processing data transfer between the main storage device and the extended storage device based on the transfer address information. And extended storage data transfer control system. 2. A transfer instruction register in which the arithmetic processing unit holds head main memory virtual address information, head extended memory address information, and data transfer length information, the head main memory virtual address information, and head extended memory address information. Page boundary address generation circuit for sequentially generating page boundary virtual address information from these address information, and page conversion buffer index information for receiving the page boundary virtual address information sequentially generated by the page boundary address generation circuit And a page conversion buffer index circuit for sequentially reading real page address information from the page conversion buffer, the page boundary virtual address information and page size information sequentially generated in the page boundary address generation circuit, and the transfer instruction register Is held in A decomposed extended memory address generation circuit for sequentially generating decomposed extended memory address information to be accessed from the head extended memory address information, the page boundary virtual address information sequentially generated in the page boundary address generation circuit, and the data transfer length information From the page boundary virtual address information, a decomposed data transfer length generation circuit for sequentially generating decomposed data transfer length information, the address conversion buffer index circuit, the decomposed extended storage address generation circuit, and the decomposed data transfer length generation. A transfer address sending circuit that sequentially sends the real page address information sequentially generated by a circuit, the decomposed extended storage address information, and the decomposed data transfer length information as the transfer address information to the extended storage transfer control device. The extended storage transfer control device comprises: As transfer address information, data transfer between the main storage device and the extended storage device is performed by the real page address information sent from the arithmetic processing device, the disassembled extended storage address information, and the disassembled data transfer length information. An extended storage data transfer control system, comprising: a data transfer processing circuit that processes the data.