JPH0868875A - Electronic timepiece and method for setting time - Google Patents

Abstract

PURPOSE: To provide an electronic timepiece wherein rapid feed time setting can be surely and quickly performed at a stable speed with good operation feeling. CONSTITUTION: An electronic timepiece comprises an input counting means 103 for counting a time when an input control means 102 detects continuous input of a same switch 107 by using a clock signal produced by a dividing means 101 for dividing an original oscillation 106, an input time detection means 104 for detecting that a value of the input time counting means 103 reached a constant one, and a setting addition and subtraction quantity control means 105 for varying a setting addition and subtraction quantity (time unit) of a setting value every constant time due to the clock signal of the dividing means 101 in response to output of the input time detection means 104. When input of the switch 107 continues, constitution is performed in that the setting addition and subtraction quantity increases at a rate of 2<n> .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for setting numerical values such as clock time and alarm time in an electronic timepiece, and more particularly to improvement of time setting means using fast forward.

[0002]

2. Description of the Related Art In a conventional electronic timepiece, as a method for the operator to set the time, after an input operation by a setting switch is continuously recognized for 1 to 2 seconds, a unit is set at a constant speed while the switch input is continued. A so-called constant-speed fast-forward setting method, such as continuous addition / subtraction of time (fast-forward), is widely used. Furthermore, as a method for improving this setting method, a method (variable speed fast-forward method) of changing the frequency of addition (or subtraction) of unit time according to the switch input duration is also used. In this method, a clock, which is a control cycle of a time control means (for example, a microcomputer) for performing addition (or subtraction) of one unit of time, is, for example, 8 Hz, 16 Hz, 32 Hz, 64.
It is variable in the order of Hz. According to this method, as the switch input continuation time becomes longer, the addition (or subtraction) change amount of the unit time increases and the fast-forwarding amount increases, and when a new setting is made at a time greatly separated from the current set time, Has the advantage that the time to reach that time can be shortened.

[0003]

However, the conventional electronic timepiece described above has the following problems.

First, in the constant-speed fast-forward method, when the fast-forward speed is set relatively slow, for example, when fast-forwarding at a rate of 1 unit time every 8 Hz, the time to be set is far from the current time. Takes time to set the time.
On the other hand, if the fast-forward speed is increased, there is a problem in that it is difficult to set because the target time has passed too much.

In addition, in the variable speed fast-forward method represented by the variable unit of addition / subtraction clock of one unit time, the addition / subtraction process of the unit time can be periodically performed by the time control means such as a microcomputer while the speed is slow. The time can be set at the fast-forward speed. However, for example, when the clock becomes 32 Hz, 64 Hz, etc., the time required for the addition / subtraction processing becomes short, and 32 Hz or 64 H
There is a possibility that processing cannot be completed within the calculation cycle corresponding to z. For this reason, there are cases where reliable periodic addition / subtraction, that is, stable addition / subtraction at a constant speed cannot be performed, which gives a feeling of strangeness to the operator's operational feeling. That is,
There was a problem that it stopped for a moment during the fast-forwarding, resulting in a feeling of being stuck in the operation feeling. This operational problem is not limited to the sensory problem, and the instability of the addition / subtraction speed directly leads to difficulty in setting the time. In other words, if the addition / subtraction speed fluctuates in an unstable manner, it becomes difficult for the user to predict how easily the user will release the switch during fast-forward and stop fast-forward to set the target time. It ends up.

In this case, in order to perform stable addition / subtraction processing, it is conceivable to shorten the one-instruction execution time (system clock) of the microcomputer, that is, to set the original oscillation of the system clock to a higher frequency. However, this causes a decrease in battery life due to an increase in current consumption and an increase in the lower limit of operating voltage of the microcomputer. Furthermore, in a normal clock, 32.
Since a fundamental vibration of 768 kHz is basically required, a second oscillator different from this 32.768 kHz may be required. This causes a problem that the size of the timepiece becomes large due to the increase in cost and the increase in the number of parts used.

Further, the current consumption of the microcomputer is divided into a portion constantly consumed by the hardware portion and a portion consumed by the operation of the software. Then, performing addition / subtraction processing by software at a high frequency such as every 32 Hz or 64 Hz causes a problem of increasing current consumption and decreasing battery life. In controlling the electronic timepiece, 32Hz, 64H
If there is no content to be processed for each z other than this addition / subtraction processing, the microcomputer that should originally be in the standby or stopped state is started for this addition / subtraction processing. This also causes a problem that unnecessary current consumption increases and battery life decreases.

The electronic timepiece and the time setting method of the present invention solve the above problems, and an object thereof is to set the time reliably and quickly at a stable fast-forwarding speed. It is to realize a possible electronic timepiece. Furthermore, it is to realize an electronic timepiece that can set the time with a good operation feeling. Moreover, it is an object of the invention to realize an electronic timepiece that does not cause unnecessary increase in current consumption and does not place an excessive burden on the software of the time control means such as a microcomputer.

[0009]

According to the present invention, in a time setting method for an electronic timepiece, a clock for addition / subtraction processing by a time control means such as a microcomputer is made constant and an operation continuation time of a switch for time setting is set. The unit of time to be added / subtracted is changed according to.
That is, the addition / subtraction process for fast-forwarding is performed at a constant time interval (timing), but the amount (time unit) added / subtracted by this addition / subtraction process changes according to the operation continuation time of the setting switch.

In order to realize this, the present invention has the following two modes.

The first form of the electronic timepiece of the present invention is shown by the block diagram of FIG. That is, in FIG. 1, the frequency dividing means 1 for dividing the original oscillator 106 such as a crystal oscillator.
01, the input control means 102 for detecting a switch input by operating the switch 107 for setting the time, and the input control means 10 using the output clock signal of the frequency dividing means 101.
2, input time counting means 103 for counting the time during which continuous input of the same switch is detected, and input time detecting means 104 for detecting that the value of the input time counting means 103 has reached a predetermined value, This input time detecting means 104
Setting adjustment amount control means 105 for varying the set adjustment amount of the time unit set value for each constant time formed by using the output clock signal of the frequency dividing means 101 according to the output of Is.

Since the present invention is an electronic timepiece, a 1 Hz clock signal (1 second signal) is required for timekeeping. Further, it is desirable that the original vibration has a predetermined oscillation frequency and that the frequency dividing unit 101 divides the frequency by 1/2 in multiple stages. This is to simplify the configuration of the frequency dividing circuit 101. Therefore, the frequency ^dividing means 101 can easily generate a clock signal of 2 ⁿ Hz (n is an integer of 0 or more). Since the input time counting means 103 and the setting adjustment control means 105 both use the output clock signal of the frequency ^dividing means 101, 2 ⁿ
It is effective to use a clock signal of Hz.

Therefore, it is desirable that the input time detecting means 103 counts the 1 Hz signal of the frequency dividing means 101. In this case, using the clock signal of 1 Hz for detecting the continuous input time of the switch is the time timing most suitable for the operation feeling of the operator, and the load of the software for time detection is optimized. This is because That is, the operator operates the setting switch for setting the time because the time is generally in seconds. And
This is because it is sufficient that the software for time detection also operates in units of seconds in consideration of this operation time, and therefore it is not necessary to perform time detection calculation at a frequency exceeding 1 Hz.

Further, it is desirable that the setting adjustment control means 105 operates every 4 Hz, 8 Hz or 16 Hz signal of the frequency dividing means 101. In this case, the setting control unit 1
The operation timing of 05 is 4Hz, 8Hz or 16
If the frequency of the Hz clock signal is 2 Hz or less, there is not much sense of fast-forward and the operator feels annoyed. If it is 32 Hz or more, the load on the software for the addition and subtraction processing increases, and one cycle This is because there is a high possibility that it will be difficult to dispose of it.

Further, the setting adjustment amount by the setting adjustment amount control means 105 is initially set to ± 1 unit, and after a fixed time thereafter, a ratio of ± 2 ⁿ units (± 2, ± 4, ± 8 ...). It is desirable to change with. By doing so, even when the set digits of the time (for example, 1-minute digits) are discontinuously added or subtracted (for example, ± 2, ± 4, ± 8), the higher digits beyond that are set by the time. Unlike the digit, it adjusts continuously, so
It does not give a visual impression that the set adjustment amounts are discontinuous. Therefore, there is an effect that the operation feeling is good for the operator. That is, when the time is set in the states of ± 1 minute, ± 2 minutes, and ± 4 minutes, the display interval of one minute digit is a constant interval (for example, 1/4 second, 1/8 second) in any setting amount state. ,
Every 1/16 second). And ± 2 minutes, ± 4 minutes, ± 8
In the case of minutes, even if the display of the set digit is discontinuous, the higher digits, for example, the 10-minute digit, are adjusted as numerical values one by one, and gradually change rapidly. There is no. Furthermore, the amount of change in addition and subtraction is 2
This is because the doubled value is constant and the operator can easily recognize the rate of change and can easily predict the amount of change, and as a result, the time can be set accurately and easily.

The second aspect of the electronic timepiece of the present invention is
This is shown by the block diagram of FIG. That is, in the figure, a frequency dividing means 701 for dividing a vibration source 706 such as a crystal oscillator, an input control means 702 for detecting a switch input by operating a switch 707 for setting a time, and an output of the frequency dividing means 701. Input control means 7 using a clock signal
02, an input time counting means 703 for counting the time during which continuous input of the same switch is detected, and an input time detecting means 704 for detecting that the value of the input time counting means 703 has reached a predetermined value, This input time detecting means 70
4 has setting digit selecting means 705 for selecting a time setting digit for time setting according to the output of FIG.

This embodiment does not change the amount of adjustment of the time unit setting value at the time setting digit, which is the target for setting the time, as in the first embodiment, but rather the object for setting the time. The time setting digit is changed. By this, the set adjustment amount is substantially changed.

Here, as shown in FIG. 8, the non-selected digit display control means 801 for displaying arbitrary numerical values, symbols, codes, patterns, etc., for digits other than the selected numerical value digit selected by the setting digit selection means 705. It is desirable to have. As a result, there is an effect that the user does not feel uncomfortable in use without changing the numerical value of the non-selected digit (for example, the lower digit of the selected setting digit). Further, the non-selected digits may be controlled so as to be blinked / turned off.

Then, the non-selected digit display control means 801 is
It is desirable to operate at a speed higher than the operation speed of the addition / subtraction means and the display control means operated by the setting digit selection means 705. As a result, there is an effect that it is possible to know at a glance what kind of time is being set and that the operation can be performed with a smooth operation feeling without a feeling of strangeness.

[0020]

EXAMPLES The present invention will be described in detail below based on examples. Note that the time in the present invention is not limited to hours, minutes, seconds, and includes broad information about “hours” such as year, month, day, and day of the week. First, the overall configuration of an electronic timepiece to which the present invention is applied will be described.

FIG. 2 is a hardware configuration diagram showing an embodiment of the electronic timepiece of the invention. In the figure, the electronic timepiece is
It comprises a microcomputer 1, an LCD panel 10, a switch group 11, and an alarm ringing means 13.

The microcomputer 1 controls the entire electronic timepiece. Then, an oscillation circuit 2 having a crystal oscillator as an oscillation source is built in, and the output of the oscillation circuit 2 divided by the dividing circuit 3 is used as a system clock φ of the microcomputer 1. The oscillation frequency of the original vibration is 3
At 2.768 kHz, the signal of 1 Hz is finally obtained by dividing the frequency by 1/2. The signals of a plurality of frequencies divided by the divider circuit 3 are used as control clock signals. The output clock signal of the frequency dividing circuit 3 is input to the interrupt control circuit 4 and is also used as an interrupt timing signal. The interrupt control circuit 4 controls an interrupt by a microcomputer internal signal and an external signal (not shown), and is connected to the input control circuit 12 and the control circuit 5. The control circuit 5 is a central part for controlling various operations including stopping and starting of the microcomputer 1. It is this control circuit 5 that controls the time setting, which is a feature of the present invention.

The control circuit 5, the ROM 6 in which a program for controlling the operation of the electronic timepiece is stored, the RAM 7 for storing various data necessary during the operation of the electronic timepiece,
The display control circuit 9 for controlling the display related to the clock, the input control circuit 12 for monitoring the state of the switch group 11 and controlling the switch input, and the alarm control circuit 13 for controlling the ringing of the alarm ringing means 14 are connected via the internal bus 15. Are connected to each other.

Further, since the frequency dividing circuit 3 is also connected to the internal bus 15, the state of the frequency dividing circuit 3 can be read by a program. Further, since the interrupt control circuit 4 is also connected to the internal bus 15, it is possible to set an interrupt condition and read an interrupt factor by a program. A set value storage memory 8 for storing the set value of the time is provided in a part of the RAM 7. However, this set value storage memory 8 is a RAM
7 does not have to be provided and may be an independent memory or register, or a non-volatile R
It may be provided in AM.

The alarm ringing means 14 used in this embodiment is a piezoelectric buzzer. However, the alarm ringing means is not limited to this. For example, there is no particular limitation as long as it vibrates at a predetermined vibration frequency to notify the operator, such as an acoustic speaker, a bell, a tuning fork, and a vibrator.

The switch group 11 is a push-type switch installed in the main body of an electronic timepiece (not shown) and operated by the operator. Further, it is composed of two addition switches having a setting time addition function and a subtraction switch having a setting time subtraction function. Of course, in the electronic timepiece, various switches can be provided in addition to these, and they can be appropriately installed according to the function of the electronic timepiece. In this embodiment, the push-type switch is used as the switch, but the switch is not limited to this. For example, a slide type switch or a touch type switch can be applied. Also,
The switch group 11 may be provided in addition to the main body of the electronic timepiece.
For example, it may be a remote control switch, or an input device such as a keyboard, pen, or mouse of an electronic device such as a computer connected to an electronic timepiece.

Now, the operation of the embodiment of the electronic timepiece according to the present invention will be described with reference to the flow chart.

FIG. 3 is a block diagram showing a first embodiment of the electronic timepiece according to the present invention. In the figure, the input control means 102 for detecting the input state of the two switches 211 for addition and subtraction is connected to the input time counting means 103. The input time counting means 103 is the frequency dividing means 1
Based on the output clock signal of 01, the time during which continuous input of the same switch is detected is counted. Further, the input time counting means 103 is connected to the input time detecting means 104, and the input time detecting means 104 detects that the value of the input time counting means 103 has reached a predetermined value. Input time detecting means 10
Reference numeral 4 is connected to the setting control unit 105, and the frequency dividing unit 1
The setting increment / decrement amount of the time unit set value for every fixed time based on the output clock signal 01 is changed according to the input time detecting means 104. The adding means 302 and the subtracting means 303 are connected to the setting adjustment control means 105, and are stored in the setting value storage means 208 (corresponding to the setting value storage memory 8 shown in FIG. 2) according to the output of the setting adjustment control means 105. Adds or subtracts the specified value. Addition is performed when the addition switch is operated, and subtraction is performed when the subtraction switch is operated. The content of the set value storage means 208 is the display control means 30.
5 is displayed on the LCD panel 306.

The operation shown in the above block diagram (FIG. 3) will be specifically described with reference to the flowchart of FIG. 4 and the timing chart of FIG. It should be noted that what will be described below is the operation at the time of addition. Since the operation at the time of subtraction is the same as the operation at the time of addition, it will be omitted.

Now, the frequency dividing means 101 operates with the falling count of the clock, and the interrupt control circuit 20 shown in FIG.
It is assumed that 4 is set to generate an interrupt in synchronization with the falling edge of the 1 Hz or 16 Hz clock signal of the frequency dividing means 101. In addition, the set value for time setting is the hour / minute setting type alarm time, 1 minute is added by the rising edge of the addition switch, and 1 to 2 seconds after continuous input is detected, 8 Hz for 4 seconds during continuous input It is assumed that 1 minute is added every 1 minute, 16 Hz is added every 1 minute for 4 seconds, 16 Hz is added every 2 minutes for 4 seconds, and 4 minutes is added every 16 Hz thereafter.

When an interrupt occurs in synchronization with the falling edge of the internal clock signal of 16 Hz or 1 Hz and the alarm can be set, the program stored in the ROM 6 shown in FIG. 2 according to the flowchart shown in FIG. Operate. That is, it is 1 when the alarm can be set.
This program runs every 6 Hz. In the initial state, the alarm time is first set to 1:59 and the addition switch is not input.

First, it is detected whether or not the addition switch is input (step 401), and since it is not input in the initial state, the operation of this program ends. On the other hand, as shown in the timing chart of FIG. 5A, when this program operates after the addition switch is input (timing a), after the addition switch input is detected (step 401), whether the input is a rising edge or not. Is detected (step 402). In this case, since it is the rising edge, 1 minute is added (step 40
3) The alarm time is set to 2:00, the K value for counting the input time is reset to 0 (step 404), the display is performed (step 416), and the program ends.

During the program operation by the next 16 Hz interrupt (timing b in FIG. 5), similarly after the input of the addition switch is detected (step 401), it is detected whether the input is a rising edge (step 402). However, this time, since it is not the rising edge input, it is judged whether or not the 1 Hz interrupt is simultaneously applied with the 16 Hz interrupt (step 405). In this case, since the 1 Hz interrupt is not applied at the timing b in FIG. 5, it is next determined whether the K value is less than 2 (step 4).
07). Since the K value is 0 at the timing b, the program ends.

During the program operation by the next 16 Hz interrupt (timing c in FIG. 5), the input of the addition switch is detected (step 401), the rising edge of the input is detected (step 402), and the 1 Hz interrupt is detected (step 402). Step 405). Since the 1 Hz interrupt is being applied this time, the K value is incremented by 1 to set the K value to 1 (step 406) and it is determined whether the K value is less than 2 (step 407). At timing c, the K value is 1, so the program ends without doing anything.

Thereafter, the same operation as the timing b is repeated 15 times. Then, at the timing d, the input of the addition switch is detected (step 401), whether the input is on the rising edge (step 402), the 1 Hz interrupt is detected (step 405), and the 1 Hz interrupt is applied. The value is incremented by 1, and the K value is set to 2 (step 406). Next, when it is determined whether the K value is less than 2 (step 407), the K value is 2 at the timing d.
Then, it is determined whether the K value is 2 or more and less than 6 (step 408). Since the K value is 2, the process proceeds to step 409. In step 409, the contents of the frequency dividing means 101 are read out and it is judged whether or not the 8 Hz signal is L (Low level). Since the 8 Hz signal is L now, one minute is added to set the alarm time to 2:01 (step 410), display is performed (step 416), and the program ends.

At the next timing e, the input of the addition switch is detected (step 401), whether the rising edge of the input is detected (step 402), the 1 Hz interrupt is detected (step 405), and the 1 Hz interrupt is not applied. Therefore, it is next determined whether the K value is less than 2 (step 407). Since the K value is 2 at timing e, it is next determined whether the K value is 2 or more and less than 6 (step 408). Since the K value is 2 now, the process proceeds to step 409.
However, this time, since the 8 Hz signal is H (High level), the program ends as it is.

At timing f, the addition switch input is detected (step 401), whether the input is a rising edge (step 402), 1 Hz interrupt is detected (step 405), and the 1 Hz interrupt is not applied. It is determined whether the K value is less than 2 (step 407). Since the K value is 2 at timing e, it is next determined whether the K value is 2 or more and less than 6 (step 40
8) Since the K value is 2 now, the process proceeds to step 409. Since the 8 Hz signal is L this time as well as the timing d, 1 minute is added to set the alarm time to 2:02 (step 410) and display is performed (step 416). Exit the program.

Thereafter, 16 Hz during the period when the K value is 2 or more and less than 6
The operations at timings d, e, and f are repeated depending on the interrupt status of the signal and the 1 Hz signal. Therefore, the alarm time is incremented by 1 minute every 8 Hz for 4 seconds when the K value is 2 or more and less than 6, that is, at a rate of 8 minutes per second, and the time display is updated each time. And for the initial setting time value 1:59,
When the switch input rises, 33 minutes are added together with 1 minute and the time reaches 2:32.

Incidentally, step 40 in the flow chart of FIG.
Although the determination of 8 Hz of 9 is performed by reading the 8 Hz signal of the frequency dividing means in the above method, another method may be used. Since this program operates every 16 Hz, for example, 16
The Hz signal may be binary-counted, and when it is 0, 1-minute addition (step 410) processing may be performed, and when it is 1, the addition processing may not be performed and the program may be ended as it is.

FIG. 5B is a timing chart when the K value becomes 6 by repeating the above operation and when the K value is 6 or more and less than 10 during operation. At timing g, the input of the addition switch is detected (step 40
1), the rising edge of the input is detected (step 402), the 1 Hz interrupt is detected (step 405), and since the 1 Hz interrupt is being applied, the K value is incremented by 1 and the K value is set to 6 (step). 406). Then, after determining whether the K value is less than 2 (step 40
7) and determine whether the K value is 2 or more and less than 6 (step 4
08), since the K value is 6, the process proceeds to step 411. In step 411, it is determined whether the K value is 6 or more and less than 10,
Since the K value is now 6, add 1 minute and set the alarm time to 2:33.
(Step 412) and display (step 41
6) End the program.

At the timing h, the input of the addition switch is detected (step 401), whether the input is on the rising edge (step 402), the 1 Hz interrupt is detected (step 405), and the 1 Hz interrupt is not applied. Determine if the value is less than 2 (step 4
07), it is determined whether the K value is 2 or more and less than 6 (step 4
08), the K value is now 6, so the process proceeds to step 411. In step 411, it is determined whether the K value is 6 or more and less than 10, and the K value is now 6, so 1 minute is added and the alarm time is set to 2:
34 (step 412) and display (step 4
16) Exit the program.

Thereafter, 16H is set for the period when the K value is 6 or more and less than 10.
The operation at timings g and h is performed depending on the state of z or 1 Hz interrupt. Therefore, the alarm time is incremented by 1 minute every 16 Hz for 4 seconds when the K value is 6 or more and less than 10, that is, at a rate of 16 minutes per second, the display time is updated each time, and the alarm time reaches 3:36. .

In FIG. 5C, when the K value becomes 10 by repeating the above operation, and when the K value is 10 or more 14
It is a timing chart at the time of operation of a period of less than.

At the timing i, the input of the addition switch is detected (step 401), whether the input is a rising edge (step 402), the 1 Hz interrupt is detected (step 405), and the 1 Hz interrupt is applied. Add 1 to 10 (step 40
6), determine whether the K value is less than 2 (step 407),
After determining whether it is 2 or more and less than 6 (step 408) and determining whether it is 6 or more and less than 10 (step 411), since the K value is now 10, the process proceeds to step 413. In step 413, it is determined whether the K value is 10 or more and less than 14, and the K value is 1 now.
Since it is 0, two minutes are added to set the alarm time to 3:38 (step 414), and the display is performed (step 416), and the program ends.

At timing j, the input of the addition switch is detected (step 401), whether the input is a rising edge (step 402), the 1 Hz interrupt is detected (step 405), and the 1 Hz interrupt is not applied. Determine if the value is less than 2 (step 4
07) It is determined whether it is 2 or more and less than 6 (step 40
8), it is determined whether 6 or more and less than 10 (step 41
1) It is judged whether it is 10 or more and less than 14 (step 41
3) Since the K value is now 10, the two minutes are added to set the alarm time to 3:40 (step 414), display is performed (step 416), and the program ends.

Thereafter, the period when the K value is 10 or more and less than 14 is 16
The operation at timing i, j is performed depending on the state of Hz or 1 Hz interrupt. Therefore, the alarm time is added every 2 minutes at 16 Hz for 4 seconds when the K value is 10 or more and less than 14, that is, at a rate of 32 minutes per second, and the display is updated at 5:44.
To reach. In this case, the addition effect is substantially the same as the addition effect at a rate of 1 minute every 32 Hz,
In the case of the present embodiment, addition processing and display processing are performed only every 16 Hz.

FIG. 5D is a timing chart when the K value becomes 14 by repeating the above operation and when the K value is 14 or more during operation.

At timing k, the input of the addition switch is detected (step 401), whether the input is a rising edge (step 402), the 1 Hz interrupt is detected (step 405), and the 1 Hz interrupt is applied. Add 1 to 14 (step 40
6), determine whether the K value is less than 2 (step 407),
After determining whether it is 2 or more and less than 6 (step 408) and determining whether it is 6 or more and less than 10 (step 411), since the K value is now 14, the alarm time is set to 5:48 by adding 4 minutes (step 414) and displayed. (Step 416) to end the program.

At the timing l, the input of the addition switch is detected (step 401), whether the input is a rising edge (step 402), the 1 Hz interrupt is detected (step 405), and the 1 Hz interrupt is not applied. Determine if the value is less than 2 (step 4
07) It is determined whether it is 2 or more and less than 6 (step 40
8), it is determined whether 6 or more and less than 10 (step 41
1) It is judged whether it is 10 or more and less than 14 (step 41
3) Since the K value is now 14, the four minutes are added to set the alarm time to 5:52 (step 414), the display is performed (step 416), and the program ends.

After that, when the K value is 14 or more, the operation at timings k and l is performed depending on the state of 16 Hz or 1 Hz interrupt. Therefore, when the K value is 14 or more, the alarm time is added every 16 Hz for 4 minutes, that is, at the rate of 64 minutes per second, and the display time is updated each time. In this case, the addition effect is substantially the same as that obtained by adding at a rate of 1 minute every 64 Hz, but in the present embodiment, addition processing and display processing are performed only every 16 Hz as described above. .

Since the operation at the timings k and l is repeated after the K value reaches 14, it is not necessary to add the K value as shown in FIG. In addition, in the first embodiment, the case where the set addition amount is up to quartet addition has been described, but it goes without saying that the addition may be performed at a ratio higher than this. As an example, 8 minutes, 10 minutes, 16 minutes, 20
Minutes, 30 minutes, 60 minutes, etc. Further, various patterns can be used for changing the added value. For example, first add 1 minute, then 2 minutes, 5 minutes, 10
Minutes.

However, among them, it is most preferable to change by 2 ⁿ times such as 1, 2, 4, and 8. This is because the rate of change is the most comfortable feeling for the operator. That is, since the amount of change in the added value is always doubled and constant, the operator can easily infer how the added value changes and can set the time with confidence. Further, even if the set time digit (minute digit in this embodiment) changes discontinuously, the upper digits of the set time digit (10 minute digit, hour digit, etc. in this embodiment) are Since it changes continuously, the operator feels good (no discomfort).

Further, in this example, when the K value for counting the switch input time is relatively small, the fast-forward speed is not so high. This is because it is assumed that the time is set relatively close to the preset alarm time. That is, when the time is set to a relatively close time, the fine time setting work is started immediately after operating the switch. If you fast forward from the beginning, you may pass the time you want to set immediately.

On the other hand, in the case of this example, since the amount of adjustment is changed, it is effective even when the time is set relatively far from the preset alarm time. In other words, this example can be set quickly and accurately for any time from a relatively close time to a relatively far time.

Next, a second embodiment of the present invention will be described. In the present embodiment, the addition / subtraction amount itself of the set value in units of time is not changed as in the first embodiment, but the digit of the time of addition / subtraction is changed.
As a result, the amount of fast-forward addition / subtraction is substantially changed.

FIG. 9 is a block diagram showing the detailed structure of the second embodiment of the electronic timepiece according to the present invention. In the figure, the input control means 702 for detecting the input state of the switch 211 is connected to the input time counting means 703. Then, the input time counting means 703 is connected to the frequency dividing means 701 and counts the time during which continuous input of the same switch is detected based on the output clock signal thereof. Further, the input time counting means 703 is connected to the input time detecting means 704, and the input time detecting means 704 detects that the value of the input time counting means 703 has reached a constant value. Up to this point, the process is the same as in the first embodiment described above.

The input time detecting means 704 is connected to the setting digit selecting means 705, and the setting digit selecting means 705 changes the selected setting digit for setting the time according to the value of the input time detecting means 704. The adding means 902 and the subtracting means 903 are connected to the setting digit selecting means 705, and the setting digit selecting means 705.
The value stored in the set value storage unit 208 is added or subtracted according to the output of the. Of the contents of the set value storage means 208,
The value of the selected digit or more is displayed on the LCD via the display control means 905.
It is displayed on the 906 panel. Digits less than the selected digit are displayed on the LCD 906 panel via the non-selected digit display control unit 801.

The operation shown in the above block diagram (FIG. 9) will be specifically described with reference to the flowcharts of FIGS. 10 and 11. It should be noted that what will be described below is the operation at the time of addition. Since the operation at the time of subtraction is the same as the operation at the time of addition, it will be omitted.

Now, the frequency dividing means 701 operates with a falling count, and the interrupt control circuit 204 shown in FIG. 2 is set so that an interrupt is generated in synchronization with the falling edge of the 1 Hz or 8 Hz clock signal of the frequency dividing means 701. It has been done. The set value for setting the time is an hour / minute setting type alarm time. One minute is added by the rising edge of the addition switch, and 1 to 2 seconds after 1 second of continuous input is detected. Add one minute every 8Hz,
For the next 4 seconds, add 10 minute digit every 8Hz, add 1 hour digit every 8Hz for 4 seconds, then add 10 hour digit 8
Add 1 for each Hz. Of course, it may be other than the hour / minute setting type, and may be the hour / minute / second setting type / year / month / day setting type / month / date / time / minute setting type.

When an interrupt is generated in synchronization with the fall of the internal clock of 8 Hz or 1 Hz and the alarm can be set, the state shown in FIG. 1 stored in the ROM 6 shown in FIG.
The program according to the flowchart shown in 0 operates. In other words, 8Hz when the alarm can be set
This program runs every time.

First, it is detected whether or not the addition switch is input (step 1001). If the addition switch is not input, the program is ended as it is.
When this program operates after the addition switch is input, after the addition switch input is detected (step 100
1), it is detected whether the switch input has a rising edge (step 1002). If it is a rising edge, select the 1-minute digit (step 1003), add 1 minute (step 1004), reset the K value for counting the input time to 0 (step 1005), and display. (Step 1020) The program ends.

When the input of the addition switch is not the edge input, it is judged whether the 1 Hz interrupt is simultaneously applied with the 8 Hz interrupt (step 1006),
If there is a 1 Hz interrupt, add 1 to the K value (step 10
07) If there is no 1 Hz interrupt, leave it as it is. Next, it is determined whether the K value is less than 2 (step 1008),
If the K value is less than 2, the program ends without doing anything. If the K value is 2 or more, then it is determined whether the K value is 2 or more and less than 6 (step 1009), and if it is 2 or more and less than 6, 1 minute digit is selected as the setting digit (step 1010),
One minute is added (step 1011) and displayed (step 1020).

If the K value is not less than 2 and less than 6, then it is determined whether the K value is 6 or more and less than 10 (step 1012).
If 6 or more and less than 10, select the 10-minute digit as the set digit (step 1013) and add 10 minutes (step 1
014), and display is performed (step 1020).

If the K value is not less than 6 and less than 10, then it is determined whether the K value is 10 or more and less than 14 (step 101
5) If 10 or more and less than 14, select the hour digit as the set digit (step 1016), add 1 hour (step 1017), and display (step 1020).

If the K value is not less than 14, the 10 o'clock digit is selected as the set digit (step 1018), 10 o'clock is added (step 1019), and the display is performed (step 102).
0). However, in setting the alarm time, the K value rarely exceeds 14 and this routine is rarely used.

The manner in which the alarm time changes according to the above flow chart will be briefly described. As a precondition, it is assumed that the initial alarm time is 1:59 and the addition switch is continuously operated to set a new alarm time. Table 1 below shows how the alarm time changes in this case.

[0067]

[Table 1]

As can be seen from this table, the present embodiment is very effective both when the time is set relatively close to the preset initial time and when the time is set far away. is there. In particular, since the selected digit moves sequentially in accordance with the continuous operation time of the switch, it is convenient when it is desired to set not only the hour and minute but also the month and day at the same time with one switch.

In the flowchart shown in FIG. 10, in step 1020, the digits of the selected digit or more of the alarm time, that is, the digits that may be changed are displayed as they are, and the digits less than the selected digit are blinked. It is desirable to turn off, or display any numerical value, symbol, code, or pattern. This is because there is no possibility of changing the numerical value for the time digits less than the selected digit. That is, in the case of the present embodiment, the time digit once selected is never selected again as long as the switch is continuously operated. Therefore, in consideration of the operability of the operator, it is preferable that the display of the time digit less than the selected digit is different from the display of the time digit greater than the selected digit.

In addition, in step 1020 described above, all the displays are made at the same time, but the digits above the selected digit and the digits below the selected digit may be displayed at different frequencies.

In FIG. 11, the display is divided into a digit higher than the selected digit and a digit less than the selected digit and displayed at different frequencies (frequency). In this case, it is assumed that the program shown in the flowchart of FIG. 10 operates by interruption every 1 Hz and 32 Hz. That is, the program is executed four times as frequently as the program execution frequency described above. In FIG. 11, after the process of step 1002 in the flowchart of FIG. 10, first, the number of digits below the selected digit is displayed (step 1101). And then 8Hz
The signal is read, and if the 8 Hz signal is L (Low level), the process returns to step 1006 to perform addition processing, and H (High level)
level), the program ends as it is.

According to this method, the time digits below the selected digit are changed and displayed every 32 Hz, but the time digits above the selected digit are changed and displayed every 8 Hz. Therefore, the time digits less than the selected digit and the time digits greater than or equal to the selected digit have different appearances, so that the operator can easily identify the selected digit. Furthermore, since the change frequency of the display of the time digits less than the selected digit is as high as 32 Hz, the operator does not know what kind of display is displayed,
Don't worry about it. As a result, it is possible to concentrate on the time setting operation of the digit which is the selected digit or more.

In this example, the display of the time digits less than the selected digit is made different from that of the selected digit, but the time digits other than the selected digit are controlled to be displayed in the same manner as the time digits less than the selected digit. May be. As a result, the time setting operation for the selected digit can be intensively performed. However, since the carry of the selected digit occurs, it is desirable that at least the selected digit and the time digit immediately above the selected digit be different from the display of the time digits less than the selected digit.

Further, in the present example, when the selected digit is switched, the alarm bell means may be used to notify the operator that the selected digit has changed. In the case of this example, the bell rings every 4 seconds, which further improves the operational feeling for the operator.

In this embodiment, the interrupt process is performed for each 16 Hz or 8 Hz clock signal, but of course the invention is not limited to this. There is no particular limitation as long as the operator feels fast-forwarding and the timing is such that the time can be set accurately and quickly. Above all, it is preferable to use a signal of about 4 Hz to 16 Hz. If the interrupt frequency is too low, the fast-forward speed will slow down and it will take time to set the time. Further, if the interrupt frequency is too high, the change of the numerical value is too fast, and it becomes more difficult for the operator to set the time accurately. However, it is necessary to consider the software processing time for the addition / subtraction processing. If the interrupt frequency is too high, the software load will be heavy and it may not be possible to process within one cycle of the interrupt, and it may not be possible to fast forward at a stable speed, so be careful.

Further, in the present embodiment, the addition and subtraction fast-forwarding of the time is carried out by using the two switches for addition and subtraction, but the fast-forwarding is carried out by using only one of the addition and subtraction switches. Good. That is, the time is set only by addition (or subtraction).
However, in this case, the operator needs to be careful not to overshoot the time to be set. However, in the case of the present invention, since the operator does not feel uncomfortable, there are very few operation mistakes when setting the time, as compared with the conventional time setting method.

Further, although the method of setting the alarm time has been described in the present embodiment, the present invention is not limited to this. In addition to the alarm time, the basic clock time (current time, world time, etc.) and reserved time (operation / stop time of electronic devices that operate in conjunction with the electronic clock),
For example, it may be a timer time, reserved recording / recording time), or the like.

The time setting method of the present invention can be applied to any electronic timepiece as long as the time is set by fast-forwarding. In particular, since the electronic timepiece of the present invention consumes less power and has a very simple structure, it is most suitable for portable electronic timepieces such as wristwatches and pocket watches that are driven by batteries and require a small electronic circuit. It can be utilized preferably.

[0079]

As described above, the present invention has the following effects.

According to the first, fourth, eighth and eleventh aspects of the present invention, the time can be set reliably and quickly at a stable fast-forward speed. Further, it is possible to set the time with a good operation feeling. In addition, it is possible to realize an electronic timepiece that does not cause unnecessary increase in current consumption and does not place an excessive burden on the software of the time control means such as a microcomputer.

According to the second and ninth aspects of the invention, the frequency dividing circuit is changed at a rate of ± 2 ⁿ (n is an integer of 1 or more), which is usually used as an electronic timepiece, so that the configuration of the frequency ^dividing circuit is simplified. Therefore, the circuit of the electronic timepiece can be effectively used. Further, the operator can perform the time setting operation without feeling uncomfortable.

According to the third and tenth aspects of the present invention, the most suitable operation feeling of the operator can be obtained by using the clock signal of 1 Hz for detecting the continuous input time of the switch. In addition, the load on the software for time detection can be optimized.

According to the fifth and the twelfth aspects of the present invention, there is an effect that the user does not feel uncomfortable in use without changing the numerical value of the non-selected digit (for example, the lower digit of the selected setting digit). Then, as in the inventions according to claims 6 and 13, it becomes easier to visually understand by blinking or turning off the light.

According to the invention described in claims 7 and 14, there is an effect that it is possible to understand at a glance what kind of time is being set, and an effect that the operation can be performed with a smooth operation feeling without discomfort.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an electronic timepiece according to the invention.

FIG. 2 is a hardware configuration diagram showing an embodiment of the electronic timepiece of the invention.

FIG. 3 is a block diagram showing a more detailed configuration of the first aspect of the electronic timepiece of the invention.

FIG. 4 is a flowchart showing an example of a first mode of the electronic timepiece of the invention.

FIG. 5 is a timing chart showing an embodiment of the first mode of the electronic timepiece of the invention.

FIG. 6 is a supplementary flowchart of FIG. 4 showing a process when a switch is operated for a long time.

FIG. 7 is a block diagram showing a configuration of a second mode of an electronic timepiece according to the invention.

FIG. 8 is a block diagram showing a configuration of a second embodiment of an electronic timepiece of the invention to which a non-selected digit display control means is added.

FIG. 9 is a block diagram showing a more detailed configuration of a second aspect of the electronic timepiece of the invention.

FIG. 10 is a flowchart showing an example of a second mode of the electronic timepiece of the invention.

11 is a supplementary flowchart of FIG. 10 showing an example of display control by the non-selected digit display control means.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Microcomputer 2 ... Oscillation circuit 3 ... Frequency divider circuit 4 ... Interrupt control circuit 5 ... Control circuit 6 ... ROM 7 ... RAM 8 ... Set value storage memory 9 ... Display control circuit 10, 306, 906 ... LCD panel 11 ... Switch group 12 ... Input control circuit 13 ... Alarm control circuit 14 ... Alarm ringing means 15 ... Internal Bus 101, 701 ... Frequency dividing means 102, 702 ... Input control means 103, 703 ... Input time counting means 104, 704 ... Input time detecting means 105 ... Setting adjustment control means 106, 706 ... Original vibration 107, 211, 707 ... Switch 208 ... Setting value storage means 302, 902 ... Addition means 303, 903 ... Subtraction means 305, 905 ... Display Control means 705 ... Setting digit selection means 701 ... Reset time counting means 801 ... Non-selected digit display control means

Claims (14)

[Claims] 1. A frequency dividing means for frequency-dividing an original vibration to generate a clock signal, (b) Input control means for detecting a switch input for setting time, and (c) the frequency-dividing. Input time counting means for counting the time during which the input control means detects continuous input of the same switch using the clock signal of the means, and (d) the value of the input time counting means has reached a predetermined value. And (e) forming a fixed time based on the clock signal of the frequency dividing means, and according to the output of the input time detecting means, a time unit set value for each fixed time. An electronic timepiece comprising: a setting adjustment control means for changing the setting adjustment. 2. The set amount of increase / decrease control means sets the set amount of increase / decrease to ± 1 unit initially, and thereafter, after a predetermined time according to the output of the input time detection means, ± 2 ⁿ (n is 1). The electronic timepiece according to claim 1, wherein the electronic timepiece is changed at a ratio of the above integer) units. 3. The input time detecting means counts the 1 Hz clock signal of the frequency dividing means, and the setting adjustment control means operates every 8 Hz or 16 Hz clock signal of the frequency dividing means. Item 1. An electronic watch according to item 1. 4. (a) Frequency dividing means for dividing the original vibration to generate a clock signal, (b) Input control means for detecting a switch input for setting time, and (c) The frequency dividing. Input time counting means for counting the time during which the input control means detects continuous input of the same switch using the clock signal of the means, and (d) the value of the input time counting means has reached a predetermined value. An electronic timepiece having an input time detecting means for detecting the time, and (e) setting digit selecting means for selecting a time setting digit for time setting according to the output of the input time detecting means. 5. The electronic timepiece according to claim 4, further comprising non-selected digit display control means for displaying an arbitrary value for digits other than the time setting digit selected by the setting digit selecting means. 6. The electronic timepiece according to claim 4, further comprising non-selected digit display control means for blinking or extinguishing digits other than the time setting digit selected by the setting digit selecting means. 7. The electronic timepiece according to claim 5, wherein the non-selected digit display control means operates at a speed higher than the operation speed of the display means operated by the set digit selection means. 8. A continuous input time of a switch input is counted by using a clock signal generated by a frequency dividing means for dividing the original vibration, and a time unit is set at regular time intervals according to the count value of the continuous input time. A time setting method characterized by changing the time by changing the set amount of the value. 9. The time unit setting value is adjusted, and the setting adjustment amount is initially set to ± 1 unit.
9. The time setting method according to claim 8, wherein the time is changed at a rate of ± 2 ⁿ (n is an integer of 1 or more) after a predetermined time. 10. The continuous input time of the switch input is counted using the 1 Hz clock signal of the frequency dividing means, and
Calculation of the set amount of the time unit set value is performed by the frequency dividing means 8
9. The time setting method according to claim 8, wherein the setting is performed for each Hz or 16 Hz clock signal. 11. The time setting method according to claim 8, wherein the set amount of the time unit set value for each fixed time is changed by selecting a time set digit for performing time setting. 12. The time setting method according to claim 11, wherein digits other than the selected time setting digit are displayed as arbitrary values. 13. The time setting method according to claim 11, wherein digits other than the selected time setting digit are blinked or turned off. 14. The time setting method according to claim 12, wherein the digits other than the selected time setting digit are displayed at a speed higher than the display speed of the selected time setting digit.