JP5212326B2 - Analog electronic clock - Google Patents

Description

  The present invention relates to an analog electronic timepiece having a pointer and a step motor for driving the pointer.

  In analog electronic timepieces that move the hands by driving the hands with a stepping motor (also called a stepping motor), when the information pointed to by the hands is switched by function selection, or when the hands are returned to the reference position or predetermined For example, when advancing to the time position, the step motor is driven at high speed and the pointer is fast-forwarded.

  Further, in an analog electronic timepiece in which a plurality of system hands are driven by a plurality of step motors, the fast feed speed set for each step motor is, for example, 64 pps (pulse per second) or 16 pps. May be different.

  In a conventional analog electronic timepiece, when a plurality of step motors are driven at high speed to rapidly feed a plurality of hands, first, the first step motor is fast-fed to fast-forward the first hand, When this is completed, there is a system that employs a system in which a plurality of step motors are driven in rapid traverse in order, for example, the second step motor is fast-forward driven to rapidly feed the second system pointer. In addition, when the same fast-forwarding speed is set for a plurality of step motors, there has been a system that simultaneously drives the plurality of step motors to fast-forward a plurality of pointers together.

  In addition, as a technique related to the present invention, Patent Document 1 discloses that when two motors are driven and two systems of pointers are simultaneously fast-forwarded, only one system of pointers is fast-forwarded so as not to cause power shortage. A technique is disclosed in which two motors are simultaneously driven at a fast feed speed that is one step lower than that in the case of making them.

JP 60-162980 A

  When a plurality of stepping motors are fast-forwarded to rapidly feed a plurality of pointers, if the fast-forwarding is performed sequentially for each one-way pointer, there is a problem that the entire time of the fast-forwarding process becomes long.

  In order to shorten the fast-forward processing time, it is also possible to adopt a method in which multiple stepping motors are driven simultaneously in parallel at different fast-forwarding speeds set for each to simultaneously fast-forward multiple hands. It is done. However, in general, in order to drive the step motor at a predetermined fast feed speed, it is necessary to generate a timing signal corresponding to the fast feed speed to control the drive timing of the step motor. Therefore, when multiple step motors are driven simultaneously in parallel at different fast feed speeds, multiple timing signals with different periods are generated and multiple timing controls are performed in parallel. The problem of becoming.

  An object of the present invention is to provide an analog electronic timepiece that can complete fast-forwarding of a hand in a short time without complicating the configuration of timing control when driving a plurality of stepping motors to fast-forward a plurality of hands. It is to provide.

In order to achieve the above object, the invention according to claim 1
The first guideline,
A first step motor driven at a predetermined cycle to fast-forward the first pointer;
The second guideline,
A second step motor driven at a cycle of N times the predetermined cycle (N is an integer of 2 or more) to fast-forward the second pointer;
Timing detection means for detecting the timing of the predetermined period;
The first step motor is driven every time the timing of the predetermined period is detected by the timing detection means, and the second step is performed every time the timing of the predetermined period is detected by the timing detection means. An analog electronic timepiece having fast-forward drive control means for driving a motor.

The invention according to claim 2 is the analog electronic timepiece according to claim 1,
Timing signal generating means for generating a timing signal of the predetermined period;
The timing detection means detects the timing of the predetermined period based on the timing signal of the timing signal generation means.

The invention according to claim 3 is the analog electronic timepiece according to claim 1,
The fast-forward drive control means includes
When the first pointer and the second pointer are both fast-forwarded, the first step motor is driven each time the timing of the predetermined period is detected by the timing detection unit, and the timing detection unit Driving the second step motor every time the timing of the predetermined period is detected N times,
When continuing the fast feed of the second pointer after the first pointer reaches a predetermined position, the driving of the first step motor is stopped and the timing of the predetermined cycle is set to N by the timing detection means. The second step motor is driven every time it is detected.

The invention according to claim 4 is the analog electronic timepiece according to claim 2,
The timing signal generating means includes
The generation period of the timing signal can be switched between the predetermined period and a period N times the predetermined period,
The timing detection means includes
By switching the generation period of the timing signal of the timing signal generating means, it is possible to detect the timing of a period N times the predetermined period,
The fast-forward drive control means includes
When both the first pointer and the second pointer are fast-forwarded, the timing signal generating unit generates the timing signal of the predetermined period, and the timing detecting unit detects the timing of the predetermined period. Driving the first step motor, and driving the second step motor each time the timing of the predetermined period is detected N times by the timing detection means,
When continuing the fast feed of the second pointer after the first pointer reaches a predetermined position, the generation period of the timing signal of the timing signal generating means is switched to a period N times the predetermined period, The second step motor is driven each time the timing detection unit detects a timing having a period N times the predetermined period.

The invention according to claim 5 is the analog electronic timepiece according to claim 1,
The fast-forward drive control means includes
When both the first step motor and the second step motor are driven, the first and second steps are output to the first step motor and the second step motor by shifting the drive time, respectively. It is characterized by driving a motor.

The invention according to claim 6 is the analog electronic timepiece according to claim 1,
A plurality of pointers including at least the first pointer and the second pointer;
A plurality of step motors including at least the first step motor and the second step motor, wherein the plurality of hands are driven, and each fast-forward driving cycle is set to a natural number multiple of the predetermined cycle. And
The fast-forward drive control means includes
When the plurality of hands are fast-forwarded together, the timing detection unit detects the timing of the predetermined cycle every time a multiple of the driving cycle for fast-forwarding of each step motor based on the predetermined cycle is detected. Of the step motors, the corresponding step motor is driven.

The invention according to claim 7 is the analog electronic timepiece according to claim 1,
Instead of the second pointer, a symbol is provided on the front surface, and a rotating disk is provided that rotates with at least a portion exposed on the dial.

  According to the present invention, the first step motor and the second step motor having different driving cycles are driven in parallel, and the first and second hands are fast-forwarded. Fast forward can be completed. Furthermore, since the fast-step drive control is performed by distinguishing the drive timing of the first step motor and the drive timing of the second step motor according to the number of times the timing detection means detects the timing of the predetermined period, the structure of the timing control is Not so complicated.

It is a front view which shows the external appearance structure of the analog electronic timepiece of embodiment of this invention. It is a block diagram which shows the whole structure of an analog electronic timepiece. It is a chart showing the fast feed speed of each step motor and the number of moving steps of each step motor in an example of the fast feed operation. It is a time chart explaining the control pattern of each step motor in an example of fast-forward operation. It is a flowchart which shows the control procedure of the fast-forward setting process performed before a fast-forward process. It is the first half part of the flowchart which shows the control procedure of the interruption process including the step of a fast-forward process. This is the latter half of the flowchart. It is a time chart explaining the control pattern of each step motor in the modification of fast-forwarding processing. It is a flowchart which shows the modification of the interruption process including the step of a fast-forward process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a front view showing an external configuration of an analog electronic timepiece according to an embodiment of the present invention.

  As shown in FIG. 1, the analog electronic timepiece 1 of this embodiment is provided with a dial 5 on the inner side surrounded by an outer casing 10 and a windshield on the front, and an hour hand 2 and a minute hand on the dial 5. 3, the second hand 4, the 24-hour hour hand 12, the 24-hour minute hand 13, and the 1/10 second hand 15 are arranged so as to be rotatable. A date wheel 18 as a rotating disk is rotatably provided on the back side of the dial 5, and a part of the date is exposed to the outside from the opening 17 of the dial 5. Further, four operation buttons B1 to B4 are provided on the side surface of the casing 10.

  The hour hand 2, the minute hand 3, and the second hand 4 are rotated over almost the entire area of the dial 5, while the 24-hour hour hand 12 and the 24-hour minute hand 13 are rotated in a small window 11 provided at the 3 o'clock position of the dial 5. The 1/10 second hand 15 is configured to rotate within a small window 14 provided at the 9 o'clock position of the dial 5.

  The hour hand 2, the minute hand 3, and the second hand 4 normally indicate the current time, but by switching the operation mode of the clock, for example, the alarm setting time is indicated, or various operation states are indicated by the second hand 4. Or Alternatively, it may be returned to the reference position (0 hour 0 minute 0 second position) to correct the pointer position. In addition, the 24-hour hour hand 12 and the 24-hour minute hand 13 may be switched from a state indicating the current time in Japan to a state indicating the current time in a designated foreign city by switching the operation mode of the clock. The 1/10 second hand 15 normally indicates the current day of the week, but when the operation mode of the watch is switched to the stopwatch mode, it moves to the reference position and stops until a start command is issued. ing. In addition, the date wheel 18 is normally stopped with the current date exposed to the opening 17, but when the date is switched, the date is switched by a predetermined number of steps, or the date is changed. In some cases, it may be fast-forwarded to a reference position (a position where the date display of “1” is exposed in the opening 17).

  FIG. 2 is a block diagram showing the overall configuration of the analog electronic timepiece 1.

  The analog electronic timepiece 1 includes a first step motor that rotates the plurality of hands 2 to 4, 12, 13, 15 and the date wheel 18, the hour hand 2, and the minute hand 3 in conjunction with each other via a wheel train mechanism 23. 21, a second step motor 22 that rotates the 24-hour hour hand 12 and the 24-hour minute hand 13 in conjunction with each other via the train wheel mechanism 24, and the 1/10 second hand 15, the second hand 4, and the date wheel 18 are connected to the train wheel mechanism 33. , 43, 53, and third to fifth step motors 31, 41, 51 that rotate independently, and a control unit 80 (timing) that incorporates a CPU (Central Processing Unit) and performs overall control of the timepiece. And a drive circuit 83 for outputting a drive pulse to the first to fifth step motors 21, 22, 31, 41, 51 based on signals from the control unit 80 and detecting means and fast-forward drive control means). 87, an oscillation circuit 88 that generates an oscillation signal with a fixed period, and a frequency signal that divides the oscillation signal to generate a reference frequency of the needle movement timing for normal time display or fast-forward control. The division / interrupt signal generation circuit 89 as a timing signal generation means, the switch unit 90 that outputs an operation signal to the control unit 80 when the above-described operation buttons B1 to B4 are pressed, and the CPU of the control unit 80 is operated. A RAM (Random Access Memory) 81 that provides a memory space, and a ROM (Read Only Memory) 82 that stores a control program executed by the CPU of the control unit 80 and control data.

  The frequency division / interrupt signal generation circuit 89 generates a signal having a predetermined frequency by dividing the oscillation signal of the oscillation circuit 88 and supplies the signal to the control unit 80. Further, the frequency division / interrupt signal generation circuit 89 is capable of switching the frequency division ratio by a command from the control unit 80, thereby enabling various switching of the frequency of the signal supplied to the control unit 80. It has become. For example, in the normal time display mode, a 1 Hz signal is generated and supplied to the control unit 80, so that the counter of the control unit 80 counts the signal of this frequency to measure the time, or the control unit 80 measures the frequency. By controlling the driving of the first to fifth step motors 21, 22, 31, 41, 51 on the basis of the above signals and the time data of the counters, the hands 2-4, 12, 13, 15 and the date indicator 18 The date and day of the week are displayed.

  Further, the frequency dividing / interrupt signal generation circuit 89 responds to the fast feed speeds of the first to fifth step motors 21, 22, 31, 41, 51, such as 64 Hz and 32 Hz, in the fast feed control described later. By generating a frequency signal and supplying it to the control unit 80, the control unit 80 may use a part or all of the first to fifth step motors 21, 22, 31, 41, 51 based on the frequency signal. A process of fast-forward driving is performed. The frequency signal of the frequency division / interrupt signal generation circuit 89 is not particularly limited, but is supplied to the control unit 80 as an interrupt signal.

  The ROM 82 has a time display process program and a switch for indicating the current date and day of the week by the hands 2 to 4, 12, 13, 15 and the date wheel 18 as a control program executed by the CPU of the control unit 80. A plurality of hands 2 to 4, 12, 13, 15 and the date indicator 18 are designated based on a program of operation input processing for switching the operation mode of the watch in response to an operation signal from the unit 90, switching of the operation mode of the watch, etc. Stores a fast-forward setting process program that performs various settings for fast-forwarding to the step position, and an interrupt process program that is executed each time an interrupt signal is input from the frequency division / interrupt signal generation circuit 89. ing. The ROM 82 stores a data table of fast-forwarding speeds set in the first to fifth step motors 21, 22, 31, 41, 51, respectively, as control data.

  FIG. 3 is a chart showing the fast feed speed of each step motor 21, 22, 31, 41, 51 and the number of moving steps of each step motor 21, 22, 31, 41, 51 in an example of the fast feed operation. .

  The first to fifth step motors 21, 22, 31, 41, 51 have the rotor parts meshed with the gear train mechanisms 23, 24, 33, 43, 53 by drive pulses sent from the drive circuits 83 to 87. It is rotated by a predetermined rotation angle (for example, 180 °). These stepping motors 21, 22, 31, 41, 51 are limited in the maximum driving speed based on the specifications of the motor itself, the meshed gear train mechanisms 23, 24, 33, 43, 53 and the driving pulse specifications. The maximum driving speed at which the pointer can be fast-forwarded stably and efficiently is preset as the fast-forward speed.

  As shown in the column of “maximum fast feed speed” in FIG. 3, for example, the fast feed speeds of the first, second, and fourth step motors 21, 22, and 41 are 64 pps (pulse per second, the number of drive steps per second). The fast feed speed of the fifth step motor 51 is set to 32 pps, and the fast feed speed of the third step motor 31 is set to 16 pps. These set values are stored in the fast feed speed data table of the ROM 82.

  In this embodiment, the rapid feed speeds of the step motors 21, 22, 31, 41, 51 are in a ratio relationship of 4: 4: 1: 4: 2, that is, when any two are selected, the rapid feed speeds of each other are selected. Is set to be an integer multiple or its inverse multiple.

  Next, an example of a fast-forwarding operation for fast-forwarding the hands 2 to 4, 12, 13, 15 and the date indicator 18 to a designated step position will be described.

  In FIG. 4, the time chart explaining the control pattern of each step motor in an example of fast-forward operation | movement is shown.

  An example of this fast-forward operation is to drive each step motor 21, 22, 31, 41, 51 by the number of steps indicated in the “number of moving steps” column of FIG. In the fast-forward control of this embodiment, when all or any one of the first to fifth step motors 21, 22, 31, 41, 51 is the subject of fast-forward control, it is the subject of fast-forward control. A plurality of step motors are driven simultaneously and in parallel at a fast feed speed set for each. For example, as shown in FIG. 4, when all of the five step motors 21, 22, 31, 41, 51 are the targets of the fast-forward control, the five step motors 21, 22, 31, 41, 51 are included. Are driven simultaneously and in parallel at the fast feed speed set for each.

  Timing control for simultaneously driving a plurality of step motors at different rapid feed speeds in parallel is performed as follows. That is, first, by the frequency dividing / interrupt signal generation circuit 89, the fastest fast feed speed among the stepping motors to be driven (in the example of FIG. 4, the first, second, and fourth stepping motors 21, 22, 41). An interrupt signal having a period corresponding to 64pps) is generated. In FIG. 4, the input timing of the interrupt signal is indicated by t1 to t11.

  The step motors 21, 22, and 41 for which the fastest feed speed is set are driven step by step each time one of the interrupt signals is input. On the other hand, for the step motors 31 and 51 having a slow rapid feed speed, the above interrupt signal is counted, and this interrupt signal is counted a predetermined number of times (four times for the third step motor 31 in the example of FIG. Each time the motor 51 is input, it is driven by one step.

  The number of counts of the interrupt signal is the number of times corresponding to the reciprocal of the ratio of the fast-forwarding speed (for example, 32 pps) of the target step motor based on the fastest fast-forwarding speed (for example, 64 pps) among the driven step motors (for example, 2 Times). Since the fast feed speeds of the step motors 21, 22, 31, 41, 51 are in an integer multiple or a reciprocal multiple of each other, the count number of the interrupt signal is a number represented by an integer of 2 or more. It becomes.

  According to such fast-forward control, as shown in FIG. 4, the first, second, and fourth step motors 21, 22, and 41 for which the fastest fast-forward speed “64pps” is set are set to 64Hz. Are driven one step at each input timing t1 to t11 of the interrupt signal. Further, the third step motor 31 for which the slow fast feed speed “16 pps” is set is driven step by step at the timings t1, t5, and t9 of 16 Hz where the interrupt signal is inputted four times, and the slow fast feed speed “ The fifth step motor 51 in which “32 pps” is set is driven step by step at 32 Hz timings t1, t3, t5, t7, and t9 when the interrupt signal is input twice. That is, a plurality of step motors 21, 22, 31, 41, 51 having different fast-forward speeds are respectively controlled by timing control based on one type of interrupt signal generated at a frequency corresponding to the fastest fast-forward speed. It is designed to be driven at the set fast feed speed.

  Then, such timing control is continued, and each step motor 21, 22, 31, 41, 51 is driven by the number of movement steps specified for each, and the fast-forward control is completed. In this embodiment, after the driving of the step motors 21, 22, 41 for which the fastest fast-forwarding speed is set is completed, the driving of the step motors 31, 51 for which the slow-forwarding speed is set remains. Even in such a case, the above timing control can be continued without changing the interrupt signal generation cycle.

  In the fast-forward control described above, when all or any of the step motors 21, 22, 31, 41, 51 are simultaneously driven based on the same interrupt signal, as shown in FIG. Control is performed so that the drive pulses are output to the stepping motors 21, 22, 31, 41, 51 at different timings. With this control, even when a plurality of step motors 21, 22, 31, 41, 51 are driven together, it is possible to avoid the power supply voltage from greatly decreasing due to overlapping of drive current output periods.

  Next, the control process related to the fast-forward operation will be described in detail using a flowchart.

  FIG. 5 shows a flowchart of the fast-forward setting process executed by the CPU of the control unit 80.

  This fast-forward setting process is started by the CPU of the control unit 80 when the first to fifth step motors 21, 22, 31, 41, 51 need to be fast-forwarded due to switching of the operation mode of the timepiece or the like. Is done. When this fast-forward control process is started, the number of moving steps for fast-forward driving the first to fifth step motors 21, 22, 31, 41, 51 is specified by other control processes.

  When the control process of the fast-forwarding operation is started, the CPU sequentially sets various variables and flags shown below. That is, in step S1, the number of movement steps for fast-forward driving the first to fifth step motors 21, 22, 31, 41, 51 designated by other control processes is confirmed, and the number of movement steps is “0”. The maximum fast-forwarding speed is extracted from the fast-forwarding speeds X1 to X5 of the step motor that is not, and this is set to the variable Xm.

  In step S2, when the first to fifth step motors 21, 22, 31, 41, 51 are simultaneously fast-forwarded, the interrupt signal count indicating the drive timing of each of the step motors 21, 22, 31, 41, 51 is counted. The number of times Y1 to Y5 is calculated. That is, the value obtained by dividing the maximum value Xm of the fast-forwarding speed by the fast-forwarding speeds X1 to X5 of each step motor is set in the counts Y1 to Y5 of each interrupt signal.

  In step S3, the CPU sets the frequency division ratio of the frequency division / interrupt signal generation circuit 89 so that the output frequency of the interrupt signal becomes a value corresponding to the maximum value Xm of the fast-forward speed. With this setting, the output frequency of the next interrupt signal is changed to a frequency corresponding to the maximum value Xm of the fast-forward speed.

  In step S4, "0" is set to variables Y1t to Y5t indicating the remaining number of counts of interrupt signals until the first to fifth step motors 21, 22, 31, 41, 51 are next driven. . With this setting, all the step motors 21, 22, 31, 41, 51 can be started from the next interrupt signal.

  In step S5, among the fast-forward flags F1 to F5 indicating whether or not to perform fast-forward driving for each of the first to fifth step motors 21, 22, 31, 41, and 51, the number of moving steps for fast-forward driving is “0”. A flag value corresponding to a step motor that is not “1” is set to “1”.

  In step S6, “1” is set to the fast-forward correction flag in order to start the fast-forward control of each of the step motors 21, 22, 31, 41, 51 in the interrupt processing described later. And this fast-forward control process is complete | finished.

  6 and 7 show flowcharts of interrupt processing executed by the CPU. As shown in the above fast-forward setting process, in this flowchart, the interrupts that are the drive timings of the first to fifth step motors 21, 22, 31, 41, 51 by the variables (fixed values) Y1-Y5. The number of signal counts is indicated, and variables Y1t to Y5t indicate the remaining counts of interrupt signals until the first to fifth step motors 21, 22, 31, 41, 51 are next driven. . The flags F1 to F5 indicate whether or not the fast-forward drive is necessary / unnecessary for each of the first to fifth step motors 21, 22, 31, 41, 51 (“1” if necessary, “1” if unnecessary). “0”) is indicated.

  When an interrupt signal of frequency Xm is input from the frequency division / interrupt signal generation circuit 89 and this interrupt process is started by the CPU, first, the CPU determines whether or not the fast-forward correction flag is “1”. Is determined (step S10). As a result, if the fast-forward correction flag is “0”, it is determined that there is no fast-forward request, and the process proceeds to step S63. If the fast-forward correction flag is “1”, a fast-forward request is made. And the process proceeds to step S11.

  The processes in steps S11 to S17 are fast-forward control processes for the first step motor 21. When the process proceeds to step S11, the CPU first determines whether or not the fast-forward flag F1 corresponding to the first step motor 21 is “1” (step S11). As a result, if the fast-forward flag F1 is “0”, it means that the fast-forward drive of the first step motor 21 is not necessary or has already been completed, and the process proceeds to step S21 as it is.

  On the other hand, if the fast-forward flag F1 is “1”, it is determined whether or not the remaining count Y1t until the next drive timing is “0” (step S12). If the remaining count Y1t is “0”, the first step motor 21 is driven by one step (step S13). If the remaining count Y1t is not “0”, the remaining count The count Y1t is decremented by “1” and the process proceeds to step S21.

  When the first step motor 21 is driven by one step in step S13, the movement step number of the first step motor 21 is decremented by "1" and the movement step number becomes "0", that is, the first step motor. It is determined whether or not the fast-forward drive 21 has been completed (step S14). If it is determined that the fast-forward drive of the first step motor 21 is completed, the fast-forward flag F1 of the first step motor 21 is changed to “0” (step S15), and the process proceeds to step S21. On the other hand, if it is determined that the fast-forward drive of the first step motor 21 has not been completed yet, an interrupt signal that becomes the drive timing of the first step motor is set to the remaining count number Y1t for driving the first step motor 21 next. A value obtained by subtracting “1” from the number of counts Y1 is set, and the process proceeds to step S21.

  The subsequent steps S21 to S27 are fast-forwarding control processes for the second step motor 22, and the same processes as the steps S11 to S17 for the first step motor 21 are performed on the second step motor 22. . Similarly, steps S31 to S37, S41 to S47, S51 to S57, and fast-forwarding control processing for the third, fourth, and fifth step motors 31, 41, and 51 are performed.

  That is, of the first to fifth step motors 21, 22, 31, 41, 51 based on the interrupt signal supplied from the frequency division / interrupt signal generation circuit 89 by the processes of steps S 11 to S 57 described above. The step motor corresponding to the fast-forward timing is driven by slightly shifting the timing step by step.

  If the fast-forward control processing of the first to fifth step motors 21, 22, 31, 41, 51 with respect to one interrupt signal input is performed by the processing of steps S11 to S57 described above, It is determined whether or not all the fast-forwarding flags F1 to F5 of the fifth step motor have become “0” (step S61). If all the fast-forwarding flags F1 to F5 are “0”, it can be determined that the fast-forwarding driving of all the stepping motors 21, 22, 31, 41, 51 is completed, so the CPU sets the fast-forwarding correction flag. It is changed to “0” (step S62). Then, another process based on the interrupt signal is performed (step S63), and one interrupt process is terminated. On the other hand, if it is determined in the determination process in step S61 that any of the fast-forward flags F1 to F5 is not "0", another process based on the interrupt signal is performed as it is in step S63, and one interrupt process is performed. Exit.

  Such an interrupt process is repeatedly executed each time an interrupt signal having the same frequency as the fastest fast-forward speed Xm is input, so that the stepping motors that need to be fast-forwarded are set to the fast-forward speeds set for each. It is driven at a cycle corresponding to. For example, a stepping motor with the same fast feed speed as the peripheral edge number Xm of the interrupt signal is driven each time the interrupt signal is input, and a stepping motor with a slower fast feed speed is set to the fast feed speed. It is driven each time an interrupt signal is output for a corresponding count. And for the step motors that have completed the driving of the number of movement steps specified in the middle, the driving is stopped when the value of the fast-forwarding flags F1 to F5 of each step motor motor becomes “0”, and all the driving is stopped. When the fast-forward drive of the step motor is completed, the fast-forward correction flag becomes “0”, so that the control of the fast-forward drive is skipped from the next interrupt process.

  FIG. 8 shows a time chart for explaining the control pattern of each step motor in the modified example of the fast-forward process, and FIG. 9 shows a flowchart of the interrupt process in this modified example.

  In the embodiment described above, after determining the frequency Xm of the interrupt signal by the fast-forward setting process, the frequency of the interrupt signal is changed until the fast-forwarding of all the stepping motors 21, 22, 31, 41, 51 is completed. However, the fast-forward drive of the step motor that has the same fast-forward speed as the frequency Xm of the interrupt signal has been completed, and then the fast-drive of the step motor that has been set to the slow-fast speed remains. In this case, the frequency Xm of the interrupt signal can be changed to a frequency corresponding to a slow fast feed speed. Next, a modified example in which control for changing the frequency Xm of the interrupt signal on the way is shown.

  In the time chart of FIG. 8, the input timing of the interrupt signal is shown by timings t29 to t36. In the fast-forwarding process of the modified example, after the fast-forwarding drive of the fast-forwarding step motors (first, third, and fourth stepping motors 21, 22, and 41 in the example of FIG. 8) is completed, the step with the slow-forwarding speed is still slow. When the fast-forward drive of the motor (the fifth step motor 51 in the example of FIG. 8) remains, the frequency of the interrupt signal corresponds to the fastest fast-forward speed among the step motors that need to be fast-forward driven. Change to In the example of FIG. 8, the frequency of the interrupt signal is changed from 64 Hz to 32 Hz from timing t33. Thereafter, the fast-forward drive control of the remaining step motors is similarly performed based on the interrupt signal whose frequency has been changed.

  Next, an interrupt process for changing the frequency of such an interrupt signal will be described. As shown in FIG. 9, in the interrupt process of the modification, the processes of steps S <b> 100 to S <b> 105 are added in order to perform the above-described interrupt frequency change control. In the flowchart of FIG. 9, the processes in steps S10 to S57 and steps S61 to S63 are the same as those in FIG. 6 and FIG.

  In the interrupt process of the modified example, if the process of the fast-forward control of the first to fifth step motors 21, 22, 31, 41, 51 with respect to the input of one interrupt signal is performed by the process of steps S 11 to S 57, The CPU determines whether or not the fast-forward driving of the stepping motor having the fast-forwarding speed equal to the frequency Xm of the interrupt signal has been completed (step S100). If it is determined that the process has not ended, the process proceeds to step S63 as it is, and after performing other processes, one interrupt process is ended.

  On the other hand, if it is determined in step S100 that the fast-forward driving of the stepping motor having the same speed as the interrupt signal frequency Xm has been completed, first, in step S61, the fast-forwarding flags F1 to F5 are all set to “0”. If it is determined that all are “0”, the process proceeds to step S62.

  On the other hand, if it is determined in step S61 that any one of the fast-forwarding flags F1 to F5 of each step motor is not "0", it can be determined that the fast-forwarding drive of the stepping motor with a slow rapid-feed speed remains. The process proceeds to a process for changing the frequency of the interrupt signal from S101.

  First, the CPU sets the maximum value as the next maximum value Xm2 among the fast-forwarding speeds X1 to X5 of the step motor in which the number of fast-forwarding movement steps remains. Further, a value of the maximum speed ratio obtained by dividing the previous maximum value Xm by the next maximum value Xm2 is set in the variable RX for use in the subsequent calculation.

  Next, the CPU determines whether or not all the remaining counts Y1t to Y5t of the interrupt signal until the next driving timing of the step motor having the fast feed speeds X1 to X5 equal to the maximum value Xm2 is “0”. (Step S102). If all are not "0", the process proceeds to step S63, performs other processes, and ends the interrupt process as it is. In steps S102 to S105, the variable suffix “*” indicates that this variable is a variable of each of the first to fifth step motors 21, 22, 31, 41, and 51.

  In the discrimination process in step S102, immediately after the fast-forward drive of the fast-forward speed step motor is completed, the next drive timing of the step motor one step slower than the fast-feed speed comes instead of changing the frequency of the interrupt signal. This is to change the frequency of the interrupt signal at the drive timing. If the determination result in step S102 is “NO”, the interruption process is executed several times as it is, so that the next drive timing of the step motor whose fast-forward speed is one step lower comes, and the determination process in step S102 “ YES ”is determined.

  If “YES” is determined in the determination process of step S102, the CPU divides the frequency Xm2 of the interrupt signal to be set next by the fast-forwarding speeds X1 to X5 of the first to fifth step motors. The counts Y1 to Y5 of the interrupt signal that becomes the drive timing of the step motor are reset, and the next maximum value Xm2 is set to the frequency Xm of the interrupt signal (step S104). As a result, the generation cycle is changed from the next interrupt signal.

  Next, the CPU divides the remaining number of counts Y1t to Y5t until the next drive currently set by the value of the maximum speed ratio registered in the variable RX, respectively, to thereby generate a new interrupt signal frequency Xm. The remaining number of counts Y1t to Y5t until the next drive corresponding to is reset. With this setting, the drive cycle of the stepping motor that is continuously fast-forwarded is driven at a cycle according to the fast-forwarding speed of the stepping motor without opening or clogging before and after changing the interrupt signal frequency. become.

  As described above, according to the analog electronic timepiece 1 of this embodiment, the plurality of hands 2, 4, 12, 13, 51 by the plurality of step motors 21, 22, 31, 41, 51 having different fast-forwarding speeds. When the 15 or the date wheel 18 is fast-forwarded, a plurality of step motors are driven in parallel at different fast-forwarding speeds to perform a fast-forwarding operation. For example, a plurality of step motors are sequentially fast-forwarded one by one. In comparison, the total time required for the fast-forward operation can be shortened.

  Furthermore, with the interrupt signal corresponding to the fastest fast-forwarding speed as a reference, the step motor with the fast fast-forwarding speed set is stepped for each interrupt signal input, and the step motor with the slow fast-forwarding speed set is interrupted. Since step driving is performed every time the interrupt signal is counted a predetermined number of times, for example, it is compared with controlling the driving timing of each step motor by generating interrupt signals of a plurality of frequencies corresponding to a plurality of fast-forwarding speeds. Thus, the structure of timing control is simplified.

  The interrupt frequency is set or changed by switching the frequency division ratio of the frequency division / interrupt signal generation circuit 89, and this interrupt signal is input from the frequency division / interrupt signal generation circuit 89 to the CPU to drive timing. Therefore, the fast-forwarding operation can be easily controlled.

  Also, when the pointer reaches the target position by driving a step motor that is set to a fast forward speed in the middle of the fast-forward operation, it corresponds to the fastest fast-forward speed among the remaining step motors that are driving fast-forward. Since it is easy to change the interrupt signal to the interrupt frequency, it is not necessary to repeat the interrupt process at an unnecessarily large frequency.

  In addition, when the plurality of step motors 21, 22, 31, 41, 51 are driven at a fast feed, the drive for one step is performed by slightly shifting the timing within the fast feed cycle of each step of the plurality of step motors. Since pulses are output, excessive power is not required at a time, and a plurality of hands can be fast-forwarded stably.

  In addition, the pointer that is fast-forwarded by the driving of the step motor includes a rotating disk that is rotated by a train wheel mechanism such as the date wheel 18, and some of the symbols marked on the rotating disk are used. It can also be used when displaying or switching the date by exposing it on the dial 5.

  The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the above embodiment, in order to detect the cycle corresponding to the fast-forwarding speed of each step motor, an interrupt signal having a frequency corresponding to the fastest fast-forwarding speed is generated by the frequency dividing / interrupt signal generating circuit 89. The frequency division / interrupt signal generation circuit 89 generates a signal with a slightly faster frequency, and counts a predetermined number of signals of this frequency by software processing, thereby achieving the fastest fast-forward speed. A corresponding period may be detected.

  In the above embodiment, an example in which an interrupt signal for starting interrupt processing is applied as a timing signal having a predetermined period corresponding to the fast-forward speed has been described. However, the CPU confirms the input signal as a simple input signal. It is good also as a structure which detects the timing of a predetermined period.

  In addition, the details specifically shown in the embodiment, such as the type and number of hands and rotating disks, the number and specifications of step motors, can be changed as appropriate without departing from the spirit of the invention.

DESCRIPTION OF SYMBOLS 1 Analog electronic timepiece 2 Hour hand 3 Minute hand 4 Second hand 5 Dial 10 Casing 11,14 Small window 12,13 24 hour minute hand 15 1/10 second hand 17 Opening 18 Day wheel 21, 22, 31, 41, 51 Step motor 23, 24, 33, 43, 53 Train wheel mechanism 80 Control unit 83-87 Drive circuit 89 Frequency division / interrupt signal generation circuit 90 Switch unit B1-B4 Operation buttons

Claims (7)

The first guideline,
A first step motor driven at a predetermined cycle to fast-forward the first pointer;
The second guideline,
A second step motor driven at a cycle of N times the predetermined cycle (N is an integer of 2 or more) to fast-forward the second pointer;
Timing detection means for detecting the timing of the predetermined period;
The first step motor is driven every time the timing of the predetermined period is detected by the timing detection means, and the second step is performed every time the timing of the predetermined period is detected by the timing detection means. An analog electronic timepiece comprising fast-forward drive control means for driving a motor. Timing signal generating means for generating a timing signal of the predetermined period;
2. The analog electronic timepiece according to claim 1, wherein the timing detection means detects the timing of the predetermined period based on a timing signal of the timing signal generation means. The fast-forward drive control means includes
When the first pointer and the second pointer are both fast-forwarded, the first step motor is driven each time the timing of the predetermined period is detected by the timing detection unit, and the timing detection unit Driving the second step motor every time the timing of the predetermined period is detected N times,
When continuing the fast feed of the second pointer after the first pointer reaches a predetermined position, the driving of the first step motor is stopped and the timing of the predetermined cycle is set to N by the timing detection means. 2. The analog electronic timepiece according to claim 1, wherein the second step motor is driven each time the detection is performed. The timing signal generating means includes
The generation period of the timing signal can be switched between the predetermined period and a period N times the predetermined period,
The timing detection means includes
By switching the generation period of the timing signal of the timing signal generating means, it is possible to detect the timing of a period N times the predetermined period,
The fast-forward drive control means includes
When both the first pointer and the second pointer are fast-forwarded, the timing signal generating unit generates the timing signal of the predetermined period, and the timing detecting unit detects the timing of the predetermined period. Driving the first step motor, and driving the second step motor each time the timing of the predetermined period is detected N times by the timing detection means,
When continuing the fast feed of the second pointer after the first pointer reaches a predetermined position, the generation period of the timing signal of the timing signal generating means is switched to a period N times the predetermined period, 3. The analog electronic timepiece according to claim 2, wherein the second step motor is driven each time the timing detection unit detects a timing having a period N times the predetermined period. The fast-forward drive control means includes
When both the first step motor and the second step motor are driven, the first and second steps are output to the first step motor and the second step motor by shifting the drive time, respectively. 2. The analog electronic timepiece according to claim 1, wherein a motor is driven. A plurality of pointers including at least the first pointer and the second pointer;
A plurality of step motors including at least the first step motor and the second step motor, wherein the plurality of hands are driven, and each fast-forward driving cycle is set to a natural number multiple of the predetermined cycle. And
The fast-forward drive control means includes
When the plurality of hands are fast-forwarded together, the timing detection unit detects the timing of the predetermined cycle every time a multiple of the driving cycle for fast-forwarding of each step motor based on the predetermined cycle is detected. 2. An analog electronic timepiece according to claim 1, wherein said step motor is driven among said step motors.   2. The analog electronic timepiece according to claim 1, further comprising a rotating disk which is provided with a symbol on a front face and rotates with at least a part of the dial being exposed instead of the second pointer.

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