JPH086528A - Flat panel display device - Google Patents

Abstract

PURPOSE:To improve a display function by enabling write-in or read-out for the other picture memory while read-out operation for display operation is performed from one side out of first and second picture memories. CONSTITUTION:This device is provided with first and second storage means 2, 3 having storage capacity corresponding to one screen of a LCD(Liquid Crystal Display) panel. And a first changeover switch 4 and a second changeover switch 5 are complimentarily controlled to switch. For example, when the first changeover switch 4 inputs display data to the first storage means 2, the second changeover switch 5 reads out display data stored in the second storage means 3 to a FRC(Frame Rate Control) circuit 6. On the contrary, when the first changeover switch 4 inputs display data to the second storage means 3, the second changeover switch 5 reads out new display data stored in the first storage means 2 to the FRC circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, for example, an FRC (F
The present invention relates to a technology that is effectively used for displaying halftones by using the rame rate control.

[0002]

2. Description of the Related Art FRC (Frame Rate Control) is one of the halftone display techniques using liquid crystals. This FRC
The technique is to perform halftone display by controlling display data between frames to change the effective value of the liquid crystal drive voltage. Regarding such an FRC, for example, there are "Flat Panel Display '91", pages 173 to 180, published by 1991, Nikkei Electronics, Nikkei Microdevices.

FIG. 5 is a schematic block diagram of an embodiment of a conventional liquid crystal display device. The CPU (microprocessor) 9 accesses the display controller 10 via the data bus 12 and writes or reads image data to or from the image memory 11 via the controller 10. The controller 10 reads the image memory 11 by a timing signal and supplies display data and a timing signal necessary for a display operation to a driver 7 that drives a liquid crystal display panel (LCD panel) 8. In the controller 10, the image data read from the image memory 11 is processed, and halftone display is performed by the frame rate control in the read cycle.

[0004]

In the liquid crystal display device as described above, as shown in the operation timing chart of FIG. 6, the time between the display operations for one frame to the liquid crystal driver is utilized to allow the CPU to operate. Is accessed. That is, the input of new image data and the reading of the displayed image data are performed using the gap between the display operations for each frame. Therefore, when driving a high-speed response liquid crystal, it is necessary to increase the frame frequency and shorten the drive cycle in order to prevent the contrast from being lowered due to the frame response. In particular, when performing halftone display by FRC, since the effective value of the liquid crystal drive voltage is changed by using a plurality of frames, it is necessary to increase the frame frequency by using liquid crystal for the above high-speed response. However, if the frame frequency is increased in this way, the period during which the CPU can access each data transfer for one frame is inevitably shortened, and the rewriting of the necessary image memory is performed over a plurality of frames, which deteriorates the display image quality. I will invite you.

An object of the present invention is to provide a flat panel display device having an improved display function. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the first and second display data for storing one screen of display data displayed on the flat panel are stored.
Image memory is provided, and while one of the first and second image memories performs the read operation for the display operation, the other image memory can be written or read.

[0007]

According to the above means, the rewriting of the display data and the reading of the display data for the display operation are performed in parallel in time, so that the response of the flat panel using the frequency of the frame frequency can be adjusted. While setting arbitrarily,
A sufficient data transfer time for one frame can be secured.

[0008]

FIG. 3 is a schematic block diagram of an embodiment of the liquid crystal display device according to the present invention. In the figure, 1 is display data, which is input from a CPU or the like (not shown). Alternatively, the display data 1 is also a signal read by the CPU or the like as needed.

In this embodiment, an LCD (liquid crystal) panel 8 is used.
Two first and second with storage capacity corresponding to one screen
The storage means 2 and the storage means 3 are provided. The display data 1 is stored in the storage means 2 through the first changeover switch 4.
And is selectively supplied to the storage means 3. The storage means 2 and the storage means 3 are read out via the second changeover switch 5 and transmitted to the driver 7 which drives the signal line (segment) of the LCD panel 8.

The driver 7 serially takes in one line of image data and outputs it in parallel to perform one line of display operation. During this display period, the serial acquisition of the image data of the next line is performed. Although not shown in the figure, the LCD panel 8 is provided with scanning lines arranged so as to be orthogonal to the above-mentioned signal lines, and shifts sequentially shifting the selection signal input at the beginning of the frame. The selection signal is formed by the register and is sequentially selected by the scanning line driver that receives the output signal of the shift register.

The first changeover switch 4 and the second changeover switch 5 are complementarily switch-controlled. For example, when the first changeover switch 4 is inputting the display data to the first storage means 2, the second changeover switch 5 outputs the display data stored in the second storage means 3 to the driver 7. Read out. On the contrary, when the first changeover switch 4 is inputting the display data to the second storage means 3, the second changeover switch 5 displays the new display data stored in the first storage means 2. It is being read by the driver 7.

FIG. 4 shows a timing chart for explaining the operation. The display data A for one frame is stored in the storage means 2 by the first changeover switch 4. In the next frame, the display data B is stored in the storage means 3. During this period, the storage means 2
The display data A stored in the memory is stored in
It is repeatedly read and displayed. This makes LC
Even if the D panel 8 has a high-speed response, since the frame frequency can be increased, a high-quality display operation can be realized without flickering on the screen. The display data input by the CPU or the like can be input in parallel with one frame of display data without being affected by the frame frequency as described above.

FIG. 1 is a schematic block diagram of another embodiment of the liquid crystal display device according to the present invention. In this embodiment, a high quality display screen by FRC is obtained.

Also in this embodiment, similarly to the embodiment of FIG. 3, two first and second storage means 2 and storage means 3 having a storage capacity corresponding to one screen of the LCD panel 8 are provided. . The display data 1 is selectively supplied to the storage means 2 and the storage means 3 through the first changeover switch 4. In this embodiment, the storage means 2 and the storage means 3 are
Is transmitted to the FRC (frame rate control) circuit 6 instead of being directly supplied to the divider 7 through the second changeover switch 5 as described above, where F
RC processing is performed and the result is transmitted to the driver 7.

The driver 7 serially takes in one line of image data that has passed through the FRC circuit 6 in the same manner as above.
It is output in parallel and the display operation for one line is performed. During this display period, the serial acquisition of the image data of the next line is performed. Although omitted in the figure, L
The CD panel 8 is provided with scanning lines arranged so as to be orthogonal to the signal lines, and a selection signal is formed by a shift register that sequentially shifts the selection signal input at the beginning of the frame. It is sequentially selected by the scanning line driver which receives the output signal of the register.

The first changeover switch 4 and the second changeover switch 5 are complementarily switch-controlled. For example, when the first changeover switch 4 is inputting the display data to the first storage means 2, the second changeover switch 5 changes the display data stored in the second storage means 3 to the FRC circuit. 6 is read. On the contrary, when the first changeover switch 4 is inputting the display data to the second storage means 3, the second changeover switch 5
Indicates the new display data stored in the first storage means 2 as F
It is read to the RC circuit 6.

The above-mentioned first and second changeover switches 4 and 5
The switching timing of is performed at regular time intervals. For example, in the timing diagram (A) of FIG.
The gradation obtained by giving only 0 to the driver 7 is “gradation 1”.
Then, the gradation obtained by applying only 1 to the driver 7 is defined as “gradation 3”, the data 1 and 0 are alternately applied to the driver, and the intermediate gradation between the above “gradation 1” and “gradation 3” is obtained. When "gray level 2" is set, an example of displaying "gray level 2" which is the intermediate gray level is shown.

When the liquid crystal drive for four frames is performed at a frequency four times that of the input time of the display data for one screen as a reference, the first changeover switch 4 causes the storage means 2 to store "gradation 2". Display data indicating is input. Then, at the next timing, the second changeover switch 5 sets the display data of “gradation 2” stored in the storage means 2 to F
It is input to the RC circuit 6, where "grayscale 1" corresponding to 0 is displayed in the first frame, "grayscale 3" is displayed corresponding to 1 in the second frame, and is displayed in the third frame. Then, "gradation 1" corresponding to 0 is displayed again, and "gradation 3" corresponding to 1 is displayed again in the fourth frame. With such an effective value of the liquid crystal driving voltage over four frames, a display operation of "gray level 2" corresponding to the middle of the "gray level 1" and "gray level 3" is performed.

Since display data can be input to the storage means 3 by the first changeover switch 4 during the display period, the display data for one screen is rewritten in parallel with the display operation. be able to. Conversely speaking, the changeover switches 4 and 5 may be switched on the basis of a plurality of frames necessary for the FRC operation and the high-speed response of the liquid crystal. Generally, since the display data is input by the CPU or the like in a short time, the changeover switch 4 is set in accordance with the frame frequency of the liquid crystal as described above.
There is no problem even if the control of 5 and 5 is performed. Particularly, in this embodiment, since display data always exists in at least one of the storage means, it takes a relatively long time to change all display data as in the case of clearing all display data on the display screen. In this case, the changeover switches 4 and 5 are extended to double the reference time only at that time so that the display operation is performed by the display data of the other while the clear operation of one is performed. Because you can.

FIG. 2B shows an FRC according to the embodiment of FIG.
The operation is shown. Even in the case where two storage means are provided, when FRC-processed display data is input to the storage means, 0 is written in the storage means 2 and it is set to 4
While displaying for one frame, 1 is written in the storage means 3 and it is similarly displayed for four frames. For this reason, the frame frequency of the LCD itself can be increased as shown in (A), but when viewed from the FRC, a half-tone display is performed over a long time period of 8 frames, which causes a chip. On the other hand, in the case of (A), since half-tone display can be performed with two frames, the substantial frame frequency can be increased four times as high as that of (B).

The effects obtained from the above embodiment are as follows. That is, (1) first and second image memories for respectively storing display data for one screen displayed on the liquid crystal panel are provided, and one of the first and second image memories reads out for display operation. By enabling writing or reading to the other image memory while performing the operation, rewriting of the image data and reading of the image data for the display operation are performed in parallel in time, so that the frame It is possible to obtain an effect that the data transfer time for one frame can be sufficiently secured while arbitrarily setting the frequency according to the response of the liquid crystal panel using the frequency.

(2) The image data read from one of the image memories for a display operation is read a plurality of times while writing the image data for one screen to the other image memory and repeatedly displayed. As a result, it is possible to obtain an effect that it is possible to prevent the deterioration of the contrast due to the frame response even when using the liquid crystal having a high-speed response.

(3) Image data read from one of the image memories for display operation is subjected to FRC processing and transmitted to the driver of the flat panel, so that the substantial frame frequency is also obtained in FRC. It is possible to obtain the effect of increasing the value.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the liquid crystal display panel may be of a simple matrix type,
Alternatively, it may be an active matrix type using a TFT (thin film transistor). In addition to liquid crystal, the display panel may be any flat panel such as a plasma display capable of displaying at least at a lighted / unlighted state. As the storage means, a static RAM (random access memory) or a dynamic RAM can be used. This storage means may be configured in one semiconductor integrated circuit device together with the changeover switch, the FRC circuit and the control circuit. The present invention can be widely used in flat panel display devices.

[0025]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, 1 displayed on the liquid crystal panel
First and second image memories for respectively storing display data for the screen are provided, and while the read operation for the display operation is performed from one of the first and second image memories, the other image memory is By enabling writing or reading by writing, the rewriting of the image data and the reading of the image data for the display operation are performed in parallel in time,
It is possible to secure a sufficient data transfer time for one frame while arbitrarily setting the frame frequency according to the response of the liquid crystal panel using the frame frequency.

The image data read out from one of the image memories for the display operation is read out a plurality of times during the writing of one screen of image data into the other image memory, and is repeatedly displayed. Even if a high-speed response liquid crystal is used, it is possible to prevent deterioration of contrast due to frame response.

Image data read out from one of the image memories for display operation is subjected to FRC processing and transmitted to the driver of the flat panel, whereby the substantial frame frequency can be increased even in FRC. .

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the liquid crystal display device according to the present invention.

FIG. 3 is a schematic block diagram showing an embodiment of a liquid crystal display device according to the present invention.

4 is a timing diagram for explaining the operation of the liquid crystal display device of FIG.

FIG. 5 is a schematic block diagram showing an example of a conventional liquid crystal display device.

FIG. 6 is a timing chart for explaining the operation of the conventional liquid crystal display device.

[Explanation of symbols]

1 ... Display data, 2, 3 ... Storage means, 4 ... First changeover switch, 5 ... Second changeover switch, 6 ... FRC
Circuit, 7 ... Driver, 8 ... LCD panel, 9 ... CPU,
10 ... Display controller, 11 ... Image memory, 12 ... Data bus.

Claims (3)

[Claims] 1. A first and second image memories for respectively storing display data for one screen displayed on a flat panel, and a read operation for a display operation from one of the first and second image memories. A flat panel display device, wherein writing or reading can be performed on the other image memory while performing. 2. The image data read from one of the image memories for a display operation is repeatedly read and displayed a plurality of times while writing one screen of image data into the other image memory. The flat panel display device according to claim 1, wherein the flat panel display device is a display device. 3. The image data read out for display operation from the one image memory is FRC processed and transmitted to a flat panel driver. Flat panel display device.