JPH0865061A - Idling current control circuit - Google Patents

Abstract

PURPOSE: To maintain stable bias against temperature change without generating switching distortion in an amplifier circuit output stage. CONSTITUTION: Operating signals are detected from the emitter resistor of the NPN output TR 3 of an SEPP type power amplifier, a minimum value is held, the minimum value is compared with a reference voltage 29 set beforehand, a variable constant voltage source 7 is controlled so as to equalize the voltage and the bias is supplied through a diode 11 to the base of an NPNTR 2. A PNP output TR 5 is turned to similar circuit constitution as well and the idling currents of the respective output TRs are controlled. Also, the output difference of the holding circuit 27 of the NPN output TR 3 and the holding circuit 28 of the PNP output TR 5 is detected, the variable constant voltage source 6 is controlled so as to be equal to the reference voltage 30 set beforehand in a control amplifier 25 and the bias is applied between the bases of the NPNTR 2 and a PNPTR 4 through the diodes 13 and 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor output amplifier circuit which performs a class AB push-pull operation, and in particular, does not cause switching distortion and is idling for stable operation without being affected by ambient temperature or heat generation and variations of the transistor itself. The present invention relates to a current control circuit.

[0002]

2. Description of the Related Art In a push-pull type amplifier circuit that drives a low impedance load (speaker) represented by an audio power amplifier, compensation of a bias current fluctuation due to self-heating of an output stage output transistor and a change in ambient temperature. Therefore, a bias circuit as shown in the circuit diagram of FIG. 4 is generally used. The compensation uses the thermal feedback by thermally coupling the output stage output transistor 3 and the output transistor 5 and the transistor 32 for generating a bias on the heat sink.

However, such an amplifier circuit has a long time constant of thermal feedback, cannot follow a signal which changes every moment like a musical tone signal, and has a large fluctuation in bias current. Therefore, many amplifier circuits have been devised, which detect a bias current by detecting a voltage drop of an emitter resistance, and perform electric feedback based on this to control a bias.

For example, a circuit configuration as shown in the block diagram of FIG. 5 is disclosed in Japanese Utility Model Publication No. 4-18249. In the figure, 201 is a bias voltage generator, 2
Reference numeral 02 is a comparator, 203 is a voltage detector, and 204 is a minimum value holding device. The operation will be described. The voltage detector 2
03 detects a voltage drop due to a current flowing through the emitter resistors R1 and R2, and outputs the detection signal. The minimum value holding unit 204 holds the minimum value of the signal and sequentially outputs the minimum voltage value to the comparator 202.

The comparator 202 is a minimum value holding device 204.
Is compared with the reference voltage value VS, and the difference signal between them is compared to the control signal input terminal 2013 of the bias voltage generator 201.
Output to. The bias voltage generator 201 generates a desired bias voltage VBO between the output terminals 2011 and 2012 to control the idling current so that the difference signal becomes zero. Since the negative feedback circuit is configured as described above, a stable idling current value can be determined by adjusting the reference voltage VS, for example.

A circuit configuration as shown in FIG. 6 is disclosed in Japanese Patent Publication No. 4-27725. The operation will be described. Output transistor 3 and output transistor 5
Bias current flows through resistors 108 and 109, and a voltage drop occurs between both ends A and B of these resistors. Therefore, a voltage according to the magnitude of the bias current is applied to the detection circuit 101, A detection signal corresponding to the magnitude of the bias current is obtained at the output. This detection signal is applied to one of the comparators 102 and compared with the reference signal level applied to the other terminal E.

The comparator 102 outputs a high (H) level signal when the detection signal is larger than the reference signal level of the terminal E,
When the detection signal is small, a low (L) level signal is generated, and this comparison signal is applied to the integration / drive circuit 110.
The integrating / driving circuit 110 uses a variable impedance source (FET 106, 1) according to an integrated signal obtained by integrating the comparison signal.
07) is changed. The voltage drop between points C and D is changed by this change in impedance, and the bias currents of the output transistors 3 and 5 are controlled.

That is, when the bias currents of the output transistor 3 and the output transistor 5 increase due to temperature rise or the like, the detection signal of the detection circuit 101 increases, and when the detection signal exceeds a predetermined reference signal level of the terminal E, the comparator 102. Outputs an H level signal, and this H level signal is applied to the integration / drive circuit 110 to reduce the impedance of the drive circuit (FET), and the voltage drop between points C and D is reduced,
Reduce the bias. As a result, the bias current can maintain excellent stability, and the time required for stabilizing the bias current is extremely short.

[0009]

However, in the circuit configuration shown in FIG. 5, from the emitter of the NPN output transistor Q1 and the emitter of the PNP output transistor Q2,
Since the bias current is detected by the total voltage drop of the resistors R1 and R2, the operating state of the transistor in each of Q1 and Q2 cannot be detected. Further, when the output of the amplifier circuit becomes large and enters the class B operation range, the PNP output transistor Q2 is cut off near the positive peak of the signal and the NPN output transistor Q1 is cut off near the negative peak, causing switching distortion. The same can be said for the conventional circuit shown in FIG.

As a non-switching circuit, there is a circuit shown in a broken line in the circuit diagram of FIG. 7, but when the VBE decreases due to the temperature rise of the output transistor or the diode (16 to 19).
If the quasi-direction voltage VF of ## EQU1 ## varies in a high direction, the base bias of the output transistors 3 and 5 becomes large, and an excessive bias current may flow. Therefore, in FIG. 7, the transistor 32 and the resistor R
The biases (voltages) applied to the bases of the transistors 2 and 4 (points C and D respectively) by a and Rb are slightly smaller than the biases applied to points C and D by the non-switching circuit in the broken line. It can be suppressed. Therefore, the current flowing through the output transistor 3 and the output transistor 5 at the positive and negative peaks of the large-amplitude output becomes small, and in some cases the current is cut off. The present invention has been made in view of the above problems, and provides an idling current control circuit that does not cause switching distortion, is not affected by variations in elements, and has good follow-up with respect to temperature changes. is there.

[0011]

Therefore, in the idling current control circuit according to claim 1, in the control circuit for controlling the idling current of the SEPP type power amplifier each having an emitter resistance in the final output stage, the NPN output transistor 3 A first detector 21 that detects an operation signal from the emitter resistor REN, a first hold circuit 27 that holds the minimum value of the output waveform of the first detector 21, and a minimum value of the first hold circuit 27. A first bias voltage is supplied to the base 2 of the NPN transistor via the diode 11 so that the preset first reference voltage 29 becomes equal to the first reference voltage 29.
First control amplifier 24 for controlling the variable constant voltage source 7 of
A second detector 22 that detects an operation signal from the emitter resistance REP of the PNP output transistor 5, a second hold circuit 28 that holds the minimum value of the output waveform of the second detector 22, and a second A second variable constant voltage source 8 for controlling the second variable constant voltage source 8 which supplies a bias to the base of the PNP transistor 4 via the diode 12 so that the minimum value of the hold circuit 28 and the preset second reference voltage 31 become equal. Of the control amplifier 26 and the idling current flowing through the NPN output transistor 3 is determined by the first reference voltage 29, and the idling current flowing through the PNP output transistor 5 is determined by the second reference voltage.

In the idling current control circuit according to the second aspect of the present invention, the differential amplifier 23 having the outputs of the first hold circuit 27 and the second hold circuit 28 as inputs,
The NPN transistor 2 and the PNP are arranged so that the output of the differential amplifier 23 becomes equal to the preset third reference voltage 30.
Between the base of transistor 4 and diode 13 respectively
And a third control amplifier 2 for controlling a third variable constant voltage source 6 inserted to supply a bias current via
5, and the bias current is determined by the third reference voltage 30.

[0013]

Therefore, in the present invention, the first and second detectors detect the operating states of the NPN and PNP output transistors, respectively, and the first and second variable constant voltage sources flow to the emitters of the NPN and PNP output transistors. Since each operates so that the current does not fall below the idling current value, the power transistor does not reach the cutoff even at the time of high output and switching distortion does not occur. Further, since the bias is supplied between the NPN-PNP transistor bases by the third variable constant voltage source so that a predetermined idling current flows, the bias rapidly follows the temperature change and stabilizes the operation state. Can be made.

[0014]

1 is a block diagram of an output stage of an amplifier circuit according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of its operation. In these figures, when a signal vo (between point b and GND in the figure) as shown in FIG. 2 (1) is output, no current flows through the speaker 33 when there is no signal, so the first detector As shown in FIG. 2 (2), the signals input to the second detector 21 and the second detector 22 are caused by the emitter resistance REN (between a and b in the figure) and REP (between c and b in the figure) by the idling current, respectively. It corresponds to the voltage drop. Further, even when a signal is present, no current flows through the speaker 33 at the moment when the output vo becomes zero, so a signal corresponding to the same voltage drop is input.

The first detector 21 and the second detector 22
Is a first hold circuit 27 that multiplies the input signal by a gain G,
And to the second hold circuit 28. The first hold circuit 27 and the second hold circuit 28 hold the minimum value in the input signal and output a DC signal. The structure of this circuit can be realized by an operational amplifier and a transistor as shown in FIG. The operation is performed as R1 >> R2, and when the input Vin becomes lower than the output Vout, the electric charge stored in the capacitor C is rapidly discharged through R2.

During the period when Vin is higher than Vout, the transistor Tr is cut off, and the capacitor C is slowly charged through R1. FIG. 3B shows the input / output waveform of the hold circuit. The output of the first hold circuit 27 is the first
Is input to the control amplifier 24. The first control amplifier 24 controls the voltage of the variable constant voltage source 7 so that the hold value becomes equal to the first reference voltage 29, and a bias is supplied to the base of the transistor 2 via the diode 11.

Similarly, the output of the second hold circuit 28 is
It is input to the second control amplifier 26. The second control amplifier 26 controls the voltage of the variable constant voltage source 8 so that the hold value becomes equal to the second reference voltage 31, and a bias is supplied to the base of the transistor 4 via the diode 12. On the other hand, the outputs of the first hold circuit 27 and the second hold circuit 28 are input to the differential amplifier 23.
The differential amplifier 23 functions as a differential buffer and outputs the voltage difference between the two input signals to the third control amplifier 25.

The third control amplifier 25 is the differential amplifier 2
The voltage of the variable constant voltage source 6 is controlled so that the output of the transistor 3 becomes equal to the third reference voltage 30, and a bias is supplied between the bases of the transistor 2 and the transistor 4 via the diodes 13 and 14. Here, the ratio of the first reference voltage 29, the second reference voltage 31, and the third reference voltage 30 is 1:
Set the value at 2: 1. Therefore, the bias of the variable constant voltage source 6 is controlled so that a constant idling current always flows.

The variable constant voltage source 7 biases the base of the transistor 2 so that the output transistor 3 does not cut off even when the output vo of the amplifier circuit is negative and the current flowing through the output transistor 3 does not fall below the idling current. Similarly, the variable constant-voltage source 8 biases the base of the transistor 4 so that the output transistor 5 does not cut off even when the output vo of the amplifier circuit is positive and the current flowing through the output transistor 5 does not fall below the idling current. The signal lines of h, f, and g in FIG. 1 in this state are
It becomes like Fig. 2 (3).

The relationship between the idling current Iid and the reference voltage Vref is given by the following equation. Iid × (REN + REP) × G = Vref Iid = Vref / ((REN + REP) × G) [A]

Although the power source of the control circuit unit 1 of the present invention in FIG. 1 is omitted, the configuration is such that the inputs of the first detector 21 and the second detector 22 (a and b in FIG. 1) are omitted. , C) is G
Since the output voltage of the amplifier circuit is applied to the ND in the common mode, a floating power supply configuration in which the output line operates as the floating GND is desirable.

[0022]

As described above, according to the present invention, a bias that does not cut off the output transistor can be supplied to the base of the transistor by detecting and controlling the current flowing through the emitter resistance of each output transistor, which causes switching distortion. Can be prevented. Further, even if VBE changes due to a change in ambient temperature or abrupt heat generation of the transistor itself, a constant idling current value is maintained and stable operation can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an amplifier circuit output stage of the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of the amplifier circuit of the present invention.

3A and 3B show an embodiment of a minimum value detection circuit used in the amplifier circuit of the present invention, FIG. 3A is a circuit diagram, and FIG. 3B is its output waveform.

FIG. 4 is a circuit diagram showing an output stage of a conventional amplifier circuit.

FIG. 5 is a block diagram showing an example of bias control by electrical feedback in a conventional example.

FIG. 6 is a circuit diagram showing another example of bias control by electric feedback in a conventional example.

FIG. 7 is a circuit diagram showing an embodiment of an output stage of an amplifier circuit provided with a non-switching circuit in a conventional example.

[Explanation of symbols]

 1 Control Circuit Unit 2, 4, 10, 32 Transistor 3, 5 Output Transistor 6, 7, 8 Variable Constant Voltage Source 9 Constant Current Source 11-20 Diode 21 First Detector 22 Second Detector 23 Differential Amplifier 24 1st control amplifier 25 3rd control amplifier 26 2nd control amplifier 27 1st hold circuit 28 2nd hold circuit 29 1st reference voltage 30 3rd reference voltage 31 2nd reference Voltage 33 Speaker 101 Detection circuit 102 Comparator 103, 104 Constant voltage source (power supply) 105 Reference voltage 106, 107 FETs 108, 109 Emitter resistance 110 Integration / driving circuit 111 Input 112 Output 113 Load 201 Bias voltage generator 202 Comparator 203 Voltage detector 204 Minimum value hold device R1 to R6 resistance Q1 to Q4 transistor

Claims (2)

[Claims] 1. A first detector 2 for detecting an operating signal from an emitter resistance REN of an NPN output transistor 3 in a control circuit for controlling an idling current of a SEPP type power amplifier each having an emitter resistance in a final output stage.
1, a first hold circuit 27 that holds the minimum value of the output waveform of the first detector 21, and a first hold circuit 2
A first control for controlling the first variable constant voltage source 7 that supplies a bias to the base of the NPN transistor 2 via the diode 11 so that the minimum value of 7 and the preset first reference voltage 29 become equal. Amplifier 24, a second detector 22 that detects an operation signal from the emitter resistance REP of the PNP output transistor 5, and a second hold circuit 28 that holds the minimum value of the output waveform of the second detector 22. , The second
PNP transistor 4 so that the minimum value of the hold circuit 28 and the preset second reference voltage 31 become equal to each other.
Second control amplifier 26 for controlling the second variable constant voltage source 8 which supplies a bias to the base of the transistor via the diode 12.
And an idling current flowing through the NPN output transistor 3 is determined by the first reference voltage 29, and an idling current flowing through the PNP output transistor 5 is determined by the second reference voltage. Control circuit. 2. A differential amplifier 23 which receives the outputs of the first hold circuit 27 and the second hold circuit 28, and a third preset output of the differential amplifier 23.
A third variable constant voltage source 6 inserted to supply a bias current between the bases of the NPN transistor 2 and the PNP transistor 4 via the diodes 13 and 14 so as to be equal to the reference voltage 30 of And a bias amplifier 25 for controlling the bias current.
2. The idling current control circuit according to claim 1, wherein the idling current control circuit is determined by the reference voltage 30.