JP3281798B2 - Power amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a power amplifier circuit in which an output DC bias is set to a level close to the ground level.

[0002]

2. Description of the Related Art Conventionally, the midpoint voltage of an amplifier is set to 1
Japanese Patent Laid-Open Publication No. 6-338 discloses a technique for achieving high efficiency of the amplifier and non-clip of the output signal of the amplifier by setting the value very close to the ground without setting the value to / 2.
No. 738 discloses a power amplification device. In such a power amplifying device, the number of switching power supplies could be significantly reduced.

In FIG. 2, for example, a sine wave input signal is applied to a negative input terminal of a first differential amplifier (1),
Output signals of opposite phases are generated from the positive and negative output terminals of the differential amplifier (1). The positive and negative output signals of the first differential amplifier (1) are first and second bias circuits (2) and (3).
After the bias is superimposed on the first and second SEPP (single-ended push-pull) amplifiers (4) and (5)
Is applied to The first and second SEPP amplifiers (4) and (5) form a BTL amplifier, and the load RL is changed to B by the output signals of the first and second SEPP amplifiers (4) and (5).
TL drive is performed.

Further, first and second SEPP amplifiers (4)
And (5) are non-linearly added by a non-linear addition circuit (6). The non-linear addition circuit (6) operates as an addition circuit when the output signal levels of the first and second SEPP amplifiers (4) and (5) are equal to or lower than a predetermined level, and a clamp circuit when the output signal level is equal to or higher than a predetermined level. It works as. An output signal of the non-linear addition circuit (6) is applied to a negative input terminal of the second differential amplifier (7), and an output signal corresponding to a difference from the reference voltage Vref of the positive input terminal is output from the first differential amplifier (1). Is applied to the common terminal of The common terminal is a terminal for determining the output DC voltage of the first and second SEPP amplifiers (4) and (5).
The first and second SEPs are controlled by controlling the output DC voltage according to the output signals of the PP amplifiers (4) and (5).
The output DC voltages of the P amplifiers (4) and (5) are set to voltages close to the ground level, and the output signals of the first and second SEPP amplifiers (4) and (5) become half-wave output signals.

Further, first and second SEPP amplifiers (4)
The output signals of (5) and (5) are added by an adding circuit (8).
According to the output signal of the addition circuit (8), the transistor (1
1) is turned on and off, and the switching power supply circuit (1)
2) to first and second SEPP amplifiers (4) and (5)
A power supply voltage Vx similar to that of the output signal is generated.

[0006]

The DC bias of the input signal is Vcc / 2 (for example, Vcc = 13.5).
V), but the DC bias is actually Vcc
/ 2 is converted to a lower value (for example, 3.5 V) and then applied to the first differential amplifier circuit (1). Then, in the first differential amplifier circuit (1), the DC bias is converted to a level (2 V) closer to a lower earth level. Thus, the generation of the shock noise can be prevented by gradually lowering the DC level. However, since the DC bias of the input signal is reduced,
When the power supply voltage Vcc is high and a large input is applied, a signal whose lower waveform is clipped as shown in FIG. 3A is applied to the first differential amplifier circuit (1). Therefore, as shown in FIG.
Only the output signal corresponding to the lower waveform of the input signal among the output signals of the second and fourth SEPP amplifiers (4) and (5) is clipped, and the first and second SEPP amplifiers (4) and (5) are clipped.
Are unbalanced. Since the output signal waveform corresponding to the upper waveform of the input signal becomes large up to the vicinity of the power supply voltage Vcc, if the power supply voltage Vcc is high, the imbalance of the output signal waveform becomes large as shown in FIG. There was a problem that happened.

[0007]

SUMMARY OF THE INVENTION The present invention provides first and second embodiments.
A first and a second for generating an output signal and BTL driving the load
An output amplifier, a non-linear addition circuit that non-linearly adds the output signals of the first and second output amplifiers, and an input signal that is amplified and controlled in accordance with the output signal of the non-linear addition circuit; A nonlinear amplifier that generates an input signal of the output amplifier; anda power amplifier circuit that amplifies a DC bias generation circuit that generates a low DC bias close to the ground level and a superimposed signal of the DC bias and the input signal. An input amplification circuit applied to the non-linear amplifier, and a control circuit for detecting that a power supply voltage has become equal to or higher than a predetermined level and changing the DC bias are provided.

When the power supply voltage is higher than a predetermined level, the DC bias generation circuit includes a first input terminal to which a DC current is supplied and a second input terminal to which an output signal is fed back via a resistor.
An input terminal is provided, and a DC bias is increased by flowing a DC current of the control circuit through a feedback path.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing an embodiment of the present invention, wherein (13) denotes an amplifier (14) and an amplifier (1).
DC bias generation comprising a resistor (15) connected to the feedback path of 4), a voltage source (17) connected to one input terminal, and a constant current source (18) connected to the other input terminal. Circuit, (19) amplifier (20) and coupling capacitor C
, An input amplifier circuit composed of input resistors R1 and R2, and a feedback resistor R3, (21) is a series-connected zener diodes (22) and (23), and diode-connected transistors (24) and (25). ) And a current mirror circuit (2) for inverting the emitter current of the transistor (25).
6). In FIG. 1, the same circuits as those in the conventional example in FIG. 2 are denoted by the same reference numerals as in FIG. 2, and the description will be omitted. In FIG. 1, the operation of the power amplifying device is the same as that of FIG.

Referring to FIG. 1, first, a description will be given of a bias generation operation when a first constant voltage Vreg1 obtained by converting the first power supply voltage Vcc1 to a constant voltage is applied to the cathode of the Zener diode (22). Zener diode (2
2) and (23) and the transistor (2
4) and (25) and the total forward voltage of the transistor (26a) forming the current mirror circuit (26) is the first voltage.
Since the voltage is set lower than the constant voltage Vreg1, the Zener diodes (22) and (23) and the transistors (24), (25) and (26a) are turned off.

In the DC bias generation circuit (13),
The output current of the constant current source (18) flows through the resistor (15).
Therefore, the DC output bias Vb1 of the amplifier (14) is
The voltage is obtained by adding the voltage of the voltage source (17) and the voltage due to the voltage drop of the resistor (15) of the constant current source (18). The bias voltage Vb1 is applied to input terminals of the amplifier (20) via input resistors R1 and R2, respectively. Further, the input signal is applied to one input terminal of the amplifier (20) after being DC cut by the coupling capacitor C. Therefore, an output signal is generated at the output terminal of the amplifier (20) by amplifying the superimposed signal of the input signal and the first DC bias voltage Vb1, and is applied to the first differential amplifier circuit (1).

Here, at the time of large input, the output signal of the amplifier (20) becomes a one-sided clip as shown in FIG. For that reason,
The output signals of the first and second SEPP amplifiers (4) and (5) are as shown in FIG. 3B, and the waveforms of the output signals are unbalanced. Next, the case where the second power supply voltage Vcc2 higher than the first power supply voltage Vcc1 is replaced with a higher power supply voltage and the second constant voltage Vreg2 obtained by converting the second power supply voltage Vcc2 to a constant voltage is applied to the cathode of the Zener diode (22). explain. The second constant voltage Vreg2 includes Zener diodes (22) and (23) and diodes (24) and (2).
Since they are higher than the sum of the forward voltages of 5) and (26a), the Zener diodes (22) and (23) and the diodes (24), (25) and (26a) are turned on.
The current flowing through the Zener diodes (22) and (23) and the transistors (24), (25) and (26a) is inverted by the current mirror circuit (26), and then the resistance (1
Flow to 5). Therefore, the addition current of the output currents of the constant current source (18) and the current mirror circuit (26) flows through the resistor (15). Therefore, the output voltage of the amplifier (14) becomes the second DC bias voltage Vb2 obtained by adding the voltage due to the voltage drop of the resistor (15) through which the addition current flows and the output voltage of the constant voltage source (17), and the first DC bias voltage Vb2 is obtained. Bias voltage Vb1
Higher voltage. Then, the input signal is superimposed on the second DC output bias voltage by the amplifier (20), and then applied to the first differential amplifier circuit (1).

Here, at the time of large input, an input amplifier circuit (19)
Since the DC bias voltage Vb2 is high, the dynamic range of the input amplifying circuit (19) increases, and no clipping occurs in the output signal of the input amplifying circuit (19) as shown in FIG. Therefore, the clip level of the output signal is determined by the dynamic range of the first and second SEPP amplifier circuits (4) and (5). Therefore, the output signals of the first and second SEPP amplifiers (4) and (5) are as shown in FIG. As is apparent from FIG. 3E, there is no imbalance in the output signal waveforms of the first and second SEPP amplifiers (4) and (5).

[0014]

As described above, according to the present invention, the output DC voltage is close to the ground level, and the load is changed to a BT by a half-wave signal.
In the power amplifying device driven by L, the level of the power supply voltage is detected, and when the level becomes high, the input bias voltage of the power amplifying device is increased. Can be improved. For this reason, it is possible to reduce the uncomfortable feeling at the time of large input of a high power supply voltage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a waveform chart for explaining the present invention.

[Explanation of symbols]

 13 DC bias generation circuit 14, 20 amplifier 18 constant current source 19 input amplification circuit 21 control circuit 26 current mirror circuit

Claims (2)

(57) [Claims] 1. A method for generating a first output signal and a second output signal.
First and second output amplifiers for TL driving, a non-linear addition circuit for non-linearly adding the output signals of the first and second output amplifiers, and an input signal which is amplified and output according to the output signal of the non-linear addition circuit bias is controlled, ah
Half-wave waveform superimposed on the first DC bias close to the
And a non-linear amplifier that generates an input signal of the first and second output amplifiers in a power amplifier circuit .
A DC bias generating circuit for generating a second DC bias between the DC bias and the DC bias; and superimposing the second DC bias on an input signal to reduce the DC bias from half the power supply voltage to the second DC bias. into a DC voltage, an input amplifier circuit to be applied to the non-linear amplifier, detects that said power supply voltage exceeds a predetermined level,
A power amplifier circuit, comprising: a control circuit that changes the second DC bias. 2. When the power supply voltage is higher than a predetermined level, the DC bias generation circuit has a first input terminal to which a DC current is supplied, and a second input terminal to which an output signal is fed back via a resistor. 2. The power amplifier circuit according to claim 1, wherein the DC bias of the control circuit is increased by flowing the DC current of the control circuit through a feedback path.