JPH09294032A - Power amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an unbalanced clip of a BTL amplifier output signal when a power supply with a high voltage is employed. SOLUTION: A power amplifier is configured such that an output DC bias is set to a level close to ground level and BTL drive is applied to a load with a half wave signal. In this case, when a higher voltage Vreg is received, Zener diodes 22, 23 and transistors(TRs) 25, 26a are conductive. Since a current flowing to the diode 25 being a TR of diode connection is inverted by a current mirror circuit 26, a current flowing to a resistor 15 is increased and a DC bias produced at an output terminal of an amplifier 14 is increased. Thus, even when an input signal is increased, a clipped level is increased and clip levels of output signals of SEPP amplifiers 4, 5 are close to each other. Then unbalanced output signals of the SEPP amplifiers 4, 5 are reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a power amplifier circuit in which an output DC bias is set to a level close to a ground level.

[0002]

2. Description of the Related Art Conventionally, the midpoint voltage of an amplifier is set to 1 of the power supply voltage.
Japanese Laid-Open Patent Publication No. 6-338 discloses a technique that achieves high efficiency of the amplifier and non-clipping of the output signal of the amplifier by setting a value very close to the ground without setting / 2.
There is a power amplification device disclosed in No. 738. In such a power amplification device, the number of switching power supplies could be significantly reduced.

In FIG. 2, for example, a sinusoidal input signal is applied to the negative input terminal of the first differential amplifier (1),
Output signals of opposite phases are generated from the positive and negative output terminals of the differential amplifier (1). Positive and negative output signals of the first differential amplifier (1) are fed to the first and second bias circuits (2) and (3).
First and second SEPP (single ended push-pull) amplifiers (4) and (5) after the bias is superimposed at
Applied to. The first and second SEPP amplifiers (4) and (5) form a BTL amplifier, and the load RL is set to B by the output signals of the first and second SEPP amplifiers (4) and (5).
TL driven.

The first and second SEPP amplifiers (4)
And (5) are nonlinearly added by the nonlinear addition circuit (6). The non-linear adder circuit (6) operates as an adder circuit when the output signal levels of the first and second SEPP amplifiers (4) and (5) are below a predetermined level, and a clamp circuit when the output signal level is above a predetermined level. Is to work as. The output signal of the non-linear addition circuit (6) is applied to the negative input terminal of the second differential amplifier (7), and the output signal corresponding to the difference from the reference voltage Vref of the positive input terminal is the first differential amplifier (1). Applied to the common terminal of. The common terminal is a terminal for determining the output DC voltage of the first and second SEPP amplifiers (4) and (5).
The first and second SEPs are controlled by controlling the output DC voltage according to the output signals of the PP amplifiers (4) and (5).
The output DC voltage of the P amplifiers (4) and (5) is set to a voltage close to the ground level, and the output signals of the first and second SEPP amplifiers (4) and (5) become half-wave output signals.

The first and second SEPP amplifiers (4)
The output signals of (5) and (5) are added by the adder circuit (8).
Depending on the output signal of the adder circuit (8), the transistor (1
1) is turned on and off, and the switching power supply circuit (1
2) to the first and second SEPP amplifiers (4) and (5)
A power supply voltage Vx having a similar shape to that of the output signal is generated.

[0006]

By the way, the DC bias of the input signal is Vcc / 2 (for example, Vcc = 13.5).
Although it is set to V), the DC bias is actually set to Vcc.
It is applied to the first differential amplifier circuit (1) after being converted from / 2 to a lower value (for example, 3.5 V). Then, in the first differential amplifier circuit (1), the DC bias is converted to a level (2V) closer to a lower ground level. In this way, it is possible to prevent the generation of shock noise by gradually decreasing the DC level. However, since the DC bias of the input signal is reduced,
When the power supply voltage Vcc is high and a large input is applied, a signal having a lower waveform clipped as shown in FIG. 3A is applied to the first differential amplifier circuit (1). Therefore, as shown in FIG.
Of the output signals of the second and second SEPP amplifiers (4) and (5), only the output signal corresponding to the lower waveform of the input signal is clipped, and the first and second SEPP amplifiers (4) and (5) are clipped.
The output signal waveform of is unbalanced. Since the output signal waveform corresponding to the upper side waveform of the input signal increases up to the vicinity of the power supply voltage Vcc, when the power supply voltage Vcc is high, the imbalance of the output signal waveform becomes large as shown in FIG. There was a problem that happened.

[0007]

The present invention includes first and second aspects.
First and second BTL driving load by generating an output signal
An output amplifier, a non-linear addition circuit for non-linearly adding the output signals of the first and second output amplifiers, and an amplifier for amplifying an input signal, and being controlled according to the output signal of the non-linear addition circuit, the first and second A non-linear circuit including a non-linear amplifier that generates an input signal of an output amplifier is a power amplification circuit, and a direct current bias generation circuit that generates a low direct current bias close to a ground level and a superimposed signal of the direct current bias and the input signal are amplified. An input amplifier circuit for applying to the non-linear amplifier, and a control circuit for detecting that the power supply voltage has become equal to or higher than a predetermined level and changing the DC bias are provided.

When the power supply voltage is higher than a predetermined level, the DC bias generating circuit has a first input terminal to which a DC current is supplied and a second input terminal to which an output signal is fed back through a resistor.
An input terminal is provided, and a direct current bias of the control control circuit is increased by causing a direct current of the control circuit to flow in a feedback path.

[0009]

1 is a diagram showing an embodiment of the present invention, in which (13) is an amplifier (14) and an amplifier (1
DC bias generation consisting of a resistor (15) connected to the return path of 4), a voltage source (17) connected to one input end, and a constant current source (18) connected to the other input end Circuit (19) is amplifier (20) and coupling capacitor C
An input amplifier circuit composed of an input resistor R1 and R2 and a feedback resistor R3, and (21) is a Zener diode (22) and (23) connected in series, and a diode-connected transistor (24) and (25). ) And a current mirror circuit (2) that inverts the emitter current of the transistor (25).
6) is a control circuit consisting of In FIG. 1, the same circuits as those of the conventional example of FIG. 2 are designated by the same reference numerals as those of FIG. 2 and their explanations are omitted. Further, in FIG. 1, the operation of the power amplification device is the same as in FIG.

Referring to FIG. 1, first, a bias generating operation in the case where a first constant voltage Vreg1 which is a constant voltage of the first power supply voltage Vcc1 is applied to the cathode of the Zener diode (22) will be described. Zener diode (2
2) and the forward voltage of (23) and the transistor (2
4) and (25) and the forward voltage of the transistor (26a) forming the current mirror circuit (26) is the first voltage.
Since it is set lower than the constant voltage Vreg1, the Zener diodes (22) and (23) and the transistors (24), (25) and (26a) are turned off.

In the DC bias generating circuit (13),
The output current of the constant current source (18) flows through the resistor (15).
Therefore, the DC output bias Vb1 of the amplifier (14) is
The voltage is the sum of the voltage source (17) and the voltage due to the voltage drop of the resistor (15) of the constant current source (18). The bias voltage Vb1 is applied to the input terminal of the amplifier (20) via the input resistors R1 and R2, respectively. The input signal is DC-cut by the coupling capacitor C and then applied to one input terminal of the amplifier (20). Therefore, an output signal obtained by amplifying the superimposed signal of the input signal and the first DC bias voltage Vb1 is generated at the output end of the amplifier (20) and applied to the first differential amplifier circuit (1).

Here, at the time of a large input, the output signal of the amplifier (20) becomes a one-side clip as shown in FIG. For that reason,
The output signals of the first and second SEPP amplifiers (4) and (5) are as shown in FIG. 3B, and the waveforms of the output signals are unbalanced. Next, when the second power supply voltage Vcc2 higher than the first power supply voltage Vcc1 is changed to a higher power supply voltage Vcc2 and the second constant voltage Vreg2 obtained by converting the second power supply voltage Vcc2 into a constant voltage is applied to the cathode of the Zener diode (22), explain. The second constant voltage Vreg2 is applied to the zener diodes (22) and (23) and the diodes (24) and (2
5) and (26a) higher than the sum of the forward voltage, so the Zener diodes (22) and (23) and the diodes (24), (25) and (26a) are turned on.
The currents flowing through the Zener diodes (22) and (23) and the transistors (24), (25) and (26a) are inverted by the current mirror circuit (26) and then the resistance (1
Flow to 5). Therefore, the added current of the output currents of the constant current source (18) and the current mirror circuit (26) flows through the resistor (15). Therefore, the output voltage of the amplifier (14) becomes the second DC bias voltage Vb2 obtained by adding the voltage due to the voltage drop of the resistor (15) through which the addition current flows and the output voltage of the constant voltage source (17), and the first DC Bias voltage Vb1
Higher voltage. Then, the input signal is superimposed on the second DC output bias voltage by the amplifier (20) and then applied to the first differential amplifier circuit (1).

Here, at the time of large input, the input amplifier circuit (19)
Since the DC bias voltage Vb2 is high, the dynamic range of the input amplifier circuit (19) is high, and no clipping occurs in the output signal of the input amplifier circuit (19) as shown in FIG. Therefore, the clip level of the output signal is determined by the dynamic range of the first and second SEPP amplifier circuits (4) and (5). Therefore, the output signals of the first and second SEPP amplifiers (4) and (5) are as shown in FIG. As is clear from FIG. 3 (e), the imbalance of the output signal waveforms of the first and second SEPP amplifiers (4) and (5) disappears.

[0014]

As described above, according to the present invention, the output DC voltage is close to the ground level, and the load is BT by the half-wave signal.
In a power amplifier that drives L, the level of the power supply voltage is detected, and when the level becomes high, the input bias voltage of the power amplifier is increased, so that the output signal waveform of the power amplifier at the time of large input is unbalanced. Can be improved. Therefore, it is possible to reduce an unpleasant sensation in hearing when a high input of a high power supply voltage is input.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a waveform diagram for explaining the present invention.

[Explanation of symbols]

 13 DC bias generation circuit 14, 20 Amplifier 18 Constant current source 19 Input amplification circuit 21 Control circuit 26 Current mirror circuit

Claims (2)

[Claims] 1. A first and a second output signal are generated and a load is B
TL-driven first and second output amplifiers, a non-linear addition circuit that non-linearly adds the output signals of the first and second output amplifiers, an input signal is amplified, and control is performed according to the output signal of the non-linear addition circuit. In the power amplification circuit, a non-linear circuit including a non-linear amplifier that generates the input signals of the first and second output amplifiers is a DC bias generation circuit that generates a low DC bias close to a ground level; An input amplifier circuit for amplifying a superimposed signal with an input signal and applying the amplified signal to the non-linear amplifier; and a control circuit for detecting that the power supply voltage is above a predetermined level and changing the DC bias. Characteristic power amplification circuit. 2. The DC bias generating circuit comprises a first input terminal to which a DC current is supplied and a second input terminal to which an output signal is fed back through a resistor when the power supply voltage is higher than a predetermined level. 2. The power amplifier circuit according to claim 1, wherein a DC bias is increased by causing a DC current of the control control circuit to flow in a feedback path.