JPH0864683A - Semiconductor integrated circuit and its layout method - Google Patents

Abstract

PURPOSE: To improve flexibility in layout design by providing choices for take- out direction of output signal by enclosing three sides of the second block containing a control transistor with the first block containing an output transis tor, and then assigning a power supply wiring between the facing two sides of the second block and the first block. CONSTITUTION: An output transistor for driving an input of load or other logic circuit connected to an output terminal or pad, and a control transistor for driving the output transistor are provided. Relating to such a semiconductor integrated circuit, with the first block 13 containing the output transistor, three sides of the second block 12 containing the control transistor are enclosed, and further, power supply wirings 10 and 11 are assigned between the facing two sides and the first block 13. For example, the first block 13 consists of a pull-up area 13a, a pull-dawn area 13b and a connection area 13c connecting each side of these two areas together, so that the entire has a recessed shape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a layout method thereof, and more particularly to a technique which contributes to improving the efficiency of layout design.

[0002]

2. Description of the Related Art Generally, in the layout design of a semiconductor integrated circuit, it is required to make a signal path as short as possible and to make an appropriate wiring width. In the element logic circuit), since the number of elements (transistors) is large and the element sizes are different, these requirements cannot be easily satisfied.

FIG. 6 is a schematic layout of a conventional multi-element logic circuit. Reference numerals 1 and 2 denote a pair of parallel power supply wirings (for example, a V _CC power supply and a V _EE power supply), and a control block 3 and an output block 4 are laid out side by side between the pair of power supply wirings 1 and 2. . Each block 3, 4
Pull-up areas 3a and 4a and pull-down area 3 respectively
A plurality of transistors (not shown) are laid out in each region including b and 4b.

A transistor (not shown) inside the control block 3 (hereinafter referred to as "control transistor") is an input signal IN.
In response to the driving of the control transistor (hereinafter also referred to as "output transistor") in the output block 4, the output transistor being in response to the driving of the control transistor. It drives a load connected to a pad or an input of another logic circuit (hereinafter, “represented by load”).

The two signals OUTa and OUTb extracted from the right end side of the output block 4 are signals (output signals) for driving a load, and the upper output signal OUTa is for pull-up operation and the lower side. The output signal OUTb of the above is for the pull-down operation. Input signal signal IN
An imaginary line connecting the output signal OUTa and the output signal signal OUTb schematically represents a signal flow. In this example,
Some signals are fed back from the output block 4 to the control block 3.

[0006]

However, in such a conventional semiconductor integrated circuit, the control block 3 and the output block 4 are laid out side by side between the two parallel power supply lines 1 and 2. Therefore, there is an inconvenience that the output signal extraction direction is fixed in one direction. For example, in the case of FIG. 6, since it is fixed in the right direction of the output block 4, there is flexibility in layout design. There was room for improvement.

[0007]

[Purpose] Therefore, an object of the present invention is to increase the flexibility of layout design by giving some options to the output signal extraction direction.

[0008]

According to the first aspect of the present invention,
A semiconductor integrated circuit having an output transistor for driving a load connected to an output terminal or an output pad or an input of another logic circuit, and a control transistor for driving the output transistor, the first integrated circuit including the output transistor. It is characterized in that a block surrounds three sides of the second block including the control transistor, and a power supply wiring is arranged between two opposite sides of the second block and the first block.

According to a second aspect of the invention, in the first aspect of the invention, the first block includes an output transistor including an even number of MOS transistors arranged in parallel. According to a third aspect of the present invention, all the elements common to a plurality of different types of logic circuits and the elements unique to each of the logic circuits are all pre-fabricated, and the elements depending on the type of the logic circuit to be designed. It is characterized in that a unique element is selected.

[0010]

According to the first aspect of the invention, the output signal can be taken out from any one of the outer peripheral sides of the first block.
Therefore, it is possible to give some options to the output signal extraction direction, and it is possible to enhance the flexibility of layout design. According to the second aspect of the invention, since the same electrode (source electrode or drain electrode) of the MOS transistor is located at both ends of the array of the output transistors, the output signal can be taken out from either of the both ends. Therefore, the choices can be further increased and the layout flexibility can be further enhanced.

According to the third aspect of the invention, since only the wiring design of a unique element has to be performed for each logic circuit to be designed, the layout design efficiency is improved although the layout is limited to a specific logic circuit group. Can be achieved.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are views showing an embodiment of a semiconductor integrated circuit according to the invention described in claim 1 or claim 2. FIG. 1 is a schematic layout thereof, and FIG. 2 is a detailed layout of its main part.

In FIG. 1, 10 and 11 are parallel pairs.
Power supply wiring (for example, V_CCPower supply and V _EEPower) and one
A conventional control block is provided between the pair of power supply wirings 10 and 11.
Rectangular block 12 corresponding to 3 (described in the summary of the invention)
Corresponding to the second block:
U) is arranged. 13 corresponds to the conventional output block
Block (corresponding to the first block described in the summary of the invention)
Corresponding: hereinafter referred to as "first block").

The first block 13 is composed of a pull-up region 13a, a pull-down region 13b, and a connecting region 13c connecting one end sides of these two regions, and is formed in a concave shape as a whole. The concave portion 13 of the first block 13
The power supply wirings 10 and 11 and the second block 12 are housed inside d, and the pull-up region 12a of the second block 12 has the pull-up area of the first block 13 sandwiching one power supply wiring 10 therebetween. The pull-down region 12 b of the second block 12 faces the pull-up region 13 a, and the pull-down region 12 b of the second block 12 faces the pull-down region 13 b of the first block 13 with the other power supply line 11 interposed therebetween.

A plurality of output transistors (not shown) are formed in the pull-up region 13a and the pull-down region 13b of the first block 13, and the second block is formed in the second block.
A plurality of control transistors (not shown) are formed in the pull-up region 12a and the pull-down region 12b of the block 12. The control transistor drives the output transistor in response to the input signal IN, and the output transistor drives the input of a load or other logic circuit connected to an output terminal or output pad (not shown) in response to the drive of the control transistor. It is a thing.

The two signals OUTa and OUTb extracted from the right end side of the first block 13 are signals (output signals) for driving an input of a load or another logic circuit, and the upper output signal OUTa is The output signal OUTb on the lower side is in the pull-up operation, and the lower output signal OUTb is in the pull-down operation. The input signal signal IN and the output signal signal OUT
An imaginary line connecting a and OUTb schematically represents the flow of signals, and in this example, some signals are returned from the first block 13 to the second block 12. .

In the above configuration, the first block 13
Is a pair of power supply wirings 10 and 11 and a second block 12.
It is laid out so as to surround the three directions. That is, in the example of FIG. 1, the first block 13 surrounds the pair of power supply lines 10 and 11 and the second block 12 in the upper, lower, and right directions.
The outer periphery of 3 is completely opened from these power supply wirings 10 and 11 and the second block 12.

Therefore, the output signals OUTa, OUTb
Is not fixed only on the right side of the figure, for example,
Upper side (OUTa ', OUTb') and left side (OUTa ",
OUTb ″) as well. As a result, it is possible to give some choices to the output signal extraction direction, and to enhance the flexibility of layout design.

FIG. 2 shows the layout of the main part of the first block 13, and here shows the layout of the pull-down area 13b. Reference numeral 14 is a diffusion region, 15 is a gate wiring, 16 is a power supply wiring (corresponding to the power supply wiring 11 in FIG. 1), 1
Reference numeral 7 is an output wiring, and 18 to 31 are contacts. The six branch lines 32 to 37 extending from the gate wiring 15 function as the gate electrodes of the MOS transistors that are output transistors, and the source electrode and the drain electrode are arranged on both sides of each branch line 32 to 37. here,
The electrodes connected to the power supply wiring 16 are drain electrodes 38 to 4
0, the electrodes connected to the output wiring 17 are source electrodes 41 to 4
4 is set.

That is, in this example, the source electrode 41,
The gate electrode 32 and the drain electrode 38 form the first MOS transistor 45, and the drain electrode 38 and the gate electrode 33.
The source electrode 42 and the second MOS transistor 46.
The source electrode 42, the gate electrode 34, and the drain electrode 39 have a third MOS transistor 47, and the drain electrode 39, the gate electrode 35, and the source electrode 43 have a fourth MO transistor 47.
The S transistor 48 has a source electrode 43 and a gate electrode 3
6 and drain electrode 40 form the fifth MOS transistor 4
A drain electrode 40, a gate electrode 37 and a source electrode 44 form a sixth MOS transistor 50.

The layout of FIG. 2 is characterized in that the output transistor is composed of an even number (six in the figure) of MOS transistors arranged in parallel. According to this, since the electrodes 41 and 44 at both ends of the array are the same electrode (source electrode in the illustrated example), it is possible to take out the output signal on either side. 3 to 5 are views showing an embodiment of a semiconductor integrated circuit according to the invention described in claim 3.

FIG. 3 shows a signal OUT having the same phase as the input signal IN.
Is a single-input non-inverting circuit (buffer circuit) that outputs
In FIG. 3, 60, 61, and 62 are high-potential-side power supplies V_CC(Example
Speaking of V_CC= + 5V power line (hereinafter "high-potential-side power line")
, 63, 64, 65 are low-potential-side power supplies V _EE(example
If V_EE= 0V power supply line (hereinafter referred to as "low potential side power supply line")
), 66 is an output terminal connected to a load (not shown).
It is a force node.

Between the high potential side power supply line 60 and the output node 66, a p-channel type MOS transistor (hereinafter referred to as "p
MOS ") 67 is interposed, and this pMOS67
Is turned on when an L level is applied to the gate and connects the high potential side power supply line 60 and the output node 66 with a minute ON resistance close to 0Ω, and serves as an output transistor on the pull-up side. It works.

The low potential side power supply line 65 and the output node 6
An n-channel type MOS transistor (hereinafter referred to as “nMOS”) 68 is interposed between the n-channel MOS transistor 6 and the n-channel MOS transistor 6.
68 turns on when an H level is applied to the gate,
Almost 0Ω between the low potential side power line 65 and the output node 66
It is connected with a small ON resistance close to, and functions as an output transistor on the pull-down side.

69 is a pMOS 69a and an nMOS 69b
And 70 are inverter gates (hereinafter, referred to as “second logic unit”) composed of pMOS 70a and nMOS 70b, and first and second logic units 69. , 70 are input signals I
It outputs a first logic signal Sa and a second logic signal Sb which are the inverted logics of N, respectively.

The first logic signal Sa is applied to the gate of the pMOS 67. The gate of the pMOS 67 is supplied to the high potential side power source V through the pMOS 71 which is turned on under a predetermined condition.
It is designed to be pulled up to _CC . Further, the second logic signal Sb is given to the gate of the nMOS 68,
The gate of the nMOS 68 is turned on under a predetermined condition.
It is adapted to be pulled down to the low potential side power source V _EE via the MOS 72.

Reference numeral 73 is an inverter gate composed of a pMOS 73a and an nMOS 73b. The inverter gate 73 compares a predetermined threshold value with the potential of the output node 66 to determine the logic of the output node 66 (that is, the signal OU).
Detection signal Sc having a logic state (here, a reverse phase logic state) corresponding to the confirmed logic.
Is output.

Reference numeral 74 denotes an nMO which is turned on when the detection signal Sc is at H level and permits the operation of the first logic section 69.
S and 75 are pMOSs that are turned on when the detection signal Sc is at L level to permit the operation of the second logic unit 70.
The nMOS 74 permits the operation of the first logic section 69 when the logic state of the output node 66 is at the L level, in other words, when it is not the logic state corresponding to the high potential side, and the first logic section 69 operates. If the input signal IN is at H level when allowed, the first logic signal Sa is set at L level and the pMOS
Turn on 67.

Further, the pMOS 75 permits the operation of the second logic section 70 when the logic state of the output node 66 is at H level, in other words, when it is not the logic state corresponding to the low potential side, the second logic section 70 is operated. When the input signal IN is L level when the operation is permitted, the unit 70 sets the second logic signal Sb to H level to turn on the nMOS 68. Note that 76 is p
PMOS and 77 are nMOS connected in parallel to MOS67
NMOS connected in parallel with 68, the on resistance of pMOS 76 is higher than the on resistance of pMOS 67, and
For example, the size of the nMOS 77 is adjusted so that the on resistance of the nMOS 77 is higher than that of the nMOS 68.

In such a configuration, the output signal O
If UT is stable at L level, for example, the output of the inverter gate 73, that is, the detection signal Sc is stable at H level. Therefore, with this Sc, n
The MOS 74, nMOS 72, and nMOS 77 are on. Therefore, the gate of the nMOS 68 is the nMOS 72.
Is pulled down to V _EE (the second logic signal Sb is fixed at the L level) through the nMOS 68, and the nMOS 68 is in a completely off state.

At this time, the first logic section 69 is an nMOS.
The operation is permitted by 74, and when the input signal IN changes from the L level to the H level in this operation permitted state, the logic state of the first logic signal Sa changes from the H level to the L level, so that , This first logic signal Sa
In response to the change of the L level to the L level, the pMOS 67 is turned on.

When the pMOS 67 is turned on, the load connected to the output node 66 is charged toward the high potential side power supply V _CC , and the potential of the output node 66 is changed to the load capacitance or pMOS 6.
7 gradually starts to rise according to the time constant determined by the ON resistance of 7 and the like. When the potential of the output node 66 exceeds the threshold value of the inverter gate 73 after a predetermined time (the time corresponding to the above time constant), that is, when the logic of the output node 66 is set to the H level, the detection signal Sc becomes From H level to L
Changes to the level, and in response to this change, the nMOS7
4, the nMOS 72 and the nMOS 77 are turned off and the pMOS 75 and the pMOS 75 are turned off at substantially the same timing.
71 and pMOS 76 are turned on.

The gate of the pMOS 67 is the pMOS
It is pulled up to V _CC via 71 (the first logic signal Sa is fixed at H level), the pMOS 67 immediately changes to a completely off state, and the charging path for the load capacitance is cut off. That is, the pMOS 67 is turned on in response to the change of the input signal IN from the L level to the H level, and the change of the detection signal Sc from the L level to the H level (the output node 6).
Since it is turned off in response to the logic determination (6), the turn-on period can be limited to only the period required for charging the load capacitance.

The nMOS 68 is the pMO described above.
Contrary to the operation of S67, from the H level of the input signal IN to L
It turns on in response to a change in level and turns off in response to a change in the detection signal Sc from H level to L level (logic determination of the output node 66). Therefore, the turn-on period is a period required for discharging the load capacitance. Can be limited to only.

Thus, in the circuit of FIG. 3, the input signal I
In response to the change of N level from L level to H level, pMOS6
7 is turned on and the output signal OUT is changed to H level, while the nMOS 68 is turned on in response to the change of the input signal IN from H level to L level, and the output signal O
The UT can be transited to the L level. This operation is a non-inverting buffer operation, and thus forms a single-input non-inverting logic circuit.

Here, FIG. 4 shows a configuration of a 2-input AND logic circuit, but when compared with the configuration of FIG. 3, most of them are common except some elements. When common elements are given the same reference numerals, the elements unique to this 2-input AND logic circuit are pMOS 78, 79 and nMOS 8 surrounded by broken lines.
There are only four elements, 0 and 81. Further, FIG. 5 shows a configuration of a 3-input AND logic circuit, but when compared with the configuration of FIG. 4, this is also almost the same except for some elements. Similarly, when the same reference numerals are given to common elements, the elements unique to this 3-input AND logic circuit are p
There are only four elements: MOS 82, 83 and nMOS 84, 85.

Therefore, all elements of FIG.
And the elements specific to FIG. 5 (pMOS 78, 79, 82, 8
3 and nMOS 80, 81, 84, 85) in advance and, for example, by selecting four elements 3 of pMOS 78, 79 and nMOS 80, 81 for wiring design, in this case, a 2-input AND logic circuit Can be configured.

That is, in this embodiment, an element common to a plurality of different kinds of logic circuits (for example, a single-input non-inverting logic circuit, a 2-input AND logic circuit and a 3-input AND logic circuit) and each of the logic circuits are provided. Since all of the unique elements are created in advance and the unique elements are selected according to the type of logic circuit to be designed, the efficiency of layout design is improved, although it is limited to a specific logic circuit group. Can be achieved.

[0039]

According to the first aspect of the present invention, the output signal can be taken out from any of the outer peripheral sides of the first block. Therefore, it is possible to give some options to the output signal extraction direction, and it is possible to enhance the flexibility of layout design. According to the second aspect of the invention, since the same electrode (source electrode or drain electrode) of the MOS transistor is located at both ends of the array of the output transistors, the output signal can be taken out from either of the both ends. Therefore, the choices can be further increased and the layout flexibility can be further enhanced.

According to the third aspect of the invention, since only the wiring design of the unique element has to be performed for each logic circuit to be designed, the layout design is limited to a specific logic circuit group. Efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a schematic layout diagram of a semiconductor integrated circuit according to a first aspect of the invention.

FIG. 2 is a detailed layout diagram of a main part of the semiconductor integrated circuit according to the second aspect of the invention.

FIG. 3 is a configuration diagram of a single-input non-inverting logic circuit of the semiconductor integrated circuit according to the invention of claim 3;

FIG. 4 is a semiconductor integrated circuit 2 according to the invention of claim 3;
It is a block diagram of an input AND logic circuit.

FIG. 5 is a semiconductor integrated circuit 3 according to the invention of claim 3;
It is a block diagram of an input AND logic circuit.

FIG. 6 is a schematic layout diagram of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 13: 1st block 12: 2nd block 10, 11: Power supply wiring 45-50: MOS transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/04 A D

Claims (3)

[Claims] 1. A semiconductor integrated circuit having an output transistor for driving a load connected to an output terminal or an output pad or an input of another logic circuit, and a control transistor for driving the output transistor. The first block including the control transistor surrounds three sides of the second block including the control transistor, and the power supply wiring is arranged between the two opposite sides of the second block and the first block. Integrated semiconductor circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the first block includes an output transistor including an even number of MOS transistors arranged in parallel. 3. An element common to a plurality of different kinds of logic circuits and an element unique to each of the logic circuits are previously formed in advance, and the unique element is provided according to the kind of the logic circuit to be designed. A method for laying out a semiconductor integrated circuit, wherein: is selected.