JP3279829B2 - Semiconductor integrated circuit and layout method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a layout method thereof, and more particularly to a technique for improving the efficiency of layout design.

[0002]

2. Description of the Related Art In general, in the layout design of a semiconductor integrated circuit, it is required to shorten a signal path as much as possible and to set an appropriate wiring width. For example, a composite logic circuit, a feedback logic circuit, etc. In element logic circuits, the number of elements (transistors) is large and the size of each element varies, so that these requirements cannot be easily satisfied.

FIG. 6 is a schematic layout of a conventional multi-element logic circuit. Reference numerals 1 and 2 denote a pair of parallel power supply wirings (for example, a V _CC power supply and a V _EE power supply). A control block 3 and an output block 4 are laid out side by side between the pair of power supply wirings 1 and 2. . Each block 3, 4
Pull-up area 3a, 4a and pull-down area 3 respectively
b, 4b, and a plurality of transistors (not shown) are laid out in each region.

A transistor (not shown) inside the control block 3 (hereinafter, “control transistor”) is provided with an input signal IN.
That drives a transistor (also referred to as an “output transistor”) inside the output block 4 also in response to the control signal. The output transistor is an output terminal or an output not shown in response to the driving of the control transistor. It drives a load connected to a pad or an input of another logic circuit (hereinafter, “represented by a load”).

[0005] Two signals OUTa and OUTb taken out from the right end of the output block 4 are signals (output signals) for driving a load, and the upper output signal OUTa is for a pull-up operation and the lower output signal OUTa. Is the output signal OUTb during the pull-down operation. Note that the input signal IN
A virtual line connecting the output signal OUTa and the output signal OUTb schematically represents a signal flow. In this example,
Some signals are returned from the output block 4 to the control block 3.

[0006]

However, in such a conventional semiconductor integrated circuit, a control block 3 and an output block 4 are laid out side by side between two parallel power supply wires 1 and 2. Therefore, there is a disadvantage that the output signal extraction direction is fixed to one direction. For example, in the case of FIG. 6, the output signal is fixed to the right of the output block 4, so that the layout design is flexible. There was room for improvement.

[0007]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to increase the flexibility of layout design by giving several options in the direction of extracting an output signal.

[0008]

According to the first aspect of the present invention,
In a semiconductor integrated circuit having an output transistor for driving an input of a load or another logic circuit connected to an output terminal or an output pad, and a control transistor for driving the output transistor, a first integrated circuit including the output transistor A block surrounds three sides of the second block including the control transistor, and a power supply line is arranged between two opposing sides of the second block and the first block.

According to a second aspect of the present invention, in the first aspect, the first block includes an output transistor composed of an even number of MOS transistors arranged in parallel .

[0010]

According to the first aspect of the present invention, it is possible to take out the output signal from anywhere on each side of the outer periphery of the first block.
Therefore, several options can be given to the output signal extraction direction, and the flexibility of layout design can be increased. According to the second aspect of the present invention, since the same electrode (source electrode or drain electrode) of the MOS transistor is located at both ends of the output transistor array, an output signal can be taken out from either end. Therefore, the options can be further increased, and the layout flexibility can be further enhanced.

[0011]

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show a first example of a semiconductor integrated circuit according to the present invention.
FIG. 1 is a diagram showing an embodiment, FIG. 1 is a schematic layout thereof, and FIG. 2 is a detailed layout of a main part thereof.

In FIG. 1, reference numerals 10 and 11 denote parallel pairs.
Power supply wiring (for example, V_CCPower and V _EEPower)
A conventional control block is provided between the pair of power supply wirings 10 and 11.
The rectangular block 12 corresponding to 3 (described in the summary of the invention)
Equivalent to the second block of the following: hereinafter referred to as "the second block"
U) is arranged. 13 corresponds to the conventional output block.
Corresponding block (the first block described in the summary of the invention)
Corresponding: hereinafter referred to as "first block").

The first block 13 includes a pull-up area 13a, a pull-down area 13b, and a connection area 13c connecting one end of these two areas, and is formed in a concave shape as a whole. Concave portion 13 of first block 13
The power supply wirings 10 and 11 and the second block 12 are accommodated inside d. The pull-up area 12a of the second block 12 is connected to the pull-up area of the first block 13 with one of the power supply wirings 10 interposed therebetween. The pull-down region 12b of the second block 12 faces the pull-up region 13b of the first block 13 with the other power supply line 11 interposed therebetween.

In the pull-up region 13a and the pull-down region 13b of the first block 13, a plurality of output transistors (not shown) are formed.
A plurality of control transistors (not shown) are formed in the pull-up region 12a and the pull-down region 12b of the block 12. The control transistor drives an output transistor in response to an input signal IN, and the output transistor drives an input of a load or another logic circuit connected to an output terminal or an output pad (not shown) in response to the drive of the control transistor. Things.

The two signals OUTa and OUTb extracted from the right end of the first block 13 are signals (output signals) for driving an input of a load or another logic circuit, and the upper output signal OUTa is The output signal OUTb during the pull-up operation and the lower output signal OUTb are those during the pull-down operation. Note that the input signal signal IN and the output signal signal OUT
A virtual line connecting between a and OUTb schematically represents the flow of a signal. In this example, a part of the signal returns from the first block 13 to the second block 12. .

In the above configuration, the first block 13
Are a pair of power supply wirings 10 and 11 and a second block 12
Are arranged so as to surround the three directions. That is, in the example of FIG. 1, the first block 13 surrounds the upper, lower, and right directions of the pair of power supply lines 10 and 11 and the second block 12.
The outer periphery of 3 is completely open from these power supply wirings 10 and 11 and the second block 12.

Therefore, the output signals OUTa, OUTb
Is not fixed only on the right side of the figure, for example,
The upper side (OUTa ', OUTb') and the left side (OUTa ",
OUTb "). As a result, several options can be given to the output signal extraction direction, and the flexibility of layout design can be increased.

FIG. 2 shows a layout of a main part of the first block 13, in which the layout of the pull-down area 13b is shown. 14 is a diffusion region, 15 is a gate wiring, 16 is a power supply wiring (corresponding to the power supply wiring 11 in FIG. 1), 1
7 is an output wiring, and 18 to 31 are contacts. Six branch lines 32 to 37 extending from the gate wiring 15 function as gate electrodes of MOS transistors as output transistors, and a source electrode and a drain electrode are arranged on both sides of each branch line 32 to 37, respectively. here,
Connect the electrodes connected to the power supply wiring 16 to the drain electrodes 38 to 4
0, the electrodes connected to the output wiring 17 are connected to the source electrodes 41 to 4
It is set to 4.

That is, in this example, the source electrode 41,
The first MOS transistor 45 includes the gate electrode 32 and the drain electrode 38, and the drain electrode 38 and the gate electrode 33.
And a second MOS transistor 46 with the source electrode 42
However, the third MOS transistor 47 includes the source electrode 42, the gate electrode 34, and the drain electrode 39, and the fourth MOS transistor 47 includes the drain electrode 39, the gate electrode 35, and the source electrode 43.
The S transistor 48 includes the source electrode 43 and the gate electrode 3
6 and the drain electrode 40, the fifth MOS transistor 4
Reference numeral 9 denotes a sixth MOS transistor 50 including the drain electrode 40, the gate electrode 37, and the source electrode 44.

A feature of the layout of FIG. 2 is that an output transistor is constituted by an even number (six in the figure) of MOS transistors arranged in parallel. According to this, since the electrodes 41 and 44 at both ends of the array are the same electrode (the source electrode in the illustrated example), it is possible to take out the output signal from either the left or right. 3 to 5 show a second embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 3 shows a signal OUT in phase with the input signal IN.
Is a single-input non-inverting circuit (buffer circuit).
3, reference numerals 60, 61, and 62 denote high-potential-side power supplies V._CC(Example
For example, V_CC= + 5V) power supply line (hereinafter “high-potential-side power supply line”)
, 63, 64, and 65 are low-potential-side power supplies V _EE(example
V_EE= 0V) power supply line (hereinafter referred to as “low potential side power supply line”).
), 66 is an output as an output terminal leading to a load (not shown).
Force node.

A p-channel MOS transistor (hereinafter “p”) is connected between the high-potential-side power supply line 60 and the output node 66.
MOS ”) 67, and the pMOS 67
Turns on when an L level is applied to the gate, and connects the high-potential-side power supply line 60 and the output node 66 with a small on-resistance close to 0Ω, and serves as an output transistor on the pull-up side. It works.

The low potential side power supply line 65 and the output node 6
6, an n-channel MOS transistor (hereinafter referred to as “nMOS”) 68 is interposed.
68 turns on when an H level is applied to the gate,
A voltage between the low-potential-side power supply line 65 and the output node 66 of approximately 0Ω
And a function as a pull-down output transistor.

Reference numeral 69 denotes a pMOS 69a and an nMOS 69b
, An inverter gate (hereinafter, referred to as a “second logic unit”) including a pMOS 70a and an nMOS 70b, and a first and a second logic unit 69 , 70 are the input signals I
A first logic signal Sa and a second logic signal Sb obtained by inverting the logic of N are output.

The first logic signal Sa is applied to the gate of the pMOS 67. The gate of the pMOS 67 is connected to the high potential side power supply V
_Pulled up to _CC . Also, the second logic signal Sb is given to the gate of the nMOS 68,
The gate of the nMOS 68 is turned on under a predetermined condition.
It is adapted to be pulled down to the low potential side power source V _EE through MOS72.

Numeral 73 denotes an inverter gate composed of a pMOS 73a and an nMOS 73b. The inverter gate 73 compares a predetermined threshold value with the potential of the output node 66 to determine the logic of the output node 66 (that is, the signal OU).
T is detected, and a detection signal Sc having a logic state (here, a logic state having an opposite phase) corresponding to the determined logic is detected.
Is output.

Reference numeral 74 denotes an nMO which is turned on when the detection signal Sc is at the H level to permit the operation of the first logic unit 69.
S and 75 are pMOSs that are turned on when the detection signal Sc is at the L level to allow the operation of the second logic unit 70.
The nMOS 74 allows the operation of the first logic unit 69 when the logic state of the output node 66 is at the L level, in other words, when the logic state of the output node 66 is not the logic state corresponding to the high potential side. When the input signal IN is at the H level during the permissible period, the first logic signal Sa is set to the L level and the pMOS
Turn on 67.

The pMOS 75 allows the operation of the second logic section 70 when the logic state of the output node 66 is at the H level, in other words, when the logic state of the output node 66 is not the logic state corresponding to the low potential side. If the input signal IN is at the L level when the operation is permitted, the unit 70 sets the second logic signal Sb to the H level to turn on the nMOS 68. 76 is p
A pMOS connected in parallel to the MOS 67 and an nMOS 77
68, the on-resistance of the pMOS 76 is higher than the on-resistance of the pMOS 67,
For example, the size is adjusted so that the on-resistance of the nMOS 77 is higher than the on-resistance of the nMOS 68.

In such a configuration, the output signal O
Assuming that the UT is stable at the L level, for example, the output of the inverter gate 73, that is, the detection signal Sc is stable at the H level. Therefore, this Sc gives n
MOS 74, nMOS 72 and nMOS 77 are on. Therefore, the gate of the nMOS 68 is
Pulled down (fixed second logic signal Sb to the L level) to V _EE through, NMOS68 is a fully off state.

At this time, the first logic unit 69 is an nMOS
74, the operation is permitted. When the input signal IN changes from the L level to the H level in this operation allowable state, the logic state of the first logic signal Sa changes from the H level to the L level. , The first logic signal Sa
In response to the change to the L level, the pMOS 67 is turned on.

When the pMOS 67 is turned on, the load connected to the output node 66 is charged toward the high potential side power supply V _CC , and the potential of the output node 66 is changed to the load capacitance or the pMOS 6.
7 and gradually starts to rise in accordance with a time constant determined by the on-resistance and the like. After a predetermined time (time corresponding to the above time constant), when the potential of output node 66 exceeds the threshold value of inverter gate 73, that is, when the logic of output node 66 is determined to be at the H level, detection signal Sc is output. H level to L
Level, and in response to this change, the nMOS7
4, the nMOS 72 and the nMOS 77 are turned off, and the pMOS 75 and the pMOS
71 and pMOS 76 turn on.

The gate of the pMOS 67 is a pMOS
Pulled up to V _CC through a 71 (first logic signal Sa fixed at H level) is, PMOS67 is changed to immediately complete OFF state, the charging path for the load capacitance is cut off. That is, the pMOS 67 is turned on in response to the change of the input signal IN from the L level to the H level, and the detection signal Sc changes from the L level to the H level (output node 6).
6), the turn-on period can be limited to only the period necessary for charging the load capacitance.

The nMOS 68 is provided by the pMO described above.
Conversely to the operation of S67, the input signal IN is changed from H level to L level.
It turns on in response to a change in the level and turns off in response to a change in the detection signal Sc from the H level to the L level (logic decision of the output node 66). Only.

As described above, in the circuit of FIG.
In response to the change of N from L level to H level, pMOS6
7 is turned on, causing the output signal OUT to transition to the H level, while the nMOS 68 is turned on in response to the change of the input signal IN from the H level to the L level, and the output signal O is output.
The UT can transition to the L level. This operation is a non-inverting buffer operation, and thus forms a single-input non-inverting logic circuit.

Here, FIG. 4 shows a configuration of a two-input AND logic circuit. However, as compared with the configuration of FIG. 3, most of them are common except for some elements. When the same reference numerals are given to the common elements, the elements unique to the two-input AND logic circuit are pMOS 78 and 79 and nMOS 8
There are only four elements 0 and 81. FIG. 5 shows a configuration of a three-input AND logic circuit. However, as compared with the configuration of FIG. 4, almost all of them are common except for some elements. Similarly, when the same reference numerals are given to the common elements, the elements unique to the three-input AND logic circuit are represented by p surrounded by a broken line.
There are only four elements, MOSs 82 and 83 and nMOSs 84 and 85.

Therefore, all the elements in FIG.
And elements unique to FIG. 5 (pMOS 78, 79, 82, 8
3 and nMOSs 80, 81, 84, and 85) are prepared in advance, and, for example, by selecting four elements 3 of pMOSs 78 and 79 and nMOSs 80 and 81 and performing wiring design, in this case, a two-input AND logic circuit Can be configured.

That is, in the present embodiment, an element common to a plurality of different types of logic circuits (for example, a single-input non-inverting logic circuit, a two-input AND logic circuit, and a three-input AND logic circuit), and an element common to each of the logic circuits All of the unique elements are created in advance, and the unique elements are selected according to the type of logic circuit to be designed. Therefore, the layout is limited to a specific logic circuit group, but the efficiency of layout design is improved. Can be achieved.

[0039]

According to the first aspect of the present invention, it is possible to take out an output signal from anywhere on each side of the outer periphery of the first block. Therefore, several options can be given to the output signal extraction direction, and the flexibility of layout design can be increased. According to the second aspect of the present invention, since the same electrode (source electrode or drain electrode) of the MOS transistor is located at both ends of the array of output transistors, it is possible to extract an output signal from either of the two ends. Therefore, the options can be further increased, and the layout flexibility can be further enhanced.

[0040]

[Brief description of the drawings]

FIG. 1 is a schematic layout diagram of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a detailed layout diagram of a main part of the semiconductor integrated circuit according to the present invention.

FIG. 3 is a configuration diagram of a single-input non-inverting logic circuit of the semiconductor integrated circuit according to the present invention.

FIG. 4 is a configuration diagram of a two-input AND logic circuit of the semiconductor integrated circuit according to the present invention.

FIG. 5 is a configuration diagram of a three-input AND logic circuit of the semiconductor integrated circuit according to the present invention.

FIG. 6 is a schematic layout diagram of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 13: first block 12: second block 10, 11: power supply wiring 45 to 50: MOS transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 21/822 H01L 27/04

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit comprising: an output transistor for driving an input of a load or another logic circuit connected to an output terminal or an output pad; and a control transistor for driving the output transistor. A first block including the control transistor, surrounding three sides of the second block including the control transistor, and a power supply line is disposed between two opposing sides of the second block and the first block. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein said first block includes an output transistor including an even number of MOS transistors arranged in parallel .