JPH0864678A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a convenient planarization method applicable to a case where the interval of wiring in a semiconductor chip is wide. CONSTITUTION: After forming an interlayer insulating film 15 on a substrate having level difference, an upper layer film 16 is formed and then the interlayer insulating film 15 is planarized through the upper layer film 16 by heating. The lower interlayer insulating 15 is composed of polyhydrogen silosesquioxane whereas the upper layer film 16 is composed of a low melting point metal. When it is heated at a temperature higher than the softening points of the upper and lower layers, the viscosity of the interlayer insulating film 15 decreases to fluidized the film 15 such that the surface energy is minimized. It is accelerated by the self weight of the upper layer film 16 and a sufficient planarity can be ensured even for a wide space wiring. The heating temperature is optimally set between 200 deg.C, at which the interlayer insulating film 15 is softened, and 400 deg.C at which the film 15 is changed to have a perfect three- dimensional mesh structure. This method improves planarity of the lower layer film 15 and ensures a good planarity even in case of wide wiring space.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to the manufacture of semiconductor devices. INDUSTRIAL APPLICABILITY The present invention can be utilized, for example, in manufacturing integrated semiconductor circuits such as highly miniaturized and highly integrated memory devices.

[0002]

2. Description of the Related Art With the advancement of semiconductor devices, wiring technology has been progressing toward miniaturization and multilayering. However, high integration of semiconductor devices may cause a decrease in wiring reliability. This is because the step of the interlayer insulating film becomes large and steep due to the miniaturization of wiring and the progress of multi-layering, and the processing accuracy and reliability of the wiring formed thereon are lowered. For this reason, it is necessary to develop a technique for improving the flatness of the interlayer insulating film at present when the step coverage of aluminum (Al) wiring cannot be significantly improved. Until now, various insulating film forming technologies and flattening technologies have been developed. However, when applied to miniaturized and multi-layered wiring layers, lack of flattening when the wiring spacing is wide and interlayer spacing in the wiring spacing Due to the occurrence of "stain" in the film, poor connection between wirings has become an important issue.

Therefore, as a means for improving the problems such as connection failure between wirings due to the occurrence of "su" in the interlayer film in the wiring space, there is a technique of filling the space between Al wirings of high aspect ratio with polyhydrogensilsesquioxane. Attention has been paid. Since this material has a softening point near 200 ° C., it has been reported that keeping this temperature causes fluidity and improves embedding and flatness. For this kind of technology, for example, 1993.
"VMIC Conference" June 8-9, 2014
Report, page 329.

[0004]

The method using polyhydrogensilsesquioxane has been able to improve the problem of connection failure between wirings due to the generation of "su" in the interlayer film in the wiring space. It is not possible to perform flattening in the case where the wiring interval in the chip is wide for the purpose of securing DOF in the lithography process. Therefore, there has been proposed an attempt to improve flatness by using a dummy pattern to narrow a portion having a large wiring interval in a chip. As a method of forming a dummy pattern, there are a method of forming an Al dummy layer when forming an Al wiring and a method of newly forming a dummy layer using an interlayer insulating film or the like. The increase is a problem, and the latter has a problem that the process is complicated because a dummy layer is newly formed. It is an object of the present invention to provide a planarization method that facilitates planarization when the wiring interval in a semiconductor device is wide.

[0005]

In order to achieve the above-mentioned object, the present invention is an intensive study to form an interlayer insulating film having a softening point in a manufacturing process of a semiconductor device, and then form an upper layer film having a low melting point. Then, the inventors have found a method of improving the flatness of the lower layer film by forming the film and then maintaining the temperature above the softening point of the upper and lower film. That is, the present invention is a method for manufacturing a semiconductor device, in which after forming an interlayer insulating film on a stepped substrate, forming an upper layer film, and then performing a process of lowering the viscosity of the interlayer insulating film through the upper layer film by heating, or A semiconductor in which an interlayer insulating film is formed on a stepped substrate, an upper layer film is formed, and the viscosity of the interlayer insulating film is lowered by heating to planarize the interlayer insulating film, and then the upper layer film is peeled off. It is a method of manufacturing a device.

In the method of manufacturing a semiconductor device of the present invention,
It is desirable to select the film forming materials so that the softening points of the lower interlayer insulating film and the upper film are within a predetermined range. The above-mentioned predetermined range is a range of about 50 ° C to 400 ° C. The heating temperature for lowering the viscosity of the lower interlayer insulating film is preferably between 200 ° C. and 400 ° C. at which the lower interlayer insulating film softens and changes into a complete three-dimensional structure. At least polyhydrogensilsesquioxane or polyalkylsilsesquioxane is used as the lower interlayer insulating film of the present invention, and 50 ° C. is used as the upper film.
A metal film having a low melting point of about 400 ° C. can be used. The low melting point metal film contains at least silver, lead, tin, copper, and cadmium. In the method of manufacturing a semiconductor device of the present invention, such a process can be sufficiently carried out by using a heat treatment device which is generally used.

[0007]

In the method for manufacturing a semiconductor device of the present invention, after forming an interlayer insulating film having a softening point, an upper layer film having a low melting point is formed, and thereafter, a temperature higher than the softening point of the upper and lower layer films is maintained. The flatness of the lower layer film is improved, and good flatness can be secured even in a wide wiring space. Polyhydrogensilsesquioxane as the lower interlayer insulating film of the present invention, using a low-melting point metal as the upper layer film, and by heating and holding at each softening point temperature of the upper and lower layers, the surface energy due to the lowering of the viscosity of the lower layer film The interlayer insulating film flows so as to be minimized. This flow of the interlayer insulating film is accelerated by the weight of the upper layer film, and sufficient flatness can be obtained even between the wirings having a large space. The optimum heating temperature is between 200 ° C. at which the lower interlayer insulating film is softened and 400 ° C. at which the lower film changes to a complete three-dimensional structure. The object of the present invention can be achieved by using, as the upper layer film, a low melting point metal film that is softened in the softening temperature range of the lower interlayer insulating film and does not react with the lower interlayer insulating film.

[0008]

Embodiments of the present invention will be described with reference to the drawings. Example 1 In this example, the present invention is applied to the case where an insulating film is formed on a silicon semiconductor wafer, which is a base having steps, during the manufacture of semiconductor integrated circuits. In particular, the present embodiment is an example of the case where the inorganic interlayer insulating film is formed on the Al wiring. As shown in FIG. 1A, a wafer was prepared in which an interlayer insulating film 12 made of silicon oxide and an Al wiring layer 13 were formed on a semiconductor substrate 11 made of silicon. Next, as shown in FIG. 1B, an interlayer film 14 was formed for the purpose of supplementing the film quality of the interlayer insulating film formed in the next step. Next, as shown in FIG. 1C, the interlayer insulating film 15 was formed under the following conditions. Material Solute Polyhydrogensilsesquioxane (HSi
O _3/2 ) n solvent Methyl isobutyl ketone Solid content 14% Forming condition Rotation speed 4000 rpm Heating condition 150 ° C., 60 sec

Next, after forming the low melting point metal layer 16,
By annealing at 300 ° C. in nitrogen, as shown in FIG.
Planarization was performed as shown in (a). As the low melting point metal, an Ag 9.5% -Sn 96.5% alloy having a melting point of 225 ° C. was used to form the upper layer film (low melting point metal layer) 16. afterwards,
As shown in FIG. 2B, the upper layer film (low melting point metal layer) 16
Was removed by acid solution. Finally, the interlayer insulating film 17 is formed by a conventional method so as to have a required film thickness, and the planarization of the interlayer insulating films 15 and 17 is completed as shown in FIG.

Embodiment 2 In this embodiment, the present invention is applied to the case where an insulating film is formed on a silicon semiconductor wafer which is a substrate having a step during the manufacture of a semiconductor integrated circuit. Particularly, the present embodiment is a case where the organic interlayer insulating film is formed on the Al wiring. This example is performed in the same procedure as in Example 1 except that the materials for the interlayer insulating film 15 and the low-melting point metal layer 16 in Example 1 are different, and will be described with reference to FIGS. FIG.
As shown in (a), a wafer was prepared in which an interlayer insulating film 12 made of silicon oxide and an Al wiring layer 13 were formed on a semiconductor substrate 11 made of silicon. Next, as shown in FIG. 1B, an interlayer film 14 was formed for the purpose of supplementing the film quality of the interlayer insulating film formed in the next step. Next, as shown in FIG. 1C, the interlayer insulating film 15 was formed under the following conditions. Material Solute Polymethylsilsesquioxane (CH ₃ Si
O _3/2 ) n solvent Methyl isobutyl ketone Solid content 14% Forming condition Rotation speed 3000 rpm Heating condition 150 ° C., 60 sec

Next, after forming the low melting point metal layer 16,
By annealing in nitrogen at 250 ° C., FIG.
Planarization was performed as shown in (a). An Sn64% -Pb36% alloy having a melting point of 200 ° C. was used as the low melting point metal to form the upper layer film (low melting point metal layer) 16. After that, Figure 2
As shown in (b), the upper layer film (low melting point metal layer) 16 was removed with an acid solution. Finally, the interlayer insulating film 17 is formed by a conventional method so as to have a required film thickness, and the planarization of the interlayer insulating films 15 and 17 is completed as shown in FIG. Although Ag-Sn and Sn-Pb alloys were used as the upper layer film (low melting point metal layer) 16 in Examples 1 and 2 above, the structure is not limited to this material and does not depart from the gist of the present invention. The conditions can be changed as appropriate. For example, as the upper layer film, Ag5% -Pb95%, Ag3.5% -Cu10
% -Sn 86.5%, Ag 5% -Cd 80% -Zn15
%, Etc. can be used.

[0012]

As described above, according to the present invention, it is possible to greatly improve the step coverage of miniaturized and multi-layered wiring and to form an interlayer insulating film having high flatness.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

11 ... Semiconductor substrate, 12 ... Interlayer insulating film, 13 ... Al wiring layer, 14, 15, 17 ... Interlayer insulating film, 16 ... Upper layer film (low melting point metal layer)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/3205

Claims (7)

[Claims] 1. After forming an interlayer insulating film on a stepped substrate,
A method for manufacturing a semiconductor device, comprising: forming an upper layer film; and then performing a treatment to reduce the viscosity of the interlayer insulating film through the upper layer film by heating. 2. After forming an interlayer insulating film on the stepped substrate,
A method for manufacturing a semiconductor device, comprising: forming an upper layer film, lowering the viscosity of the interlayer insulating film through the upper layer film by heating to flatten the interlayer insulating film, and then peeling the upper layer film. 3. The softening points of the lower interlayer insulating film and the upper film are 5 respectively.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is in the range of 0 [deg.] C. to 400 [deg.] C. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the heating temperature for lowering the viscosity of the lower interlayer insulating film is between 200 ° C. and 400 ° C. 5. The method for manufacturing a semiconductor device according to claim 1, wherein polyhydrogensilsesquioxane or polyalkylsilsesquioxane is used as the lower interlayer insulating film. 6. The method of manufacturing a semiconductor device according to claim 1, wherein a metal film having a melting point of 400 ° C. or lower is used as the upper layer film. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the metal film having a melting point of 400 ° C. or lower contains at least silver, lead, tin, copper and cadmium.