JPH0864401A - Chip-like electronic part - Google Patents
Chip-like electronic partInfo
- Publication number
- JPH0864401A JPH0864401A JP6201842A JP20184294A JPH0864401A JP H0864401 A JPH0864401 A JP H0864401A JP 6201842 A JP6201842 A JP 6201842A JP 20184294 A JP20184294 A JP 20184294A JP H0864401 A JPH0864401 A JP H0864401A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- layer
- chip
- substrate
- paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Details Of Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、チップ抵抗器、チップ
ネットワーク抵抗器、厚膜ハイブリッドＩＣ等のセラミ
ック基板の一方の面に電子素子を有する面実装タイプの
チップ状電子部品に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type chip-like electronic component having an electronic element on one surface of a ceramic substrate such as a chip resistor, a chip network resistor and a thick film hybrid IC.
【０００２】[0002]
【従来の技術】チップ抵抗器、チップネットワーク抵抗
器、厚膜ハイブリッドＩＣ等の面実装タイプのチップ状
電子部品は、アルミナ等のセラミック基板の上面側に抵
抗体等の電子素子が設けられ、上記セラミック基板の下
面側はその大半がセラミック表面が露出した状態であ
る。2. Description of the Related Art A surface mount type chip-shaped electronic component such as a chip resistor, a chip network resistor and a thick film hybrid IC is provided with an electronic element such as a resistor on the upper surface side of a ceramic substrate such as alumina. Most of the lower surface side of the ceramic substrate has a ceramic surface exposed.
【０００３】例えば、従来のチップ抵抗器は、図２に示
すように、セラミック基板１１と、該セラミック基板１
１の上面の両端部に設けられた一対の上面電極層１２
と、上記セラミック基板１１の下面の両端部に設けられ
た一対の下面電極層１３と、上記一対の上面電極層１２
に跨って設けられた抵抗体層１４と、該抵抗体層１４上
に設けられた保護層１５と、上記セラミック基板１１の
両端面に上記上面電極層１２と上記下面電極層１３とに
接続するように設けられた側面電極層１６と、上記上面
電極層１２、下面電極層１３及び側面電極層１６の露出
部上に設けられたニッケルメッキ層及び半田メッキ層か
らなるメッキ層１７と、から構成されており、上記セラ
ミック基板１１の下面における一対の下面電極層１３間
はセラミック基板が露出した状態となっている。For example, a conventional chip resistor has a ceramic substrate 11 and a ceramic substrate 1 as shown in FIG.
1. A pair of upper surface electrode layers 12 provided on both ends of the upper surface of No. 1
A pair of lower surface electrode layers 13 provided on both ends of the lower surface of the ceramic substrate 11, and a pair of upper surface electrode layers 12
The resistor layer 14 provided over the resistor layer 14, the protective layer 15 provided on the resistor layer 14, and the upper surface electrode layer 12 and the lower surface electrode layer 13 connected to both end surfaces of the ceramic substrate 11. And a plating layer 17 made of a nickel plating layer and a solder plating layer provided on the exposed portions of the upper surface electrode layer 12, the lower surface electrode layer 13, and the side surface electrode layer 16 described above. The ceramic substrate is exposed between the pair of lower surface electrode layers 13 on the lower surface of the ceramic substrate 11.
【０００４】これらチップ状電子部品は、一般に図３に
示すように、チップ状電子部品Ａの上面の略中央部を実
装機における吸着コレットＢ等により保持され、プリン
ト基板等の実装基板Ｃ上の所定の位置に搬送・搭載し半
田付けされて用いられる。As shown in FIG. 3, these chip-shaped electronic components are generally held on the upper surface of the chip-shaped electronic component A by a suction collet B or the like in a mounting machine and mounted on a mounting substrate C such as a printed circuit board. It is used after being transported and mounted at a predetermined position and soldered.
【０００５】[0005]
【発明が解決しようとする課題】上記のようにチップ状
電子部品Ａを実装機で実装するとき、上記チップ状電子
部品Ａは、吸着コレットＢで実装基板Ｃ上に搭載される
ために、上記チップ状電子部品Ａには、上記吸着コレッ
トＢによる上方からの押圧力が及ぶことになり、図４に
示すように、チップ状電子部品Ａが割れるという問題が
ある。特に上記に示したチップ抵抗器のように、下面電
極層１３が形成された部分が、下面電極層１３間のセラ
ミック基板の露出面から突出している如く、チップ状電
子部品Ａがその下面両端部で実装基板Ｃに支持される場
合は、上記両端部が支点となって吸着コレットＢにより
チップ状電子部品Ａのセラミック基板が露出する中央部
がたわみ上記割れが生じ易いのである。When the chip-shaped electronic component A is mounted by the mounting machine as described above, since the chip-shaped electronic component A is mounted on the mounting substrate C by the suction collet B, the above-mentioned Since the chip-shaped electronic component A is subjected to a pressing force from above by the suction collet B, there is a problem that the chip-shaped electronic component A is cracked as shown in FIG. In particular, like the chip resistor described above, the chip-shaped electronic component A has its lower end portions so that the portion where the lower surface electrode layer 13 is formed protrudes from the exposed surface of the ceramic substrate between the lower surface electrode layers 13. In the case of being supported by the mounting substrate C, the above-mentioned both ends serve as fulcrums, and the central portion where the ceramic substrate of the chip-shaped electronic component A is exposed is deflected by the suction collet B, and the above crack is likely to occur.
【０００６】また、上記チップ状電子部品Ａの割れの問
題は、チップ状電子部品Ａを実装基板等に実装した後
に、熱により上記実装基板が膨張し、反りが生じたとき
にも発生することがあるのである。この割れは、チップ
状電子部品に用いられるセラミック基板を製造したとき
に該セラミック基板の表面に生じたボイドや製造後に生
じたキズの部分でセラミック基板の割れ強度（抗折強
度）が低下し、上記ボイドもしくはキズにある一定以上
の応力がかかったときに、該ボイドもしくはキズを起点
として起点として亀裂が発生することにより生じるので
ある。この割れの原因となるボイドは、例えばアルミナ
基板であれば、アルミナの純度が低下するに従い発生率
が大きくなる。しかしながら、通常用いられるアルミナ
基板は、アルミナ含有率が約９６〜９７％で、不純物或
いは添加物として例えば酸化シリコン、酸化カルシウ
ム、酸化マグネシウム等が含まれ、このアルミナ基板を
よりアルミナ含有率の高いものとすると、アルミナ基板
を製造するときの焼成温度が高くなり工程管理を困難と
し、消費エネルギー的にも不利となり好ましくない。The problem of cracking of the chip-shaped electronic component A also occurs when the chip-shaped electronic component A is mounted on a mounting board or the like and then the mounting board expands due to heat and warps. There is. The cracks reduce the crack strength (flexural strength) of the ceramic substrate due to voids generated on the surface of the ceramic substrate when manufacturing the ceramic substrate used for the chip-shaped electronic component and scratches generated after the manufacturing, This is caused by the occurrence of cracks starting from the voids or scratches as a starting point when a certain stress or more is applied to the voids or scratches. In the case of an alumina substrate, for example, the voids that cause the cracks increase in occurrence rate as the purity of alumina decreases. However, the alumina substrate usually used has an alumina content of about 96 to 97% and contains, for example, silicon oxide, calcium oxide, magnesium oxide, etc. as impurities or additives, and this alumina substrate has a higher alumina content. If so, the firing temperature at the time of manufacturing the alumina substrate becomes high, which makes the process control difficult and is disadvantageous in terms of energy consumption, which is not preferable.
【０００７】また、上記チップ抵抗器等は、実装基板に
実装された状態において、セラミック基板の下面におけ
る電極層の面が、セラミック基板の下面におけるセラミ
ック基板の露出面よりも下方に位置するために、上記セ
ラミック基板の下面における電極層と実装基板における
配線パターンの所定の接続部との間に半田層が介在し難
く、もっぱらセラミック基板の端面と上記接続部との間
に生じる半田フィレットにより接続されていることにな
り、半田付け強度が必ずしも十分とは言えなかった。更
に、上記のようにセラミック基板の下面における電極層
の面が、セラミック基板の下面におけるセラミック基板
の露出面よりも下方に位置するために、実装基板等に実
装した状態では、上記セラミック基板の露出面と実装基
板との間に僅かな隙間が生じ、電子部品が小型になるに
つれて、上記隙間に半田が流れ込み電極層間でショート
不良を招来する危険性が生じるのである。Further, in the above chip resistor and the like, the surface of the electrode layer on the lower surface of the ceramic substrate is located below the exposed surface of the ceramic substrate on the lower surface of the ceramic substrate when mounted on the mounting substrate. The solder layer is unlikely to be interposed between the electrode layer on the lower surface of the ceramic substrate and the predetermined connection portion of the wiring pattern on the mounting substrate, and is exclusively connected by the solder fillet generated between the end surface of the ceramic substrate and the connection portion. The soldering strength was not always sufficient. Further, as described above, since the surface of the electrode layer on the lower surface of the ceramic substrate is located below the exposed surface of the ceramic substrate on the lower surface of the ceramic substrate, the surface of the ceramic substrate is exposed when mounted on a mounting board or the like. A slight gap is generated between the surface and the mounting substrate, and as the electronic component becomes smaller, solder may flow into the gap and cause a short circuit defect between the electrode layers.
【０００８】本発明は、上記チップ状電子部品の抗折強
度を向上して、上記割れの問題を軽減乃至解消すること
を目的とする。また、本発明は、チップ状電子部品の実
装基板等に対する半田付け強度を向上し、更には実装時
の電極層間のショート不良の軽減を図ることを目的とす
る。It is an object of the present invention to improve the bending strength of the chip-shaped electronic component and reduce or eliminate the problem of cracking. Another object of the present invention is to improve the soldering strength of a chip-shaped electronic component to a mounting board or the like, and further to reduce a short circuit defect between electrode layers during mounting.
【０００９】[0009]
【課題を解決するための手段】本発明は、上記目的を達
成すべくなされたもので、次のチップ状電子部品に係る
ものである。 セラミック基板の上面に電子素子が設けられ、上記
セラミック基板の下面に直接的に絶縁層が設けられてい
ることを特徴とするチップ状電子部品。The present invention has been made to achieve the above object, and relates to the following chip-shaped electronic component. An electronic element is provided on the upper surface of a ceramic substrate, and an insulating layer is provided directly on the lower surface of the ceramic substrate, which is a chip-shaped electronic component.
【００１０】 セラミック基板の両端部に、該セラミ
ック基板の上面、端面及び下面に亘って電極層が設けら
れている上記に記載のチップ状電子部品。 絶縁層の厚みがセラミック基板における下面の電極
層の厚みと同一もしくはそれ以上であるに記載のチッ
プ状電子部品。 絶縁層の熱膨張係数がセラミック基板の熱膨張係数
と同一もしくはそれ以上であることを特徴とする上記
〜に記載のチップ状電子部品。The chip-shaped electronic component described above, in which electrode layers are provided on both ends of the ceramic substrate over the upper surface, the end surface, and the lower surface of the ceramic substrate. The chip-shaped electronic component according to claim 1, wherein the thickness of the insulating layer is equal to or greater than the thickness of the electrode layer on the lower surface of the ceramic substrate. The chip-shaped electronic component described in any one of 1 to 3, wherein the thermal expansion coefficient of the insulating layer is equal to or higher than the thermal expansion coefficient of the ceramic substrate.
【００１１】[0011]
【発明の作用及び効果】上記のようにチップ状電子部品
におけるセラミック基板の下面に直接的に絶縁層を設け
たので、該絶縁層下のセラミック基板表面にあるボイ
ド、キズ等には、上記絶縁層が充填され、セラミック基
板は補強され強度が向上されることとなる。従って、チ
ップ状電子部品の割れの問題を略解消し得るのである。As described above, since the insulating layer is provided directly on the lower surface of the ceramic substrate in the chip-shaped electronic component as described above, the above-mentioned insulation is applied to the voids, scratches and the like on the surface of the ceramic substrate below the insulating layer. The layers will be filled and the ceramic substrate will be reinforced and increased in strength. Therefore, the problem of cracking of the chip-shaped electronic component can be substantially eliminated.
【００１２】上記チップ状電子部品におけるセラミック
基板の両端部に、該セラミック基板の上面、端面及び下
面に亘って電極層を設け、且つ上記絶縁層の厚みをセラ
ミック基板の下面における電極層の厚みと同一もしくは
それ以上としたときは、これを実装基板等に半田付けに
より実装したときに、実装基板と絶縁層との間に僅かな
隙間が生じるか或いは上記隙間が殆ど生じなくなり、セ
ラミック基板の下面において、上記セラミック基板の両
端部の電極層間でショートを生じる危険性を軽減できる
のである。Electrode layers are provided on both ends of the ceramic substrate of the above-mentioned chip-shaped electronic component over the upper surface, the end surface and the lower surface of the ceramic substrate, and the thickness of the insulating layer is the same as the thickness of the electrode layer on the lower surface of the ceramic substrate. When they are the same or more, when they are mounted on a mounting board or the like by soldering, a slight gap is generated between the mounting substrate and the insulating layer, or the above-mentioned gap hardly occurs, and the lower surface of the ceramic substrate In the above, the risk of causing a short circuit between the electrode layers at both ends of the ceramic substrate can be reduced.
【００１３】また、上記において、絶縁層の厚みをセラ
ミック基板の下面における電極層の厚みよりも厚くし
て、実装したときに上記下面における電極層と実装基板
の配線パターンにおける接続部との間に隙間が生じると
きは、この隙間に半田が介在して良好な半田フィレット
が生じ、半田付け強度が向上するのである。更に、本発
明において上記絶縁層の熱膨張係数をセラミック基板の
ものよりも大きくしたときは、チップ状電子部品に熱ス
トレスがかかった場合、該チップ状電子部品のセラミッ
ク基板の膨張率よりも上記絶縁層の膨張率が大きいこと
となり、絶縁層はセラミック基板に比して柔軟的となる
ので、絶縁層はセラミック基板により膨張を抑制される
方向に力が作用し、絶縁層のより効果的な熱的強度を得
ることができ、絶縁層に亀裂や割れが生じ、セラミック
基板が割れることを一段と軽減できるのである。In addition, in the above, the thickness of the insulating layer is made thicker than the thickness of the electrode layer on the lower surface of the ceramic substrate, and when mounted, the electrode layer on the lower surface and the connection portion in the wiring pattern of the mounting substrate are mounted. When a gap is formed, the solder intervenes in this gap to form a good solder fillet, and the soldering strength is improved. Further, in the present invention, when the thermal expansion coefficient of the insulating layer is set to be larger than that of the ceramic substrate, when the chip-shaped electronic component is subjected to thermal stress, the expansion coefficient of the ceramic substrate of the chip-shaped electronic component is higher than that of the ceramic substrate. Since the expansion coefficient of the insulating layer is large and the insulating layer is more flexible than the ceramic substrate, a force acts on the insulating layer in the direction in which the expansion is suppressed by the ceramic substrate, and the insulating layer is more effective. It is possible to obtain thermal strength, and it is possible to further reduce cracking of the insulating layer and cracking of the ceramic substrate.
【００１４】[0014]
【実施例】以下、本発明をチップ抵抗器に適用したとき
の実施例を示し、本発明の特徴とするところをより詳細
に説明する。図１に示すように、本発明の実施例におけ
るチップ抵抗器は、例えば次のような構成を有するもの
である。即ち、アルミナ等からなるセラミック基板１
（約長さ５×幅２．５×厚さ０．５ｍｍ）と、該セラミ
ック基板１の上面の両端部に例えばＡｇ、Ａｇ／Ｐｄを
含有するメタルグレーズ系導電ペーストを印刷・乾燥・
焼成して設けられた一対の上面電極層２（層厚約０．０
１ｍｍ）と、上記セラミック基板１の下面の両端部に上
記メタルグレーズ系導電ペーストをもちいて設けられた
一対の下面電極層３（層厚約０．０１ｍｍ）と、上記一
対の上面電極層２に跨って抵抗ペーストを印刷・乾燥・
焼成して設けられた酸化ルテニウム系の抵抗体層４（層
厚約０．０２ｍｍ）と、該抵抗体層４上にガラスペース
トもしくは樹脂ペーストを印刷し、乾燥・焼成もしくは
熱硬化させて設けられた１層もしくは２層以上からなる
保護層５（層厚約０．０２ｍｍ）と、上記セラミック基
板１の両端面に上記上面電極層２と上記下面電極層３と
に接続するようにメタルグレーズ系導電ペーストもしく
は導電性樹脂ペーストを塗着し、乾燥・焼成もしくは熱
硬化して設けられた側面電極層６（層厚約０．０２ｍ
ｍ）と、上記上面電極層２、下面電極層３及び側面電極
層６の露出部上に設けられたニッケルメッキ層及び半田
メッキ層とからなるメッキ層７（層厚約０．０１ｍｍ）
と、上記一対の下面電極層間において上記セラミック基
板１の下面のセラミック表面上に、例えば硼硅酸系ガラ
ス等のガラスペースト、エポキシ樹脂等の熱硬化性樹脂
ペースト等の絶縁体ペーストを印刷等して塗着し、乾燥
・焼成もしくは熱硬化させて設けられた絶縁層８（層厚
約０．０２ｍｍ）と、から構成されている。EXAMPLES Examples of the present invention applied to a chip resistor will be shown below to explain the features of the present invention in more detail. As shown in FIG. 1, the chip resistor according to the embodiment of the present invention has, for example, the following configuration. That is, the ceramic substrate 1 made of alumina or the like
(About length 5 × width 2.5 × thickness 0.5 mm), and print / dry a metal glaze-based conductive paste containing, for example, Ag or Ag / Pd on both ends of the upper surface of the ceramic substrate 1.
A pair of upper electrode layers 2 (layer thickness of about 0.0
1 mm), a pair of lower surface electrode layers 3 (layer thickness of about 0.01 mm) provided by using the metal glaze-based conductive paste on both ends of the lower surface of the ceramic substrate 1, and a pair of upper surface electrode layers 2. Print / dry resistance paste across
A ruthenium oxide-based resistor layer 4 (layer thickness of about 0.02 mm) provided by firing, and a glass paste or a resin paste printed on the resistor layer 4 and dried / fired or heat-cured. Further, a protective layer 5 (layer thickness of about 0.02 mm) consisting of one layer or two or more layers, and a metal glaze system so as to be connected to the upper surface electrode layer 2 and the lower surface electrode layer 3 on both end surfaces of the ceramic substrate 1. The side surface electrode layer 6 (layer thickness of about 0.02 m, which is provided by applying a conductive paste or a conductive resin paste and drying / baking or thermosetting)
m) and a nickel plating layer and a solder plating layer provided on the exposed portions of the upper surface electrode layer 2, the lower surface electrode layer 3 and the side surface electrode layer 6 (layer thickness about 0.01 mm).
And printing an insulating paste such as a glass paste such as borosilicate glass or a thermosetting resin paste such as an epoxy resin on the ceramic surface of the lower surface of the ceramic substrate 1 between the pair of lower surface electrode layers. And an insulating layer 8 (having a layer thickness of about 0.02 mm) provided by being dried, fired, or thermally cured.
【００１５】上記チップ抵抗器において、絶縁層８は、
その熱膨張係数が上記セラミック基板１の熱膨張係数に
比して小さなものとされてもよいが、同一もしくはそれ
以上のものとされることにより、上記チップ抵抗器の抗
折強度をより一層向上することができる。また、上記実
施例においては、上記絶縁層８とセラミック基板１にお
ける下面両端部の電極層の厚みとを略同一としたが、絶
縁層８の厚みをセラミック基板における下面両端部の電
極層の厚みより薄くするか、或いは厚くして設けてもよ
く、特に上記絶縁層８の厚みを、チップ抵抗器を実装基
板等の基板上に設けられた配線層上に半田付けして実装
したときに上記下面の電極層と配線層との間に隙間が生
じるか、上記絶縁層と実装基板との間に隙間が無くなる
程度に厚くして設けたときは、上記下面両端部の電極層
間に半田が流れ込む等してショートが生じることを一層
軽減できるとともに、半田付け強度をも向上し得る。ま
た、このように上記絶縁層８をセラミック基板１の下面
両端部の電極層より厚くして突出したようにするとフェ
イスダウンボンディングをするときの吸着コレットによ
る保持をより確実に行うことができる。更に、上記絶縁
層８は、上記セラミック基板１の下面におけるセラミッ
ク表面の露出部全域に設けてもよいが、必ずしもこれに
限定されることなく、例えば必要な強度が得られる程
度、製造工程上の不都合がない程度等の範囲で適宜設け
ればよい。In the above chip resistor, the insulating layer 8 is
The coefficient of thermal expansion may be smaller than the coefficient of thermal expansion of the ceramic substrate 1, but the coefficient of thermal expansion is the same or higher, so that the bending resistance of the chip resistor is further improved. can do. Further, in the above embodiment, the thickness of the insulating layer 8 and the thickness of the electrode layers on both ends of the lower surface of the ceramic substrate 1 are substantially the same, but the thickness of the insulating layer 8 is the thickness of the electrode layers on both ends of the lower surface of the ceramic substrate. The insulating layer 8 may be made thinner or thicker. In particular, the thickness of the insulating layer 8 is set to the above value when the chip resistor is mounted by soldering on a wiring layer provided on a substrate such as a mounting substrate. If a gap is created between the lower electrode layer and the wiring layer, or if it is made thick enough to eliminate the gap between the insulating layer and the mounting substrate, the solder will flow between the electrode layers on both ends of the lower face. It is possible to further reduce the occurrence of short circuit due to the above, and to improve the soldering strength. Further, when the insulating layer 8 is made thicker than the electrode layers on both end portions of the lower surface of the ceramic substrate 1 so as to project, the holding by the suction collet at the time of face-down bonding can be performed more reliably. Further, the insulating layer 8 may be provided on the entire exposed portion of the ceramic surface on the lower surface of the ceramic substrate 1, but the present invention is not necessarily limited to this. It may be appropriately provided within a range such that there is no inconvenience.
【００１６】（抗折強度試験）上記実施例のチップ抵抗
器及び該チップ抵抗器において絶縁層８を設けなかった
チップ抵抗器（従来のチップ抵抗器）の各１２０個を資
料として、それぞれの破壊強度をＪＩＳ（日本工業規
格）Ｃ２１４１−７８、電気絶縁用セラミック材料試験
方法に記載の抗折強度の試験方法に準じて測定し、比較
した。(Bending strength test) Each of 120 chip resistors (conventional chip resistors) in which the insulating layer 8 is not provided in the chip resistor of the above-mentioned embodiment is used as a reference, and each is broken. The strength was measured according to JIS (Japanese Industrial Standard) C2141-78, the bending strength test method described in the Test method for ceramic material for electrical insulation, and compared.
【００１７】尚、上記資料としたチップ抵抗器におい
て、セラミック基板１としてはアルミナ含有率約９６％
のアルミナ基板（熱膨張係数約３×１０-7／Ｋ）を、保
護層５として硼硅酸鉛ガラスを、また上記実施例のチッ
プ抵抗器における絶縁層８として硼硅酸鉛ガラス（約長
さ３．７×幅２ｍｍ、熱膨張係数約３×１０-6／Ｋ）を
それぞれ用いた。In the chip resistor described above, the ceramic substrate 1 has an alumina content of about 96%.
Alumina substrate (coefficient of thermal expansion of about 3 × 10 −7 / K), lead borosilicate glass as the protective layer 5, and lead borosilicate glass (about long length) as the insulating layer 8 in the chip resistor of the above embodiment. 3.7 × width 2 mm, coefficient of thermal expansion of about 3 × 10 −6 / K).
【００１８】上記抗折試験の結果、従来のチップ抵抗器
の破壊強度の平均値が３．５２Ｋｇであったのに対して
実施例のチップ抵抗器の破壊強度の平均値が４．９６Ｋ
ｇであり、従来に比して実施例のチップ抵抗器の破壊強
度が約４０％向上したことがわかる。尚、上記実施例で
は、チップ抵抗器について示したが、本発明はこれに限
定されることなく、例えばチップネットワーク抵抗器、
厚膜ハイブリッドＩＣ等のセラミック基板の一方の面に
のみ電子素子を有する面実装タイプのチップ状電子部品
に広く適用できることは言うまでもない。As a result of the bending test, the average value of the breaking strength of the conventional chip resistor was 3.52 Kg, whereas the average value of the breaking strength of the chip resistor of the example was 4.96 K.
Since it is g, it can be seen that the breaking strength of the chip resistor of the example is improved by about 40% as compared with the conventional case. In the above embodiment, the chip resistor is shown, but the present invention is not limited to this. For example, a chip network resistor,
It is needless to say that the present invention can be widely applied to surface mount type chip-shaped electronic components having an electronic element only on one surface of a ceramic substrate such as a thick film hybrid IC.
【図１】本発明の実施例におけるチップ抵抗器の（ａ）
断面図及び（ｂ）下面図である。FIG. 1 (a) of a chip resistor according to an embodiment of the present invention.
It is sectional drawing and (b) bottom view.
【図２】従来のチップ抵抗器の断面図である。FIG. 2 is a sectional view of a conventional chip resistor.
【図３】チップ状電子部品を実装基板に実装する方法を
説明する概略断面図である。FIG. 3 is a schematic cross-sectional view illustrating a method of mounting a chip-shaped electronic component on a mounting board.
【図４】チップ状電子部品を実装基板に実装するとき
に、上記チップ状電子部品に割れが生じた状態を説明す
る概略断面図である。FIG. 4 is a schematic cross-sectional view illustrating a state where the chip-shaped electronic component is cracked when the chip-shaped electronic component is mounted on a mounting board.
１・・・・セラミック基板 ２・・・・上面電極層 ３・・・・下面電極層 ４・・・・抵抗体層 ５・・・・保護層 ６・・・・側面電極層 ８・・・・絶縁層 1 ... Ceramic substrate 2 ... Upper surface electrode layer 3 ... Lower surface electrode layer 4 ... Resistor layer 5 ... Protective layer 6 ... Side electrode layer 8 ...・ Insulation layer
Claims (4)
られ、上記セラミック基板の下面に直接的に絶縁層が設
けられていることを特徴とするチップ状電子部品。1. A chip-shaped electronic component, wherein an electronic element is provided on an upper surface of a ceramic substrate, and an insulating layer is directly provided on a lower surface of the ceramic substrate.
ク基板の上面、端面及び下面に亘って電極層が設けられ
ている請求項１に記載のチップ状電子部品。2. The chip-shaped electronic component according to claim 1, wherein electrode layers are provided on both ends of the ceramic substrate over the upper surface, the end surface and the lower surface of the ceramic substrate.
下面の電極層の厚みと同一もしくはそれ以上である請求
項２に記載のチップ状電子部品。3. The chip-shaped electronic component according to claim 2, wherein the thickness of the insulating layer is the same as or more than the thickness of the electrode layer on the lower surface of the ceramic substrate.
熱膨張係数よりも大きい請求項１〜３に記載のチップ状
電子部品。4. The chip-shaped electronic component according to claim 1, wherein the thermal expansion coefficient of the insulating layer is larger than the thermal expansion coefficient of the ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6201842A JPH0864401A (en) | 1994-08-26 | 1994-08-26 | Chip-like electronic part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6201842A JPH0864401A (en) | 1994-08-26 | 1994-08-26 | Chip-like electronic part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0864401A true JPH0864401A (en) | 1996-03-08 |
Family
ID=16447803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6201842A Pending JPH0864401A (en) | 1994-08-26 | 1994-08-26 | Chip-like electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0864401A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002075752A1 (en) * | 2001-03-16 | 2002-09-26 | Vishay Intertechnology, Inc. | Surface mounted resistor |
| WO2004090915A1 (en) * | 2003-04-08 | 2004-10-21 | Rohm Co. Ltd. | Chip resistor and method for manufacturing same |
| WO2004093101A1 (en) * | 2003-04-16 | 2004-10-28 | Rohm Co. Ltd. | Chip resistor and method for manufacturing same |
| WO2006022055A1 (en) * | 2004-08-26 | 2006-03-02 | Rohm Co., Ltd. | Chip type component and its manufacturing process |
| JP2010161135A (en) * | 2009-01-07 | 2010-07-22 | Rohm Co Ltd | Chip resistor, and method of making the same |
| JP2015061034A (en) * | 2013-09-20 | 2015-03-30 | コーア株式会社 | Chip resistor |
-
1994
- 1994-08-26 JP JP6201842A patent/JPH0864401A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002075752A1 (en) * | 2001-03-16 | 2002-09-26 | Vishay Intertechnology, Inc. | Surface mounted resistor |
| US6529115B2 (en) | 2001-03-16 | 2003-03-04 | Vishay Israel Ltd. | Surface mounted resistor |
| WO2004090915A1 (en) * | 2003-04-08 | 2004-10-21 | Rohm Co. Ltd. | Chip resistor and method for manufacturing same |
| WO2004093101A1 (en) * | 2003-04-16 | 2004-10-28 | Rohm Co. Ltd. | Chip resistor and method for manufacturing same |
| US7326999B2 (en) | 2003-04-16 | 2008-02-05 | Rohm Co., Ltd. | Chip resistor and method for manufacturing same |
| WO2006022055A1 (en) * | 2004-08-26 | 2006-03-02 | Rohm Co., Ltd. | Chip type component and its manufacturing process |
| US7629872B2 (en) | 2004-08-26 | 2009-12-08 | Rohm Co., Ltd. | Chip type component and its manufacturing process |
| JP2010161135A (en) * | 2009-01-07 | 2010-07-22 | Rohm Co Ltd | Chip resistor, and method of making the same |
| JP2015061034A (en) * | 2013-09-20 | 2015-03-30 | コーア株式会社 | Chip resistor |
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