JPH0854972A - Low power consumption bus device - Google Patents

Abstract

PURPOSE:To make power consumption low and to secure a stable operation even if power source voltage is low voltage by providing a data holding device holding the data that a device outputs on a bus for a specified period. CONSTITUTION:N bus driving circuits 1 outputting the outputs Dn of n devices by bus driving timing signals Tn are connected by sharing a bus B. On the bus B, a data holding device composed of a NAND circuit 9, an inverter 12 and an N channel transistor 13 is connected. This data holding device turns on the holding function for the data on the bus B for a period when any devices do not drive the bus B, holds 'H' when the data on the bus B is 'H', holds 'L' when the data is 'L' and turns off the holding function for a period when an arbitrary device drives the bus B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption bus device for controlling a bus of a microcomputer.

[0002]

2. Description of the Related Art Usually, in a configuration in which a bus is shared by n devices (apparatuses or elements), only one device n out of n devices transfers data in accordance with a specific bus drive timing Tn. Can be output on.

A conventional bus device for controlling a bus of a microcomputer will be described with reference to the drawings. FIG.
FIG. 3 is a circuit diagram of a bus device according to a precharge system, which is an example of a conventional bus device. In FIG. 4, n bus driving circuits 1 that output respective outputs Dn of n devices by respective bus driving timing signals Tn are connected to share a bus B. In addition, the bus B holds a P-channel transistor 3 for precharge whose gate input is a signal inverted from the precharge timing signal PT by the inverter circuit 2, and "H" data on the bus B to be simulated. In order to guarantee the static bus operation, an inverter circuit 4 and a high-level holding circuit HC including a P-channel transistor 5 are connected.

FIG. 5 shows an example of a bus drive circuit 1 corresponding to a conventional precharge type bus device. In FIG. 5, with respect to the bus B, the bus driving N-channel transistor 6 uses the output signal of the AND circuit 8 that AND-connects the signal obtained by inverting the device output Dn by the inverter circuit 7 and the bus driving timing signal Tn. Controlled.

The operation of the conventional bus device will be described below.
This will be described in detail with reference to the circuit diagrams of FIGS. 4 and 5 and the timing chart of FIG. Normally, the precharge timing signal PT of the bus B and the bus drive timing signal Tn of each bus drive circuit 1 are, as shown in FIG. 6, a period during which the bus B is precharged (“H” data output) and a bus drive. The bus drive timing signal Tn of the bus drive circuit 1 does not overlap with the discharge ("L" data output) period by the N channel transistor 6 for
Are input to the bus drive circuit 1 so that the periods in which the bus drive N-channel transistors 6 are in the ON state (“L” data output) are in an exclusive relationship and do not overlap.

First, while the precharge timing signal PT is "H", the P-channel transistor 3 is turned on and outputs "H" level onto the bus B. On the other hand, since each bus drive timing signal Tn is "L" and each bus drive N-channel transistor 6 is turned off, the data BD on the bus B becomes "H".

Further, the precharge timing signal PT
Is in the "L" state, the P-channel transistor 3 is in the off state and is in the high impedance state with respect to the bus B, but the output of data by each device connected to share the bus B is prohibited. In this case, the data BD on the bus B holds "H" by the high level holding circuit including the inverter circuit 4 and the P-channel transistor 5.

Next, during the period when the precharge timing signal PT is "L" and the only bus drive timing signal Tn is "H", the P-channel transistor 3 is in the off state, and the bus B is in the high impedance state. However, in each device which shares the bus B and is connected through the bus drive circuit 1, a case where only one bus drive circuit 1 attempts to output the output Dn of the device will be described.

When the output Dn of only one device is "H" while the bus drive timing signal Tn is "H", the gate input of the bus drive N-channel transistor 6 is made by the inverter circuit 7 and the AND circuit 8. It goes to "L" level. However, since the bus driving N-channel transistor 6 of the bus driving circuit 1 is of a high level driving type, it is turned off, and is held by the high level holding circuit HC composed of the inverter circuit 4 and the P channel transistor 5. The "H" level being output is output onto the bus B.

Further, when the output Dn of only one device is "L", the gate input of the bus driving N-channel transistor 6 becomes "H" level by the inverter circuit 7 and the AND circuit 8. Since the bus driving N-channel transistor 6 of the bus driving circuit 1 is of a high level driving type, it is turned on and outputs an “L” signal on the bus B.

At this time, the output signal of the inverter circuit 4 for the high-level holding circuit HC is inverted, and the P-channel transistor 5 and the P-channel transistor 5 are in a transient period until the P-channel transistor 5 is completely turned off. Timing TLn is generated in which both the low-level drive type bus driving N-channel transistor 6 is turned on.

[0012]

However, in the above-described conventional precharge type bus device, when the bus drive circuit 1 outputs the "L" signal onto the bus signal line, the high level holding circuit HC During the transitional period of inverting the “L” data that is the output of the inverter and turning off the high-level holding P-channel transistor 5 (pull-up transistor), a through current due to a data collision on the bus B is generated. However, there is a problem in that electric current is consumed due to this flow-through current.

Before each device drives the bus B, it is necessary to precharge the bus B without fail, and the current consumption during precharge driving increases according to the circuit scale.
There is a problem that the power consumption due to this current consumption cannot be ignored.

Further, as the circuit becomes larger in scale, it becomes very difficult to design parameters such as transistor size and timing, and the operating range of the device is narrowed depending on the parameters, resulting in lower voltage and lower power consumption. It also had a problem that it would be difficult to deal with.

The present invention solves the above-mentioned conventional problems, and when outputting a device signal to a bus by a bus drive circuit, there is no data collision on the bus as in the prior art. It is possible to eliminate the shoot-through current due to, and to eliminate the current consumption due to this precharge drive without the need for precharge drive, and to realize the low power consumption by avoiding the power consumption due to these currents. It is an object of the present invention to provide a low power consumption bus device capable of ensuring stable operation even when the power supply voltage is low.

[0016]

To achieve the above object, a low power consumption bus device of the present invention is a bus device for controlling a bus shared by a plurality of devices via a bus drive circuit. While the bus is not being driven, the retention function for the data on the bus is turned on,
If the data on the bus is "H", hold "H",
In the case of "L", the data holding device holds "L" and turns off the holding function while a certain device drives the bus.

[0017]

According to the above construction, when the bus drive circuit outputs the device signal to the bus, the data holding device eliminates the data collision on the bus by the complete static operation, and this data collision occurs. The through current that flows in some cases is avoided. In addition, when the device signal is output to the bus, the precharge drive performed each time this output is performed is eliminated.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A low power consumption bus device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a low power consumption bus device according to the data holding method of this embodiment. In FIG. 1, n bus drive circuits 1 that output outputs Dn of n devices according to a bus drive timing signal Tn are connected to share a bus B. On the bus B, a NAND circuit 9 and an inverter circuit are provided. A data holding device constituted by 10, an AND circuit 11, a P-channel transistor 12, and an N-channel transistor 13 is connected.

FIG. 2 shows an example of the bus drive circuit 1 corresponding to the bus control system of this embodiment. In FIG. 2, the tristate buffer 14 for driving the bus with respect to the bus B is a tristate bus driving circuit that controls the output Dn of the device by the bus driving timing signal Tn.

The operation of the low power consumption bus device of this embodiment will be described in detail below with reference to the circuit diagrams of FIGS. 1 and 2 and the timing chart of FIG. In the low power consumption bus device of the present embodiment, the bus hold timing signal HT and each bus drive timing signal Tn are signals generated by the P channel transistor 12 and the N channel transistor 13 which constitute the data holding device, as shown in FIG. There is an exclusive relationship between the output period and the output period of the signal Dn by each device, and further, the bus drive timing signal Tn of the bus drive circuit 1 does not overlap the periods output by the respective bus drive circuits 1. To each bus drive circuit 1.

First, while the bus hold timing signal HT is "L", the P-channel transistor 12 and the N-channel transistor 13 which are data holding devices are in the off state, and the data holding device does not operate. On the other hand, at the timing, a certain bus drive timing signal Tn is "H", only the tri-state buffer 14 of the only device connected to the bus B is turned on, and the output Dn of the device is on the bus B. Is output to. On this occasion,
The bus drive circuit 1 of the device is composed of a tri-state buffer, and outputs "H" on the bus B when the output Dn of the device is "H" and "L" when the output Dn is "L". To do.

Next, when the bus hold timing signal HT changes from "L" to "H", the comparison circuit formed by the NAND circuit 9, the inverter circuit 10 and the AND circuit 11 causes the immediately preceding bus B on the bus B. When the data BD is "H", the AND circuit 11 outputs "L" and the N-channel transistor 13 is turned off.
Since the D circuit 9 outputs "L" and the P-channel transistor 12 is turned on, the "H" level is held on the bus B while the bus hold timing signal HT is "H".

Similarly, when the data BD on the immediately preceding bus B is "L", the "L" level is held on the bus B while the bus hold timing signal HT is "L". By the above operation, when the device signal is output to the bus by the bus drive circuit, there is no data collision on the bus as in the conventional case, the through current due to the data collision can be eliminated, and the precharge can be performed. It is not necessary to drive, and the current consumption due to this precharge drive can be eliminated.

Therefore, it is possible to avoid power consumption due to these currents and realize low power consumption.
Stable operation can be ensured even when the power supply voltage is low.

[0026]

As described above, according to the present invention, when the signal of the device is output onto the bus by the bus drive circuit, the data holding device eliminates the data collision on the bus by the complete static operation. It is possible to avoid a through current that flows when this data collision occurs. Also,
When the device signal is output to the bus, it is possible to eliminate the precharge drive performed each time this output is performed.

Therefore, when the device signal is output to the bus by the bus drive circuit, there is no data collision on the bus as in the conventional case, the through current due to the data collision can be eliminated, and the precharge can be performed. It is not necessary to drive, and the current consumption due to this precharge drive can be eliminated. As a result, it is possible to avoid power consumption due to these currents and realize low power consumption.
Stable operation can be ensured even when the power supply voltage is low.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a low power consumption bus device according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a bus drive circuit of the same embodiment.

FIG. 3 is a timing chart according to the bus control method of the embodiment.

FIG. 4 is a circuit configuration diagram of a conventional bus device.

FIG. 5 is a circuit configuration diagram of a bus drive circuit of the conventional example.

FIG. 6 is a timing chart of the conventional bus control method.

[Explanation of symbols]

 1 Bus drive circuit 9 NAND circuit 10 Inverter circuit 11 AND circuit 12 P channel transistor 13 N channel transistor 14 Tri-state buffer B bus HT bus hold timing signal

Claims (3)

[Claims] 1. In a bus device for controlling a bus shared by a plurality of devices via a bus drive circuit, a specific period during which one device outputs data onto the bus,
A low power consumption bus including a data holding device that holds the data output to the bus by the one device during another specific period in which another device outputs the data to the bus apparatus. 2. A data holding device, wherein a holding function for data on the bus is turned on while no device is driving the bus, and when the data on the bus is "H", "H" is set. Hold, if "L", hold "L",
The low power consumption bus device according to claim 1, wherein the holding function is turned off during a period in which a certain device drives the bus. 3. The low power consumption bus device according to claim 1, wherein each device shares a bus via a bus drive circuit which is composed of a tri-state buffer and operates completely statically.