JPH0847252A - Switching regulator - Google Patents

Abstract

PURPOSE:To realize an IC of a switching regulator without employing external components by a method wherein a non-detecting circuit which does not detect an overcurrent during a period while a spike current is generated when a MOS- FET is in an ON-state is provided in the IC. CONSTITUTION:The ratios of the circumferential lengths of respective P-N-P transistors Tr22-Tr26 of which the current mirror circuit A of a non-detecting circuit is composed are as follows; Tr22:23:24:25:26-=0.5:1:0.5: 1:1. Constant currents corresponding to the ratios flow through the collectors of the respective transistors. As Tr20 is in an ON state and Tr21 and Tr27 are in OFF states when the level of a G. terminal is LOW, Tr28 is in an ON state and the level of VC1 is LOW. Further, Tr29 and Tr 30 are in OFF states and Tr31 is in an ON state and the level of the non-detecting circuit is LOW. When the level of the GA terminal is HIGH, Tr21 and Tr27 are in ON states and Tr20 and Tr28 are in OFF states and a capacitor C20 is charged with a constant current. When VC1 reaches a voltage equivalent to the two stages of VBE, Tr29 and Tr30 are turned ON and Tr31 is turned OFF and the non-detecting state is cancelled. As a result, the number of the terminals of an IC can be reduced and the size of the IC can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching regulator having an overcurrent protection circuit.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. 8 is a circuit diagram of a switching regulator according to a conventional example, FIG. 9 is an IC internal circuit diagram of FIG. 8, FIG. 10 is a time chart of each part of the circuit diagrams of FIGS. 8 and 9, and FIGS. 11A and 11B are diagrams. FIG. 8 is a diagram for explaining the operation of the CR circuit of FIG.

As shown in FIG. 8, a bridge diode BD1 is provided at the input stage of AC100V, and a capacitor C2 is provided between the output terminal of the bridge diode BD1 and GND.
00 is inserted, and in parallel with this, a resistor R connected in series
200 and Zener diode ZD200 are inserted. The connection point between the resistor R200 and the Zener diode ZD200 is connected to the VCC terminal of the IC1. Also,
Capacitor C2 in parallel with Zener diode ZD200
01 is connected.

One end of the primary side coil L1 of the transformer T1 is the output end of the bridge diode BD1 and the other end is M.
It is connected to the drain of OSFET1 (hereinafter abbreviated as MOS1). One end of the primary side coil L3 is connected to one side of the above-mentioned capacitor C201 via the diode D200, and the other end is connected to GND.

Further, between the F _B terminal of IC1 and GND,
A light receiving side (phototransistor) of a photocoupler PC1 described later is provided.

Both ends of the coil L2 on the secondary side of the transformer T1 are drawn out as output terminals, one end of which is through the diode D201. In addition, a capacitor C is placed between both terminals.
202 is inserted.

Further, a resistor R20 is connected in parallel between the output terminals.
1, 202 are connected, and the light emitting side (light emitting diode) of the photocoupler PC1 is connected in parallel to the resistor R201. The connection point of the resistors 201 and 202 is input to the shunt regulator SR1.

The gate G of the MOS1 has a resistor R20.
3 is connected to the input terminal G _A of the IC1 for overcurrent protection operation. A detection resistor R _S is inserted between the source S of the MOS1 and the GND. For the detection resistor R _S ,
Series connected resistors R204, a capacitor C203 is connected in parallel, a connection point between the resistor R204 and the capacitor C203 is connected to an input terminal O _C of IC1. This resistor R204 and the capacitor C203 make it
It constitutes the R circuit A.

_A capacitor C204 is provided between the input terminal C _{A of} IC1 and GND.

Next, the internal circuit of the IC1 will be described with reference to FIG. The same functional portions as those in FIG. 8 are designated by the same symbols. In FIG. 9, the input terminal O _C is a comparator C
It is connected to the-terminal of OM10. On the other hand, the power supply V _P1 is connected to the + terminal. The output of the comparator COM10 is input to the bar S of the RS flip-flop F1.

Further, the input terminals C _A and F _B of the IC1 are respectively connected to the two + terminals of the other comparator COM20, and between the − terminal of the comparator COM20 and the bar R of the RS flip-flop F1. Oscillator OSC1
Is provided. Then, the output of the comparator COM20 and the output from the bar Q of the RS flip-flop F1 are input to the AND circuit AC1. AND circuit A
The output of C1 is commonly connected to the bases of Tr1, Tr2 and Tr3, Tr4 connected in Darlington.

A constant voltage circuit RC1 is connected to the VCC terminal, and the constant voltage circuit RC1 is connected to the collector of the transistor Tr1.

The operation of the switching power supply circuit shown in FIGS. 8 and 9 will be described below. This switching power supply circuit is of the PWM type and keeps the output voltage constant by adjusting the duty.

First, the coil L3, the diode D200,
The capacitor C201 is for supplying a rectified and smoothed stable voltage to the V _CC terminal of the IC 1 after the SW power supply is activated. Then, when the V _CC voltage is supplied, the IC1 operates and the switching operation of the MOS1 starts. Then, the electric power is transmitted to the secondary side through the transformer T1.

On the secondary side, rectification and smoothing are performed by the diode D201 and the capacitor 202, and the output voltage V _O is output. A shunt regulator SR1 that monitors the output voltage V _O is provided on the secondary side, and feedback is performed as described below.

The output voltage V _O is divided by the resistors R201 and 202 and input to the shunt regulator SR1. This voltage is about 2.5 for the shunt regulator SR1.
When it is higher than V, I _K becomes large and the amount of light on the light emitting side (light emitting diode) of the photocoupler PC1 becomes large. When the light amount becomes large, I _C becomes large on the light receiving side (phototransistor) of the photocoupler PC1, and the F _B terminal voltage (V _FB ) becomes more LO.
W, and the switching duty of the MOS1 becomes small. Then, the amount of electric power transmitted to the secondary side decreases, and the output voltage V _O also decreases.

On the other hand, when the output voltage V _O drops and the Vref terminal of the shunt regulator SR1 drops below 2.5 V, the operation opposite to the above occurs.

Vref decrease → I _K small → PC1 light amount small →
I _C small → V _FB UP → MOS duty large → transfer power amount large → output voltage V _O large.

As described above, the control feedback is performed so that the Vref terminal becomes 2.5V. Therefore, the output voltage V _O is V _O = ((R1 + R2) / R2) × 2.5V
Becomes

Next, the overcurrent protection operation in the above circuit will be described below.

The drain current I _D input to the drain side of the MOS1 is converted into a voltage V _RS by the detection resistor R _S , this voltage V _RS is input to the input terminal O _{C of the} IC1, and the comparator COM10 preliminarily sets the overcurrent. It is compared with a constant voltage VP1 set to detect the current. Here, VP1 =
It is set to 0.25V. If V _RS exceeds VP1, the output of the comparator COM10 becomes LOW, the bar S of the RS flip-flop F1 is set, and the bar Q becomes LO.
W. As a result, the output point A ₁ of the AND circuit is LOW.
Becomes When A ₁ becomes LOW, Tr3 and Tr4 turn on
Then, the output G _A terminal becomes LOW, the MOS1 becomes OFF, and the drain current I _D also stops.

The relationship of the above output signals is shown in the time chart of FIG. By the way, as is clear from the time chart of FIG. 10, when the MOS1 is turned on, a spike current as shown by S in FIG. There is. If a spike current occurs, it may be determined that an overcurrent is flowing, and the system may shut down, resulting in a malfunction. Conventionally, in order to prevent this, a CR circuit A is provided as shown in FIG.

The operation of preventing the spike current by the CR circuit A will be described in more detail with reference to FIG. First,
FIG. 11A is a current waveform diagram when a spike current is generated. Now, assuming that the overcurrent detection level is 2.5 A, even if the original overcurrent detection point is point P, if a spike current occurs as described above, point Q at the time of occurrence is regarded as an overcurrent occurrence. Judgment is made and malfunction occurs. On the other hand, by providing the CR circuit A, the spike current can be blunted as shown in FIG. 11B, and malfunction has been prevented.

[0024]

The capacitance of the capacitor C203 of the CR circuit A is, for example, 68.
A large capacity such as 00 pF was required, and it was impossible to incorporate it in the IC, so it had to be externally attached to the IC.

The resistance value of the detection resistor R _S is, for example, 0.
It was about 1Ω, and the maximum current sometimes flowed at 4 to 5 A. In this respect, on can not be reduced form the resistance in the IC is about 0.1 [Omega, even if provided with a small resistance, there is a possibility that IC itself may be damaged by a large current, conventionally, the detection resistor R _S It could not be provided in the IC.

As described above, in the MOS control circuit, the spike current preventing capacitor and the overcurrent detecting resistor must be externally attached, and all circuits cannot be integrated. As a result, in one packaged IC, there is a problem that it is necessary to additionally provide terminals for external parts and the package size becomes large.

The detection resistor R _{S is connected} to the source S of the MOS1.
Since the overcurrent was detected by connecting in series with the above, there was a problem that the loss in the resistance portion was large when the MOS1 was ON. For example, when the overcurrent is limited when the drain current I _D = 2.5 A is set as the threshold level, R _S · I _D ² = 0.1Ω × 2.5A × 2.5A =
There is a loss of 0.625W. Further, even in the normal operation, if the drain current I _D = 1A, then R _S · I _D ² = 0.1
There is a loss of Ω × 1A × 1A = 0.1W.

Therefore, an object of the present invention is that the control circuit for preventing overcurrent can be integrated into an IC without using external parts, the number of IC package terminals can be reduced, and the size can be reduced.
Moreover, it is to provide a highly efficient switching regulator with less loss in the overcurrent detection resistor.

[0029]

In order to achieve the above-mentioned object, a switching regulator of the present invention comprises an output interrupting MOSFET provided on the primary side of a transformer and a constant voltage provided on the secondary side of the transformer. The MOSFET is turned on and off according to the magnitude of the constant voltage obtained by the circuit, and the MOS is detected when an overcurrent on the primary side of the transformer is detected.
In a switching regulator having an IC that cuts off the FET, a MOSFET with a sense terminal is used as the MOSFET, an overcurrent detection resistor for detecting a current of the sense terminal is provided in the IC, and A feature is that a non-detection circuit that does not detect an overcurrent is provided during a generation time of a spike current generated when the MOSFET is turned on.

Further, the IC is characterized in that a comparator for converting the current of the sense terminal into a voltage and comparing the converted voltage with a threshold voltage to detect an overcurrent is provided.

Further, the comparator has a current mirror circuit composed of a pair of transistors having a common base, and an overcurrent detection resistor and a threshold voltage generation resistor are connected to each transistor of the current mirror circuit. The sense terminal is connected between the overcurrent detection resistor and the transistor.

[0032]

As described above, in the present invention, the MOSFET with the sense terminal is used. The current flowing through the sense terminal is a small current having a constant ratio to the drain current, and the resistor for detecting the current at the sense terminal can be provided in the IC. That is, it is possible to provide the overcurrent detection resistor, which has conventionally been externally attached to the IC, inside the IC.

Further, since the non-detection circuit that does not detect the overcurrent is provided in the IC during the generation time of the spike current generated when the MOSFET is turned on, CR is conventionally provided to prevent the influence of the spike current. The circuit becomes unnecessary, and the large-capacity capacitor externally attached to the IC becomes unnecessary. In this way, since there are no external parts attached to the IC, the number of terminals of the IC is reduced, and the switching regulator using this IC can be downsized.

Further, in the IC, a comparator is provided for converting the current of the sense terminal into a voltage and comparing the converted voltage with a threshold voltage to detect an overcurrent. The comparator is a pair of transistors whose bases are common. The threshold voltage can be set to a small value of 0.1 v since the current mirror circuit is composed of.

As described above, by reducing the threshold voltage, 1 / th of the sense current of the MOS with sense terminal is obtained.
The accuracy of the ratio of 890 (one example) can be stably maintained.
If the threshold voltage is large, the accuracy of the ratio is deviated and the stability is deteriorated.

Further, the loss in the overcurrent detection resistor can be made very small as compared with the conventional one because the current flowing through this resistor can be made small.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A great feature of the present invention is that an MO with a sense terminal is provided.
By using SFET, the overcurrent detection resistor can
In the present invention, the CR circuit is used to absorb the spike current and absorb the spike current in the related art. However, the present invention does not use the CR circuit and provides a non-detection circuit that does not detect the current during the spike current generation period. The point is that the capacitor is unnecessary and external parts for the IC are eliminated.

Furthermore, a stable overcurrent detection accuracy is realized by forming the input stage of the control circuit for preventing overcurrent into a current mirror circuit configuration.

Hereinafter, a detailed description will be given with reference to the drawings.

FIG. 1 is a circuit diagram of a switching regulator according to an embodiment of the present invention, FIG. 2 is an IC internal circuit diagram of FIG. 1, FIG. 3 is a circuit diagram of a comparator COM1 in the IC of FIG. 2, and FIG. Schematic of the constant current circuit I ₁ in the IC of
5 is a circuit diagram using a trimming resistor in the circuit of FIG. 4, FIG. 6 is a time chart of the circuit diagrams of FIGS. 1 and 2, and FIG. 7 is a circuit diagram of the non-detection circuit in FIG.

Here, differences from the conventional example shown in FIGS. 8 and 9 will be mainly described. The same symbols are attached to the same functional parts.

[0042] As shown in FIG. 1, the switching regulator of this embodiment sense terminal with MOSFET1 using (hereinafter, the sense MOS1 abbreviated with terminal), the sense terminal S1 is connected to the O _C terminal of IC1 There is.

The MOS with a sense terminal is a MOS having a terminal through which a small current having a constant ratio to the drain current flows.

The inside of IC1 is as shown in FIG.
Two AND circuits AC2 and AC3 are used in comparison with the conventional example shown in FIG.
The difference is that a non-detection circuit DC1 is added.

Further, as shown in FIG. 3, the comparator COM1 of the IC1 has a current mirror circuit (Tr1
1, 12, R1, 2). That is, the transistors Tr11 and T whose bases are commonly connected
A detection resistor R1 and a resistor R2 are inserted between each emitter of r12 and GND. Transistor Tr
The base and collector of 12 are short-circuited. Further, the emitter of the transistor Tr11 is connected to O _C terminal of IC1, also, between the emitter and the power supply VS of the transistor Tr12 is connected to a constant current source I _1. The collectors of the transistors Tr11 and Tr12 are Tr1 of the transistors Tr13, 14, and 15 whose bases are commonly connected.
It is connected to the collectors of 4 and 15, respectively.

Further, the transistors Tr13, 14, 15
Each emitter of is connected to the power supply VS. The base and collector of the transistor Tr13 are short-circuited, and the constant current source I ₂ is inserted between this collector and GND. The connection point between the transistors Tr11 and Tr14 is connected to the base of the transistor Tr16,
The emitter of r16 is connected to GND, and the comparator output is taken out from the collector.

The detection resistor R1 is formed in the IC by an emitter diffusion resistor (sheet resistance = 6Ω / □).

In the circuit structure as described above, the MOS 1 with a sense terminal shown in FIG. 1 has the terminal S ₁ for sensing the drain current as described above. A current of 890 flows. Therefore, when I _D = 2.5 A, I _S ≈2.8 mA.
Further, as shown in FIG. 3, the comparator COM1 has a current mirror circuit at the input stage, and the threshold voltage (point of P1) is R2 × (20 μA + 80 μ
A) = 0.1v.

Therefore, the loss at the detection resistor R1 in FIG. 3 is 0.1 v × 2.8 mA = 0.28 mA. This value can be made extremely smaller than the loss of 0.625 mW in the detection resistor in the conventional example shown in FIGS. here,
The threshold level is reduced to 0.1v in order to reduce the loss and to maintain the accuracy of the ratio of 1/890 of the sense current. If the threshold level is increased, the accuracy of the ratio will shift and the stability will deteriorate.

Next, the operation of the comparator COM1 will be described with reference to FIG. Normally, P1 point is 0.1v, P
The two points are 35Ω × (1A / 890) = 3 when I _D = 1A
9mA, Tr11 is ON, Tr16 is OF
Therefore, the output of the comparator COM1 is HIGH.

However, at the time of overcurrent, I _S is 2.8 m.
When the voltage exceeds A, the voltage at point P2 exceeds 0.1v, so Tr
No. 11 cannot draw all the current of 20 μA and Tr16 turns on. Then, the output of the comparator is L
It becomes OW and outputs a detection signal.

By the way, in this embodiment, the detection resistor R
1 (= 36Ω) uses the emitter diffusion resistance as described above. On the other hand, since R2 is 1 kΩ, a base diffusion resistance of 220 Ω / □ is normally used due to the chip space problem, whereas the temperature coefficient of the emitter diffusion resistance of R1 is about 2000 ppM / ° C. The base diffusion resistance is about 2800 ppM / ° C., and the temperature characteristic of the detection threshold level deteriorates. Therefore, in order to correct this difference in temperature coefficient, the constant current circuit I1 has a circuit configuration as shown in FIG.

That is, the base of the transistor Tr100 has resistors R103 and R1 provided between the power source VS and GND.
It is connected to the voltage dividing point of 04, and a resistor 10 is connected between the emitter and GND.
5 is inserted. The collector of the transistor Tr100 has a base commonly connected to the transistor Tr10.
It is connected to the collectors of the transistors Tr102 of Nos. 1 and 102. The base and emitter of the transistor Tr102 are short-circuited. The constant current I ₁ is the transistor Tr10.
3 collectors.

In the above circuit configuration, the constant current I ₁ is represented by the following equation.

I ₁ = V _A −V _BE1 / R ₁₀₅ (1) Here, V _BE1 = 0.65 v at Tj = 25 ° C. In the formula (1), R ₁₀₅ is a base diffusion resistance of about 280.
It has a temperature coefficient of 0 ppM / ° C. On the other hand, the molecule is V
-Because of the temperature characteristic of _BE1 -2mV / ° C, -2m
It has a temperature coefficient of V / ( _VA - _VBE1 ). Therefore,
The numerator can change the temperature coefficient depending on the value of V _A. This V _A
Is an internal constant voltage V _S (= 4 v) with a small temperature fluctuation divided by R ₁₀₃ and R ₁₀₄ , and adjustment can be easily performed.

In this embodiment, as described above, the difference between the base diffusion resistance and the emitter diffusion resistance is 2800 ppM-2.
Since a correction of 000 ppM = 800 ppM is required, the temperature characteristic of I ₁ needs to be about −800 ppM / ° C., and V _A = 1.65 v and R ₁₀₅ = 12.5 kΩ.

Further, in order to further improve the accuracy of the overcurrent detection level, the circuit configuration as shown in FIG. 5 may be adopted. According to the circuit configuration of FIG. 5, the resistor R can be zener zapped, so that the resistance value of R ₁₀₅ can be set to an arbitrary value, and I ₁
Can be adjusted, and the threshold level V _P1 of the P1 point comparator in FIG. 3 can be adjusted. (V _P1 = R ₁₀₂
× (I ₁ +20 μA)) Next, the circuit configuration of the present embodiment for preventing malfunction due to spike current will be described. The feature of the present embodiment is that a malfunction is avoided by not using a CR circuit as in the prior art and providing a non-detection circuit that does not detect a current during a spike current generation period. Specifically, as shown in the time chart of FIG. 6, the output of the non-detection circuit is set to LO for about 230 nsec even after the G _A terminal becomes HIGH.
W is maintained, during this period, overcurrent detection is not detected, and even if a spike current occurs, it is completely ignored by ignoring it.

FIG. 7 shows a circuit diagram of the non-detection circuit.

In FIG. 7, A is a level shift circuit for an input signal input from the G _A terminal, B is a current mirror circuit, and C is a constant current source.

In the level shift circuit A, the collector of the transistor Tr20 whose signal is input to the base is GN.
In D, the emitter is the base of the transistor Tr21, and the transistor Tr2 forming the current mirror circuit B.
It is connected to the collectors of the transistors Tr22 of 2, 23, 24, 25, and 26. Diodes D21 and D22 and a resistor R20 are interposed between the emitter of the transistor Tr21 and GND, and a resistor R2 is interposed between the collector and the power supply V _SS.
1 is inserted.

The connection point between the diode D22 and the resistor R20 is connected to the base of the transistor Tr27, the emitter of the Tr27 is GND, and the collector is the transistor Tr23.
Connected to the collector. The collector of Tr27 is connected to the base of Tr28, the emitter of Tr28 is GND, and the collector of Tr24 is the collector of Tr24 and Tr2.
It is connected to 9 bases. Tr28 collector-G
A capacitor C20 is inserted between ND. Tr2
A resistor R22 is inserted between the collector of 9 and the power supply V _SS .

The emitter of Tr29 is connected to the base of Tr30, the emitter of Tr30 is GND, and the collector is T.
It is connected to the base of r31 and the collector of Tr26. The emitter of Tr31 is connected to GND, and the collector is drawn out as the output terminal of the non-detection circuit DC1. The input of the non-detection circuit is connected to the G _A terminal connected to the gate terminal of MOS1.

In the above circuit configuration, the emitter perimeter length ratio of each PNP transistor forming the current mirror circuit A is Tr22: 23: 24: 25: 26 =
The ratio is 0.5: 1: 0.5: 1: 1, and a constant current corresponding to this ratio flows out from each collector.

The value of the constant current I _O of the constant current source C is calculated as follows.

I _O = (4V-0.65V × 3) / 20K
Ω = 102.5 μA≈100 μA The operation will be described below. When G _A terminal is LOW (when MOS1 is OFF), Tr20 is ON, Tr21
Is OFF and T27 is OFF, so Tr28
Is ON and V _C1 is LOW. And Tr29
Is OFF, Tr30 is OFF, Tr31 is ON, and the non-detection circuit is LOW (non-detection state).

Next, when the G _A terminal becomes HIGH, T
r20 is OFF, Tr21, Tr27 is ON, Tr28
Is turned off, and the capacitor C20 is charged with a constant current of 50 μA. Here, the capacitor C20 is for obtaining the delay time. Then, when V _C1 reaches a voltage of about 1.3 V for two stages of V _BE , Tr29 and Tr30 are turned on.
Then, Tr31 is turned off and the non-detection state is released.

Time t when the capacitor C20 is charged
= 5 pF × 1.3 v / 50 μA = 130 ns, Tr2
Approximately 100n of switching time of 0, 21, 27-31
230 ns, which is the sum of s, is the delay time from when the G _A terminal becomes HIGH to when Tr31 becomes OFF,
This is the non-detection time.

Here, the capacitance of the capacitor C20 is 5 pF.
Since it is only about the level, it can be incorporated in the IC and does not need to be externally attached as in the conventional case. That is, the capacitor C
20 and the overcurrent detection resistor R1 described with reference to FIG.
Any of them can be installed in the IC, and I
C can be achieved.

As described above in detail, in the present embodiment, by using the MOS with the sense terminal, the overcurrent detection resistor which is conventionally externally attached to the IC is integrated into the IC.
It can be provided inside. Further, since the non-detection circuit that does not detect the overcurrent during the generation time of the spike current generated when the MOS is turned on is provided in the IC, the CR circuit that has been conventionally provided to prevent the influence of the spike current is unnecessary. Therefore, the large-capacity capacitor externally attached to the IC is unnecessary.

As described above, since the parts externally attached to the IC are eliminated, the number of terminals of the IC is reduced and the switching regulator using this IC can be miniaturized.

Further, in the IC, a comparator for converting the current of the sense terminal into a voltage and comparing the converted voltage with a threshold voltage to detect an overcurrent is provided, and the comparator is a pair of transistors whose bases are common. The threshold voltage can be set to a small value of 0.1 v since the current mirror circuit is composed of.

By thus reducing the threshold voltage, the accuracy of the ratio of 1/890 of the sense current can be stably maintained.

Further, the loss in the overcurrent detection resistor can be made extremely smaller than the conventional one because the current flowing in this detection resistor can be made small, and the efficiency can be improved.

[0074]

As described above, according to the present invention,
Since there are no external parts attached to the IC, the number of terminals of the IC can be reduced, and the switching regulator using this IC can be downsized and the cost can be reduced.

Further, by using the MOSFET with the sense terminal, the current flowing through the overcurrent detection resistance portion can be reduced, so that the loss in this resistance portion can be reduced and a more highly efficient switching regulator can be realized.

Further, a current mirror circuit can be provided in the overcurrent detection IC to stabilize the detection operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a switching regulator according to an embodiment of the present invention.

2 is an internal circuit diagram of the IC of FIG.

FIG. 3 is a circuit diagram of a comparator inside the IC of FIG.

4 is a circuit diagram of a constant current circuit inside the IC of FIG.

5 is a circuit diagram in which resistance trimming is used in the circuit of FIG.

FIG. 6 is a time chart of each part of the circuit diagrams of FIGS. 1 and 2.

FIG. 7 is a circuit diagram of a non-detection circuit inside the IC of FIG.

FIG. 8 is a circuit diagram of a switching regulator according to a conventional example.

9 is an internal circuit diagram of the IC of FIG.

FIG. 10 is a time chart of each part of the circuit diagrams of FIGS. 8 and 9;

11A and 11B are views for explaining the operation of the CR circuit of FIG.

[Explanation of symbols]

T ₁ trans RC1 constant voltage circuit DC1 undetected circuit COM1 comparator R1 overcurrent detecting resistor R2 threshold voltage generating resistor

Claims (3)

[Claims] 1. A MOSFET for output connection / disconnection provided on the primary side of a transformer, and the MOS according to the magnitude of a constant voltage obtained by a constant voltage circuit provided on the secondary side of the transformer.
In a switching regulator having an intermittent FET and an IC that shuts off the MOSFET when an overcurrent on the primary side of the transformer is detected, a MOSFET with a sense terminal is used as the MOSFET, and an overcurrent for detecting the current at the sense terminal is used. A current detection resistor is provided in the IC, and the MOSF is provided in the IC.
During the generation time of spike current generated when ET is ON,
A switching regulator comprising a non-detection circuit that does not detect overcurrent. 2. The switching regulator according to claim 1, wherein the IC is provided with a comparator that converts the current of the sense terminal into a voltage and compares the converted voltage with a threshold voltage to detect an overcurrent. A switching regulator characterized in that 3. The switching regulator according to claim 2, wherein the comparator includes a current mirror circuit including a pair of transistors having a common base, and each transistor of the current mirror circuit detects an overcurrent. And a threshold voltage generating resistor are connected, and the sense terminal is connected between the overcurrent detecting resistor and the transistor.