JP3140915B2 - Switching regulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching regulator having an overcurrent protection circuit.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. 8 is a circuit diagram of a conventional switching regulator, FIG. 9 is an IC internal circuit diagram of FIG. 8, FIG. 10 is a time chart of each part of the circuit diagrams of FIGS. 8 and 9, and FIGS. 11 (a) and (b) are diagrams. 8 is a diagram for explaining the operation of the CR circuit 8; FIG.

As shown in FIG. 8, a bridge diode BD1 is provided at an input stage of AC100V, and a capacitor C2 is provided between an output terminal of the bridge diode BD1 and GND.
00, and a resistor R connected in series
200 and a Zener diode ZD200 are interposed. The connection point between the resistor R200 and the Zener diode ZD200 is connected to the VCC terminal of IC1. Also,
Capacitor C2 in parallel with Zener diode ZD200
01 is connected.

One end of a coil L1 on the primary side of the transformer T1 is connected to the output terminal of the bridge diode BD1, and the other end is connected to M
It is connected to the drain of OSFET1 (hereinafter abbreviated as MOS1). One end of the coil L3 on the primary side is connected to one side of the capacitor C201 via a diode D200, and the other end is connected to GND.

[0005] Between the F _B terminal and the GND of IC1,
A light receiving side (phototransistor) of a photocoupler PC1 described later is provided.

[0006] Both ends of the coil L2 on the secondary side of the transformer T1 are drawn out as output terminals at one end via a diode D201. A capacitor C is connected between both terminals.
202 is inserted.

Further, a resistor R20 is connected in parallel between the output terminals.
1 and 202 are connected, and the light emitting side (light emitting diode) of the photocoupler PC1 is connected in parallel with the resistor R201. The connection point between the resistors 201 and 202 is input to the shunt regulator SR1.

The gate G of the MOS1 is connected to a resistor R20.
3 through is connected to the input terminal G _A of IC1 for overcurrent protection operation. Further, a detection resistor R _S is interposed between the source S of the MOS 1 and GND. The detection resistor R _S
Series connected resistors R204, a capacitor C203 is connected in parallel, a connection point between the resistor R204 and the capacitor C203 is connected to an input terminal O _C of IC1. The resistance R204 and the capacitor C203 allow the C
An R circuit A is configured.

_A capacitor C204 is provided between the input terminal CA of IC1 and GND.

Next, the internal circuit of the IC 1 will be described with reference to FIG. The same parts as those in FIG. 8 are denoted by the same reference numerals. 9, an input terminal O _C comparators C
It is connected to the-terminal of OM10. On the other hand, the power supply _VP1 is connected to the + terminal. The output of the comparator COM10 is input to the bar S of the RS flip-flop F1.

Further, the two positive terminal of the other comparator COM20, input terminal C _A of IC1, F _B are respectively connected, the comparator COM20 - between the bars R terminal and the RS flip-flop F1 is Oscillator OSC1
Is provided. Then, the output of the comparator COM20 and the output from the bar Q of the RS flip-flop F1 are input to the AND circuit AC1. AND circuit A
The output of C1 is commonly connected to the bases of Tr1, Tr2 and Tr3, Tr4 connected in Darlington.

A constant voltage circuit RC1 is connected to the VCC terminal, and the constant voltage circuit RC1 is connected to the collector of the transistor Tr1.

The operation of the switching power supply circuit shown in FIGS. 8 and 9 will be described below. This switching power supply circuit is of a PWM type, and maintains a constant output voltage by adjusting the duty.

First, a coil L3, a diode D200,
Capacitor C201 after SW power-up, rectifier, is for supplying a smoothed stabilized voltage to the V _CC terminal of IC1. When the V _CC voltage is supplied, IC1 operates and the switching operation of MOS1 starts. Then, electric power is transmitted to the secondary side through the transformer T1.

On the secondary side, rectification and smoothing are performed by a diode D201 and a capacitor 202, and an output voltage V _O is output. A shunt regulator SR1 for monitoring the output voltage V _O is provided on the secondary side, and performs feedback as described below.

The output voltage V _O is divided by the resistors R201 and R202 and is input to the shunt regulator SR1. This voltage is about 2.5 shunt regulator SR1.
If it is higher than V, I _K becomes large, and the light quantity on the light emitting side (light emitting diode) of the photocoupler PC1 becomes large. When the light quantity is large light-receiving side of the photocoupler PC1 (phototransistor) is I _C becomes large, F _B terminal voltage (V _FB) is more LO
W, and the switching duty of the MOS1 decreases. Then, the amount of power transmitted to the secondary side decreases, and the output voltage V _O also decreases.

On the other hand, when the output voltage V _O drops and the Vref terminal of the shunt regulator SR1 drops below 2.5V, the reverse operation occurs.

[0018] Vref decrease → I _K Small → PC1 of the amount of light is small →
The I _C Small → V _FB UP → MOS duty large → transmission power amount large → the output voltage V _O Univ.

As described above, the control feedback is performed so that the Vref terminal becomes 2.5V. Therefore, the output voltage V _O is V _O = ((R1 + R2) / R2) × 2.5V
Becomes

Next, the overcurrent protection operation in the above circuit will be described below.

[0021] MOS1 drain current I _D to be input to the drain side of the is converted into a voltage V _RS sense resistor R _S, the voltage V _RS is input to the input terminal O _C of IC1, in a comparator COM10, advance over The current is compared with a set constant voltage VP1 for detecting the current. Here, VP1 =
0.25V. If the output becomes LOW comparator COM10 when V _RS exceeds VP1, sets the bar S of the RS flip-flop F1, the bar Q is LO
W. As a result, the output point A ₁ of the AND circuit is LOW
Becomes When A ₁ is LOW, Tr3, Tr4 are ON
Outputs G _A terminal becomes LOW, MOS1 stops also turned OFF drain current I _D.

The relationship between the above output signals is shown in the time chart of FIG. By the way, as is clear from the time chart of FIG. 10, when the MOS1 is ON, a spike current as shown by S in FIG. 10 is generated due to a stray capacitance at the drain terminal due to factors such as a coil of the transformer and wiring. There is. When a spike current occurs, a malfunction may occur in which the system is determined to be overcurrent and shut off. Conventionally, in order to prevent this, a CR circuit A is provided as shown in FIG.

The operation of the spike current prevention by the CR circuit A will be described in more detail with reference to FIG. First,
FIG. 11A is a current waveform diagram when a spike current is generated. Now, assuming that the overcurrent detection level is 2.5 A, if the spike current occurs as described above, despite the fact that the original overcurrent detection point is at point P, the point Q at that occurrence is regarded as overcurrent occurrence. Judgment results in malfunction. On the other hand, by providing the CR circuit A, the spike current can be blunted as shown in FIG. 11B, thereby preventing a malfunction.

[0024]

The capacity of the capacitor C203 of the CR circuit A is, for example, 68
A large capacity such as 00 pF was required, and it was not possible to take in the IC, and it had to be externally attached to the IC.

The resistance value of the detection resistor R _S is, for example, 0.5.
It was about 1Ω, and the current sometimes flowed at a maximum of 4 to 5 A. In this respect, on can not be reduced form the resistance in the IC is about 0.1 [Omega, even if provided with a small resistance, there is a possibility that IC itself may be damaged by a large current, conventionally, the detection resistor R _S It could not be provided in an IC.

As described above, in the MOS control circuit, a capacitor for preventing a spike current and an overcurrent detection resistor must be externally provided, and all circuits cannot be integrated. As a result, the IC packaged in one package requires extra terminals for external components, and has a problem that the package size becomes large.

The detection resistor R _{S is connected} to the source S of the MOS 1.
And the overcurrent is detected in series, there is a problem that when the MOS1 is ON, the loss in this resistance portion is large. For example, at the time of overcurrent when the drain current I _D = 2.5 A is set as the threshold level and the overcurrent is limited, R _S · I _D ² = 0.1Ω × 2.5 A × 2.5 A =
There is a loss of 0.625W. Also, assuming that the drain current I _D = 1 A even in the normal operation, R _S · I _D ² = 0.1
There is a loss of Ω × 1A × 1A = 0.1 W.

An object of the present invention is to provide a control circuit for preventing overcurrent, all of which can be made into an IC without using external components, thereby reducing the number of package terminals of the IC and achieving downsizing.
In addition, it is an object of the present invention to provide a high-efficiency switching regulator with less loss in the overcurrent detection resistor.

[0029]

In order to achieve the above object, a switching regulator according to the present invention comprises an output interrupting MOSFET provided on a primary side of a transformer and a constant voltage MOSFET provided on a secondary side of the transformer. The MOSFET is turned on and off in accordance with the magnitude of the constant voltage obtained by the circuit, and the MOS is turned on when an overcurrent is detected on the primary side of the transformer.
A switching regulator having an IC for shutting off an FET, using a MOSFET with a sense terminal as the MOSFET, providing an overcurrent detection resistor for detecting the current of the sense terminal in the IC, and A non-detection circuit that does not perform overcurrent detection is provided during a spike current generation time that occurs when the MOSFET is turned on, and includes a pair of transistors having a common base.
A current mirror circuit, and each of the current mirror circuits
Each transistor has an overcurrent detection resistor and thread
And a sense voltage generating resistor is connected to the sense terminal.
No connection between the overcurrent detection resistor and the transistor
To convert the current of the sense terminal into a voltage in the IC.
In addition, the conversion voltage is compared with the threshold voltage to
It is characterized in that a comparator for detecting current flow is provided .

[0030]

[0031]

[0032]

As described above, in the present invention, a MOSFET with a sense terminal is used. The current flowing to the sense terminal is a small current at a fixed ratio to the drain current, and a resistor for detecting the current of the sense terminal can be provided in the IC. That is, an overcurrent detection resistor that is conventionally externally attached to the IC can be provided inside the IC.

Since a non-detection circuit that does not perform overcurrent detection is provided in the IC during the spike current generation time that occurs when the MOSFET is turned on, a CR that is conventionally provided to prevent the influence of the spike current is provided. A circuit is not required, and a large-capacity capacitor externally attached to the IC is not required. As described above, since there are no external components to the IC, the number of terminals of the IC is reduced, and the size of the switching regulator using the IC can be reduced.

In the IC, a comparator for converting the current of the sense terminal into a voltage and detecting the overcurrent by comparing the converted voltage with a threshold voltage is provided. The comparator includes a pair of transistors having a common base. , The threshold voltage can be set as low as 0.1 V.

As described above, by reducing the threshold voltage, 1 / の of the sense current of the MOS having the sense terminal can be obtained.
The accuracy of the ratio of 890 (example) can be stably maintained.
If the threshold voltage is large, the accuracy of the ratio deviates and the stability deteriorates.

Further, the loss in the overcurrent detection resistor can be made extremely small as compared with the prior art since the current flowing through this resistor can be made small.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A major feature of the present invention is that an MO with a sense terminal is provided.
The overcurrent detection resistor can be changed to IC by using SFET.
In the present invention, the spike current is absorbed by the CR circuit and the CR circuit is not used in the present invention. By providing a non-detection circuit that does not detect current during the spike current generation period, a large capacity is provided. The point is that a capacitor is not required, and external parts for the IC are eliminated.

Further, a stable overcurrent detection accuracy is realized by forming the input stage of the control circuit for overcurrent prevention into a current mirror circuit configuration.

Hereinafter, a detailed description will be given with reference to the drawings.

FIG. 1 is a circuit diagram of a switching regulator according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the IC inside of FIG. 1, FIG. 3 is a circuit diagram of a comparator COM1 inside the IC of FIG. 2, and FIG. circuit diagram of the constant current circuit I ₁ in the IC,
5 is a circuit diagram using a trimming resistor in the circuit of FIG. 4, FIG. 6 is a time chart of the circuit diagrams of FIGS. 1 and 2, and FIG. 7 is a circuit diagram of a non-detection circuit in FIG.

Here, differences from the conventional example shown in FIGS. 8 and 9 will be mainly described. Identical functional parts are given the same symbols.

[0042] As shown in FIG. 1, the switching regulator of this embodiment sense terminal with MOSFET1 using (hereinafter, the sense MOS1 abbreviated with terminal), the sense terminal S1 is connected to the O _C terminal of IC1 I have.

A MOS with a sense terminal is a MOS having a terminal through which a small current flows at a constant ratio with respect to a drain current.

The inside of the IC 1 is as shown in FIG.
The conventional example shown in FIG. 9 has two AND circuits AC2 and AC3.
And that a non-detection circuit DC1 is added.

As shown in FIG. 3, the comparator COM1 of the IC1 has a current mirror circuit (Tr1
1, 12, R1, 2). That is, the transistors Tr11 and T
A detection resistor R1 and a resistor R2 are interposed between each emitter of r12 and GND, respectively. Transistor Tr
Twelve bases and collectors are shorted. Further, the emitter of the transistor Tr11 is connected to O _C terminal of IC1, also, between the emitter and the power supply VS of the transistor Tr12 is connected to a constant current source I _1. The collectors of the transistors Tr11 and Tr12 are connected to the Tr1 of the transistors Tr13, Tr14 and Tr15 whose bases are connected in common.
4 and 15, respectively.

The transistors Tr13, Tr14, Tr15
Are connected to a power supply VS. The base of the transistor Tr 13, the collector is shorted, the constant current source I ₂ is interposed between the collector and the GND. A connection point between the transistors Tr11 and Tr14 is connected to the base of the transistor Tr16,
The emitter of r16 is connected to GND, and the comparator output is taken out from the collector.

The detection resistor R1 is formed in the IC by an emitter diffusion resistor (sheet resistance = 6Ω / □).

In the circuit configuration as described above, the MOS 1 with the sense terminal shown in FIG. 1 has the terminal S ₁ for sensing the drain current as described above. A current of 890 flows. Therefore, when I _D = 2.5 A, I _S ≒ 2.8 mA.
As shown in FIG. 3, the input stage of the comparator COM1 is a current mirror circuit, and the threshold voltage (point of P1) is R2 × (20 μA + 80 μ).
A) = 0.1v.

Therefore, the loss at the detection resistor R1 in FIG. 3 is 0.1v × 2.8mA = 0.28mA. This value can be much smaller than the loss of 0.625 mW in the detection resistor in the conventional example shown in FIGS. here,
The reason why the threshold level is reduced to 0.1 V is to reduce the loss and to maintain the accuracy of the ratio of 1/890 of the sense current. If the threshold level is increased, the accuracy of the ratio is deviated and stability is deteriorated.

Next, the operation of the comparator COM1 will be described with reference to FIG. Normally, P1 point is 0.1v, P
Two points are 35Ω × (1A / 890) = 3 when I _D = 1A.
9mA, Tr11 is ON, Tr16 is OF
F, the output of the comparator COM1 is HIGH.

However, when an overcurrent occurs, I _S becomes 2.8 m.
When the voltage exceeds A, the voltage at the point P2 exceeds 0.1 V, so that Tr
In No. 11, the current of 20 μA cannot be all drawn, and Tr16 is turned ON. Then, the output of the comparator is L
It becomes OW and outputs a detection signal.

Incidentally, in the present embodiment, the detection resistor R
1 (= 36Ω) uses the emitter diffusion resistance as described above. On the other hand, since R2 is 1 kΩ, a base diffusion resistance of a sheet resistance of 220 Ω / □ is usually used due to the problem of chip space, whereas the temperature coefficient of the emitter diffusion resistance of R1 is about 2000 ppM / ° C. , The base diffusion resistance is about 2800 ppM / ° C., and the temperature characteristics of the detection threshold level deteriorate. Therefore, in order to correct this difference in the temperature coefficient, the constant current circuit I1 has a circuit configuration as shown in FIG.

That is, the base of the transistor Tr100 is connected to the resistors R103 and R1 provided between the power supply VS and GND.
04 and a resistor 10 between the emitter and GND.
5 is inserted. The collector of the transistor Tr100 is a transistor Tr10 having a base connected in common.
1, 102 connected to the collectors of the transistors Tr102. The base and the emitter of the transistor Tr102 are short-circuited. Constant current I ₁ is transistor Tr10
3 taken out of the collector.

In the above circuit configuration, the constant current I ₁ is represented by the following equation.

I ₁ = V _A −V _BE1 / R ₁₀₅ (1) where V _BE1 = 0.65 v at Tj = 25 ° C. In the equation (1), R ₁₀₅ is a base diffusion resistance of about 280.
It has a temperature coefficient of 0 ppM / ° C. On the other hand, the molecule is V
_{Due to} the temperature characteristics of _BE1 -2mV / ° C, -2m
It has a temperature coefficient of V / (V _A -V _BE1 ). Therefore,
The numerator can change the temperature coefficient depending on the value of _VA . This V _A
Is obtained by dividing the internal constant voltage V _S (= 4 V) with small temperature fluctuation by R ₁₀₃ and R ₁₀₄ , and the adjustment can be easily performed.

In this embodiment, as described above, the difference between the base diffusion resistance and the emitter diffusion resistance is 2800 ppM−2.
000 ppm = for 800ppM amount of correction is needed, should be about -800ppM / ℃ temperature characteristics of the I _1, V _A = 1.65v, are the R ₁₀₅ = 12.5kΩ.

In order to further improve the accuracy of the overcurrent detection level, a circuit configuration as shown in FIG. 5 may be used. According to the circuit configuration of FIG. 5, since the resistor R can be zener-zipped, the resistance value of R ₁₀₅ can be set to an arbitrary value and I ₁
Values can be adjusted, it will be able to adjust the threshold level V _P1 point P1 comparator of FIG. (V _P1 = R ₁₀₂
× (I ₁ +20 μA)) Next, a circuit configuration of the present embodiment for preventing malfunction due to spike current will be described. The feature of the present embodiment is that a malfunction is avoided by providing a non-detection circuit that does not detect current during a spike current generation period without using a CR circuit as in the related art. Specifically, as shown in the time chart of FIG. 6, a period of about 230nsec the output or non-detection circuit after G _A terminal becomes HIGH LO
W is maintained. During this time, overcurrent detection is not detected, and even if a spike current is generated, erroneous operation can be completely prevented by ignoring it.

FIG. 7 is a circuit diagram of the non-detection circuit.

[0059] In FIG 7, A level shift circuit with respect to the input signal input from the G _A terminal, B is a current mirror circuit, C is a constant current source.

In the level shift circuit A, the collector of the transistor Tr20 to which a signal is input to the base is GN.
D, a transistor Tr2 whose emitter constitutes the base of the transistor Tr21 and the current mirror circuit B;
2, 23, 24, 25 and 26 are connected to the collectors of the transistors Tr22. Diode between the emitter -GND transistor Tr21 D21, D22, resistor R20 is interposed, the collector - resistance between the power supply V _SS R2
1 is inserted.

The connection point between the diode D22 and the resistor R20 is connected to the base of the transistor Tr27, the emitter of which is connected to GND, and the collector of which is connected to the transistor Tr23.
Connected to the collector. The collector of Tr27 is connected to the base of Tr28, the emitter of Tr28 is connected to GND, and the collector is connected to the collector of Tr24 and Tr2.
9 connected to the base. Tr28 Collector-G
A capacitor C20 is interposed between ND. Tr2
9 collector of - resistor R22 is interposed between the power supply V _SS.

The emitter of Tr29 is connected to the base of Tr30, the emitter of Tr30 is GND and the collector is T
It is connected to the base of r31 and the collector of Tr26. The emitter of Tr31 is connected to GND, and the collector is drawn out as the output terminal of the non-detection circuit DC1. Input undetected circuit is connected to G _A terminal that is connected to the gate terminal of MOS1.

In the above circuit configuration, the emitter circumference ratio of each PNP transistor constituting the current mirror circuit A is Tr22: 23: 24: 25: 26 =
0.5: 1: 0.5: 1: 1, and a constant current corresponding to this ratio flows out from each collector.

The value of the constant current I _O of the constant current source C is calculated as follows.

I _O = (4V−0.65V × 3) / 20K
Ω = 102.5 μA ≒ 100 μA Hereinafter, the operation will be described. When G _A pin is LOW (when MOS1 is OFF), Tr20 is ON, Tr21
Is OFF and T27 is OFF, so Tr28
Is ON and V _C1 is LOW. And Tr29
Is OFF, Tr30 is OFF, Tr31 is ON, and the non-detection circuit is LOW (non-detection state).

Next, when the G _A terminal becomes HIGH, T
r20 is OFF, Tr21 and Tr27 are ON, Tr28
Is turned off, and the capacitor C20 is charged by the constant current of 50 μA. Here, the capacitor C20 is for obtaining a delay time. Then, when V _C1 becomes about 1.3 V for two stages of V _BE , Tr29 and Tr30 are turned on.
Then, Tr31 is turned off and the non-detection state is released.

Time t during which the capacitor C20 is charged
= 5pF × 1.3v / 50μA = 130ns and Tr2
About 100n of switching time for 0, 21, 27-31
230ns that the sum of s is, the delay time from when the G _A terminal is a HIGH until Tr31 is OFF,
This is the non-detection time.

Here, the capacitance of the capacitor C20 is 5 pF
Since it is of the order, it can be taken into the IC and does not need to be externally attached unlike the conventional case. That is, the capacitor C
20 and the overcurrent detection resistor R1 described with reference to FIG.
Both can be provided in the IC, and the I
C can be achieved.

As described in detail above, in this embodiment, the use of the MOS with the sense terminal allows the overcurrent detection resistor conventionally connected to the IC to be replaced with the IC.
It can be provided inside. In addition, a non-detection circuit that does not perform overcurrent detection is provided in the IC during the spike current generation time that occurs when the MOS is turned on. Therefore, the CR circuit conventionally provided to prevent the influence of the spike current is unnecessary. This eliminates the need for a large-capacity capacitor externally attached to the IC.

As described above, since there are no external components to the IC, the number of terminals of the IC is reduced, and the size of the switching regulator using the IC can be reduced.

Further, a comparator for converting the current of the sense terminal into a voltage and comparing the converted voltage with a threshold voltage to detect an overcurrent is provided in the IC, and the comparator comprises a pair of transistors having a common base. , The threshold voltage can be set as low as 0.1 V.

As described above, by reducing the threshold voltage, the accuracy of the ratio of 1/890 of the sense current can be stably maintained.

Further, the loss in the overcurrent detection resistor can be made extremely small as compared with the prior art since the current flowing through this detection resistor can be made small, and high efficiency can be achieved.

[0074]

As described above, according to the present invention,
Since there are no components external to the IC, the number of terminals of the IC can be reduced, and the size and cost of a switching regulator using the IC can be reduced.

Also, by using a MOSFET with a sense terminal, the current flowing through the overcurrent detection resistor can be reduced, so that the loss in this resistor can be reduced, and a more efficient switching regulator can be realized.

Further, a current mirror circuit is provided in the overcurrent detection IC, so that the detection operation can be stabilized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a switching regulator according to an embodiment of the present invention.

FIG. 2 is an internal circuit diagram of the IC in FIG. 1;

FIG. 3 is a circuit diagram of a comparator inside the IC of FIG. 2;

FIG. 4 is a circuit diagram of a constant current circuit inside the IC of FIG. 2;

FIG. 5 is a circuit diagram using resistance trimming in the circuit of FIG. 4;

FIG. 6 is a time chart of each part of the circuit diagram of FIGS. 1 and 2;

FIG. 7 is a circuit diagram of a non-detection circuit inside the IC of FIG. 2;

FIG. 8 is a circuit diagram of a conventional switching regulator.

FIG. 9 is an internal circuit diagram of the IC in FIG. 8;

FIG. 10 is a time chart of each part of the circuit diagrams of FIGS. 8 and 9;

FIGS. 11A and 11B are diagrams for explaining the operation of the CR circuit in FIG. 9;

[Explanation of symbols]

T ₁ trans RC1 constant voltage circuit DC1 undetected circuit COM1 comparator R1 overcurrent detecting resistor R2 threshold voltage generating resistor

Claims (1)

(57) [Claims] An output intermittent MOSFET provided on a primary side of a transformer, and a MOS transistor connected to the MOSFET in accordance with a constant voltage obtained by a constant voltage circuit provided on a secondary side of the transformer.
An IC that interrupts the FET and shuts off the MOSFET when an overcurrent on the primary side of the transformer is detected, wherein a MOSFET with a sense terminal is used as the MOSFET, and the current of the sense terminal is detected. A current detection resistor is provided in the IC, and the MOSF is provided in the IC.
During the spike current generation time that occurs when the ET is ON,
The non-detection circuit is not performed overcurrent detection provided, the base consists of a pair of transistors with common boyfriend
The current mirror circuit.
Resistor and threshold for overcurrent detection
A voltage generating resistor is connected, and the sense terminal is
Connected between the current detection resistor and the transistor,
When converting the current of the sense terminal into a voltage in the IC,
In addition, the converted voltage is compared with a threshold voltage to detect an overcurrent.
A switching regulator characterized by comprising a comparator for performing output.