JPH0846565A - Synchronization control system at mobile station in personal handyphone system - Google Patents

Abstract

PURPOSE:To take synchronization and to hold the state without giving effect on the operation of a voice system and radio system in the case of execution of subordinate synchronization with respect to the mobile station synchronization control system for a personal handy phone system in which a synchronization word in a slot sent from a base station is detected to conduct subordinate synchronization. CONSTITUTION:The system is provided with a synchronization word detection section 1 detecting a synchronization word from received data, a slot counter 2 counting number of master clocks in a mobile station to generate timing position in a slot, and a digital PLL control section 5 receiving an output of an oscillator generating a clock signal whose frequency is n-times f the frequency of the master clock and generating the master clock. A phase detection section 3 detects a difference between a value of the slot counter 2 and the estimated position at which the synchronization word is to be in existence at the detection of the synchronization word and the digital PLL control section 5 controls the input of n-times clock based on a signal representing the phase difference and the direction from the phase detection section 3 to generate the master clock subject to 1/n frequency division thereby eliminating sequentially the phase difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile station synchronization control system in a simple type portable telephone device. In recent years, mobile communication has spread rapidly, car phones, mobile phones, pagers, etc. are generally used. Further, a simple mobile phone system is called PHS (Personal Handy phone System), which is a standard domestic air interface. Has been established and is being prepared for practical use. In the simple mobile phone system,
Digital TDMA (Time Division Multiple Acc
ess: time division multiple access), various control channels and call channels for mutually transmitting control information and call information are transmitted and received between the base station and the mobile station. A mobile station that communicates with such digital control channel and call channel signals is required to maintain accurate synchronization with the base station signal.

[0002]

2. Description of the Related Art FIG. 7 is an explanatory view of a conventional example. A. of FIG. As shown in Fig. 1, in the simple type mobile phone device, the base station CS
When the mobile station PS communicates with the mobile station PS, B. 4 channel multiplexing TDMA / TDD (Time Division
Duplex) method is adopted. In this method, T1 to T4
Individual mobile station P transmitting from base station CS in one slot
Reception is performed by S, transmission is performed from an individual mobile station to a base station in four slots of R1 to R4, one frame is composed of eight time slots, and one frame is 5 ms. The signal of each time slot is transmitted as a burst signal of 625 μs, the code length of each slot is 240 bits, and the modulation signal rate is 240 bits × 625 μs = 3.
It becomes 84 KHz.

The slot has a control channel (control carrier) for transmitting and receiving various control signals at the time of originating and terminating, and a communication channel (call carrier for transmitting and receiving information and voice (or data) information necessary for communication. ), There is a signal in two directions, a downlink transmitted from the mobile station to the base station CS and an uplink transmitted from the mobile station to the base station, and the mobile station PS receives and follows a slot transmitted from the base station CS. Need to synchronize.

Referring to FIG. Shows a configuration example of a slot transmitted from the base station CS to the mobile station PS. This example is a communication slot for transmitting voice and data, and R (ramp time) is 4 bits at the tip and SS (start symbol). And P
A UW in which 8 bits including R (preamble) are arranged and then composed of a bit pattern for frame synchronization
(Unique Word) is set to 16 bits (32 bits in the case of control channel), and then 4 bits to represent CI (Channel Identifire) for identifying the type of channel, followed by SA
16 bits representing (SACCH: Slow Associated Control Channel), then voice data (160 bits) is set, and finally CRC (error detection bit) is 16 bits,
After that, G (guard bit) is 16 bits, total 24
It is 0 bit. The control channel is also composed of 240 bits although the content of the signal is different.

A conventional method of synchronization control in a mobile station will be described. An 8-bit counter that counts a clock of 384 KHz is provided for each slot as shown in, and 10H (H is hexadecimal notation, 16 decimal) to FFH (in synchronization with the signal of each bit forming the channel). Up to 255 in decimal, that is, 1
The number of 0 ± 240 ± α (normally 240 bits are counted and changes to the front and back depending on whether UW can be detected and its position) is processed, and each data in the channel is processed according to the count value.

Referring to FIG. As shown in FIG. 7, when the mobile station receives a signal (T1 slot in this example) including the UW (synchronization pattern) sent from the base station CS, the F.F.
UW with a specific pattern from received data as shown in
7 is detected, and the detected output indicates E.E. As shown in, since the count value A (predicted position value) that should have the UW (synchronization pattern) according to the channel is known in advance, this value A is forcibly loaded into the counter to predict the detected position. It was replaced by the position. In addition, since the synchronization operation is not performed during the period when the reception is stopped such as the interval interval, the maintenance of the synchronization state during that period depends on the frequency accuracy of the oscillators of the base station and the mobile station.

[0007]

According to the above-mentioned conventional synchronous control method, there are the following problems. In the simple type portable telephone device, it is necessary to perform speed conversion by PCM coding and ADPCM (adaptive PCM) for a voice system, and at that time, a 64 KHz or 8 KHz clock generated from a 384 KHz clock is used.
However, when the expected position is loaded to the counter by UW detection as described above, the value of the counter suddenly changes and becomes a discontinuous value, and 64 KHz and 8 KHz clocks generated from the 384 KHz clock are generated. Even the phase relationship with the counter output becomes discontinuous. However, if such discontinuity occurs, there is a problem that an error occurs during speed conversion.

In a wireless system, 2-bit data is converted into four phases (0 degree, 0 degree,
(90 degrees, 180 degrees, 270 degrees) are transmitted and received, the phase demodulated on the receiving side is held and the next data is pulled in based on the phase to perform demodulation. If the counter value is different between frames, demodulation cannot be performed, the phase relationship may be converted by 180 degrees, and the symbol clock may be shifted by a half symbol from the previous frame and transmitted from the mobile station. There is a problem that the accuracy deteriorates.

Further, since the synchronous operation is not performed when the reception is stopped during the interval, it becomes impossible to detect the UW for several consecutive frames. In that case, the synchronization itself is lost and the UW cannot be detected. There was a problem of becoming.

According to the present invention, even if the UW detection is performed and the follow-up synchronization is performed, the synchronization can be achieved without affecting the operation for the voice system and the wireless system, and the synchronization can be maintained even during the interval in which the communication is stopped. It is an object to provide a mobile station synchronization control system.

[0011]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is a synchronization word (UW) detection unit, 2 is a slot counter that generates a count value for receiving control in a mobile station, 3 is a phase detection unit, and 4 is a position where the synchronization word should be (count value. ) Is generated by the expected position setting means, 5 is a DPLL control unit (digital PLL) for generating a phase-controlled master clock, 6 is an oscillator for generating a clock having a speed n times that of the master clock,
Reference numeral 7 is an accuracy determination unit that controls the DPLL by obtaining the average value of the past detected phase differences while the received signal is off, and 8 is 64 KH supplied to the audio system (circuits such as PCM and ADPCM).
It is a frequency divider that generates a clock of z or 8 KHz.

According to the present invention, the phase difference between the count value of the slot counter and the predicted position at the time of detecting the synchronization word is obtained, and the clock input of the DPLL for generating the slot counter is controlled according to the phase difference to follow-up synchronization. Is performed and the synchronization is maintained between the intervals.

[0013]

The slot counter 2 in FIG. 1 is a DP inside the mobile station.
The master clock (the same frequency as the received data clock from the base station) generated in the LL control unit 5 is counted, and the count value is used as timing information. When the received data is input to the synchronization word detection unit 1, the synchronization word detection operation is performed in synchronization with the reception clock (CLK). When the synchronization word is detected, the detection output drives the phase detector 3. The phase detector 3 detects the difference between the count value of the slot counter 2 at that time and the predicted position set in the predicted position setting means 4, and generates an output representing the phase difference, while the DPLL controller 5 is on the other hand. Is supplied to the accuracy determination unit 7.

The DPLL control unit 5 inputs a high-speed clock having a frequency n times the frequency of the master clock generated from the oscillator 6, and responds to the direction and the value of the phase difference supplied from the phase detection unit 3. By controlling the high-speed clock input to turn off or on, the phase difference of 1 / n is corrected in one cycle of the receive clock, and the correction operation is performed multiple times corresponding to the number of phase differences, The master clock is controlled so that the expected position of the position setting means 4 and the count value of the slot counter 2 match and finally the phase difference becomes zero. The frequency divider 8 divides the master clock generated from the DPLL control unit 5 to generate a clock used in a voice system of 64 KHz or 8 KHz.

Further, the accuracy determining section 7 receives the phase difference generated from the phase detecting section 3 during the receiving operation, calculates the average value of the phase differences in a fixed period, and holds it. When reception is stopped during the reception interval, the phase detection unit 3 outputs the calculated average value of the phase difference to the DPLL control unit 5, controls the DPLL control unit 5 using the average phase difference, and during the reception interval period. Also follow synchronization.

[0016]

FIG. 2 is a block diagram of an embodiment. In FIG. 2, reference numerals 1 to 7 correspond to respective parts having the same reference numerals shown in FIG. 1, 1 is a UW detection unit for detecting a unique word (UW) which is a synchronization word, and 2 is a timing when counting a 384 KHz master clock. A slot counter that generates information,
3 is a phase detector, 4 is a register in which an expected position where UW is expected to be detected in a slot is set, and 5 is D
(Digital) PLL controller, 6 is a master clock (3
An oscillator for generating a clock with a frequency (19.2 MHz) 50 times as high as 84 KHz, 7 is an accuracy determination unit, 8a, 8b
Is a latch portion, and 9 is a shifter.

In this embodiment, it is assumed that received data is sent from the base station at a bit rate of 384 bps, UW has a fixed bit pattern of 16 bits, and the register 1b of the UW detector 1 is used. Is set to.

When the received data is input to the UW detector 1, the serial data is serial-parallel converted by a flip-flop (FF) 1a having 16 stages and a comparator (COM).
P) is input to 1c. The comparator (COMP) 1c is driven when a window signal having a constant time width expected to include UW as an aperture input is supplied and compared with the 16-bit UW of the register 1b. When the comparison match is obtained, the latch unit 8a is driven by the match output to latch the count value of the slot counter 2 at that time, and the latch unit 8b is driven to drive the DP in the DPLL control unit 5.
The current count value of the LL counter 5d (divided by 25) is latched.

The phase detecting section 3 has the value of the slot counter 2 latched by the latch section 8a and the U value set in the register 4.
The expected position of W is compared by the comparator (displayed by COMP) 3a, and the detected position of UW included in the reception data is before (positive) or after (negative) or coincident (=) with respect to the expected position. Is determined, and the determination result is output as a direction signal (displayed by DIR) when the reception data is on. Further, the computing unit 3b obtains the difference (AB) between the latch 8a and the register 4 and calculates the difference (corresponding to the clock number of 384 KHz) between the value of the slot counter at the time of UW detection and the expected position. The phase difference calculated by the calculator 3b is then multiplied by 50 in the calculator 3c. As a result, the difference in clock number of 384 KHz is converted into the difference in clock number of 19.2 MHz. The value obtained by the arithmetic unit 3c is supplied to the arithmetic unit 3d and latched by the latch unit 8b.
Is added (or subtracted) to the value of.

The operation of the arithmetic unit 3d is controlled by the direction signal (DIR) from the comparator 3a. When the operation is positive (when the UW detection position is before the expected position), the value of the arithmetic unit 3c is set to the latch unit 8b. Value (the value of the DPLL counter) is added as the phase difference (when the received data is on), and if it is negative (UW
When the detected position is after the expected position), the result of subtracting the value of the latch unit 8b from the value of the calculator 3c is output as a phase difference.

The direction signal (DIR) from the phase detector 3 is input to A and the phase difference signal is input to B to the selectors 5f and 5h of the DPLL controller 5. When the received data is on, the selectors 5f and 5h select the signal A and the signal B, respectively, the direction signal of the signal A is supplied to the controller 5g, and the phase difference of the signal B is input to the counter 5i. Counter 5i
Can count up to 1920, and in this case, when the value of the signal B is set, the value is counted and an output is generated to the control unit 5g during that time. The control unit 5g receives the direction signal from the selector 5f and the count output of the counter 5i, and controls to increase or decrease the clock supplied to the DPLL counter 5d.

The oscillator 6 generates a 19.2 MHz clock signal and divides the frequency by 5 in the frequency divider 5a. In this case, two 9.6 MHz clock signals having mutually different phases are generated. However, each of the two 9.6 MHz clock signals has a pulse of the same time width as the 19.2 MHz clock and is supplied to the selector 5b. The selector 5b is controlled by the control unit 5g. When one phase is switched to the other phase, two clocks are continuously generated during one cycle of 9.6 MHz at the time of switching, and one more signal than usual is generated. The counter operation of the DPLL counter 5d that outputs the output and performs the frequency division of 25 can be operated earlier than usual to advance the phase.

This operation is performed at 19.2 MHz from the oscillator 6.
The clock signal is normally divided by 50 to generate one master clock of 384 KHz, whereas it is the same as generating one master clock by division of 49. By repeating the number of times corresponding to, the phase in which the predicted position is delayed from the received data can be advanced.

Further, the mask 5c erases one clock when driven by the controller 5g, and allows the input clock to pass as it is when not driven. When the clock is erased by the mask 5c, the count operation of the DPLL counter 5d is delayed, and the cycle of the master clock (384 KHz) is lengthened and the phase can be delayed. This operation is the same as generating one master clock of 384 KHz by dividing 19.2 MHz from the oscillator 6 by 50, while generating one master clock by dividing 51. By repeating this operation a certain number of times corresponding to the phase difference, it is possible to delay the phase in which the predicted position leads the received data.

In this way, the DPLL counter 5d is
3 by dividing the 6MHz clock by 1/25
Generates a 84 KHz clock signal, of which 384 K
The clock length of Hz is generated based on the number of 9.6 MHz clock signals added or subtracted according to the signal indicating the phase difference from the counter 5i and the direction signal of the selector 5f. The output of the DPLL counter 5d is DEC (decoder)
5e, and converted into a waveform of a clock signal having a duty ratio of 50 here. Specifically, the DPLL counter 5d counts with 8 bits, and if the upper 4-bit value and the lower 4-bit value are displayed in hexadecimal (represented by H), they are 00 to 18H (16 + 8 = 10 in decimal notation). 24)
25 states of 0 to 0CH (0 to 1
In the case of 2), decoding is performed so that "H" output is generated and "L" output is generated between 1CH and 18H.

An arithmetic unit 3d which is generated every fixed number of frames (5 ms period) during the period of receiving the received data.
The phase difference output from the comparator 3a and the direction signal generated from the comparator 3a are stored in the accuracy determination mask 7a of the accuracy determination unit 7. In this case, a numerical value designating how many frames are to be stored is set in advance in the register 7c, and the counter 7b counts the number of signals (not shown) representing the frames by the number set in the register 7c. When the counter 7b reaches the number of registers 7c, the accuracy determination mask 7a performs an operation of averaging the stored values of the plurality of phase differences including the direction signals (positive and negative). During reception, the averaging operation is repeatedly executed, and the latest averaged direction signal (DIR) and phase difference values from the accuracy determination mask 7a are output to the selectors 5f and 5h, respectively, to the signal C and the signal D. Has been entered as.

Although the phase detector 3 does not operate during the reception stop period such as the interval, in this state, the reception ON / OFF signal for controlling the selectors 5f and 5h becomes
To display OFF, the selector 5f selects the signal C,
The selector 5h selects the signal D. As a result, each circuit of the DPLL control unit 5 controls according to the averaged direction signal (DIR) output from the accuracy determination unit 7 and the value of the phase difference. In this way, even when the reception is stopped, the follow-up synchronization can be maintained by performing the synchronization operation based on the average value of the phase differences for the constant frames detected during the reception.

FIG. 3 shows an example of the phase difference detecting operation according to the configuration of the embodiment shown in FIG. As shown in FIG. 3, the master clock (384 KHz) is output, and one cycle of this clock corresponds to one bit length of the received data.
The slot counter (2 in FIG. 2) counts the master clock, and as shown in FIG. 3, the counter value is sequentially incremented to n, n + 1 .... Then, this slot counter value is shifted by a half clock by the shifter 9 of FIG. 2 and supplied to the latch section 8a. This shift is performed to match the bit identification of the received data (when UW is detected) with the timing of the clock falling.

On the other hand, in the UW detector 1 of FIG.
It is assumed that the UW is detected from the received data (at the center of the last bit of the UW) at the time point shown by in the figure in synchronization with the reception clock (CLK) as shown by. At this time, the value of the slot counter 2 (output of the shifter 9) is "n + 1" as shown in, and is latched by the latch unit 8a when UW is detected. Since the predicted UW position is "n" as shown in Fig. 3, "n + 1" and "n" are supplied to the computing unit 3b in Fig. 2, and (n + 1) -n is calculated to "1". Is obtained.

This calculation result "1" is multiplied by 50 (corresponding to the number of 19.2 MHz clocks) in the next calculation unit 3c to obtain "50". Further, this "50" is calculated in the calculator 3d with the output of the DPLL counter 5d. At this time, the output of the DPLL counter 5d that divides the frequency by 25 is "16H" as shown in FIG. 3, and this value is input to the calculator 3d. At this time, the direction signal (DI
R) is in the positive direction because the predicted position of the slot counter 2 precedes the received data, and causes the arithmetic unit 3d to add two inputs.

Thus, the phase difference = 50 from the computing unit 3d.
+ 16 × 2 = 82 is obtained. 16 × 2 is 9.
This is to convert the number of 6 MHz clocks into the number of 19.2 MHz clocks. These 82 are the control part 5g
Control to increase the clock supplied to the. The amount of phase that can be corrected by one control is one clock of 19.2 MHZ.

FIG. 4 shows an operation example of DPLL control. In this example, the UW detection position from the received data is larger than the expected position of the slot counter, and the phase difference value is different from that in the case of FIG.

As shown in FIG. 4, the expected position of the UW is "n" and the slot counter (2 in FIG. 2) is "n + 1".
At this time, UW is detected from the received data as shown in (4) of FIG. 4, and at this time, the DPLL counter (5d in FIG. 2) is set to 6
In the case of (corresponding to a clock of 19.2 MHz), since the phase difference is 1 × 50 = 50, 50 + 6 = 56, and the direction is the negative direction (delay). Therefore, the DPLL control is performed so as to delay the 384 KHz (master clock) input to the slot counter so that the count value of the slot counter is n and the UW detection position of the received data is reached (to set the phase difference 56 to 0). .

In this case, as shown in FIG.
When converted to a 19.2 MHz clock input in the L control unit 5 (FIG. 2), the operation of generating one master clock of 384 KHz at a frequency division of 51 is repeated 56 times. As a result of this operation, the slot counter can set the phase difference to 0 in synchronization with the UW position of the received data. After that,
The DPLL control unit 5 generates one master clock for every normal 50 frequency division.

FIG. 5 is a block diagram of another embodiment, and FIG. 6 is a timing chart of the other embodiment. In another embodiment shown in FIG. 5, the phase difference at the time of reception (when RX is on), which is obtained by using the arithmetic unit in the embodiment of FIG. 2, is obtained by using an up / down counter.

In FIG. 5, 1 to 7 and 9 are the same as those in FIG.
The symbols are the same as those shown in FIG. Also,
Reference numeral 10 is a comparator (indicated by COMP), and 11 is a selector for selecting either a master clock (384 KHz) as a clock signal or 19.2 MHz which is the output of the oscillator 6. In the phase detection unit 3 of FIG. 5, 3e is an up / down (U / D) counter control unit, and 3f is an up / down (U / D) counter control unit.
/ D) counter. In addition, 7d in the accuracy determination unit 7
Is a U / D counter.

Another embodiment of FIG. 5 will be described with reference to FIG. 6 focusing on a phase detection operation different from that of the embodiment shown in FIG. In the UW detector 1 of FIG. 5, the UW (16 bits) set in the register 1b when the window signal of the aperture is present in the comparator (COMP) 1c
And the received data input to the 16-stage flip-flop 1a are compared, and if a comparison match is obtained, an output at the UW detection position is generated and supplied to the U / D counter control unit 3e.

The output of the slot counter 2 for counting the master clock (384 KHz) is phase-shifted by a half clock by the shifter 9 and the comparator (COMP) 10
Is supplied to the U / D counter control unit 3 when it is compared with the expected position set in the register 4 and a comparison match is obtained.
An output representing the expected position is generated at e.

The U / D counter control unit 3e responds to the U / D corresponding to the generation order of the UW detection position output and the expected position detection output and the DPLL ON signal (a signal indicating whether or not the DPLL control unit 5 is ON). Different controls are performed on the D counter 3f.

That is, when the DPLL-ON signal is low (D
(When the PLL is off), in FIG. UW detection position <
In the case of the expected UW position (UW detection occurs first), when the output of the UW detection position occurs, the U / D counter control unit 3e causes EN (enable) of the U / D counter 3f as shown in.
The EN signal supplied to the terminal is set to "H", and the U / D signal supplied to the control terminal in the up / down (U / D display) counting direction indicated by is set to "H" (instruction of up counting).

On the other hand, the clock of the U / D counter 3f (C
The output of the selector 11 is supplied to the L) terminal. At this time, since the DPLL ON signal which is the control signal of the selector 11 is "L", the clock of 19.2 MHz is selected, and the U / D counter 3f outputs UW as shown in FIG.
The 19.2 MHz clock is counted from the detection position. At this time, the U / D counter control unit 3e causes the direction signal (D
IR) A is generated. This signal represents the direction of the phase difference when RX is on.

After that, when the comparator 10 outputs an output indicating the expected position, the U / D counter controller 3e sets the EN signal to "L". As a result, the U / D counter 3f stops the counting operation. At this time, the U / D counter 3f displays 19.2 MH from the UW detection position to the UW predicted position.
The count value of the z clock is output as the phase difference B.

After that, when the control operation of the DPLL control section 5 is started and the DPLL ON signal becomes "H", the U / D counter control section 3e sets the U / D signal to the U / D counter 3f to "L". Then, the EN signal is set to "H" and the down count state is set. At this time, the selector 11 also selects the master clock 384 KHz according to the change of the DPLL ON signal, the selected clock is supplied to the U / D counter 3f, and the phase adjustment for one 19.2 MHz clock is performed in each cycle. Each time it is done, it counts down.

In the DPLL control unit 5, the selectors 5f and 5
The input signal A (U /
The input B representing the phase difference between the direction signal DIR A) from the D counter control unit 3e and the phase difference is selected. The control unit 5g receives the direction signal (DIR) and the phase difference, and if the phase difference is not 0, the phase difference corresponding to the direction DIR is generated according to the direction signal in the same manner as in the case of the embodiment of FIG. The control for advancing the phase of the master clock is performed so that it disappears (the predicted position comes to the UW detection position). The U / D counter 3f is down-counted by one for each correction (one clock of 19.2 KHz), and when the count value becomes 0, the phase correction operation ends.

Next, referring to FIG. Is a case where UW predicted position <UW detected position (UW predicted position occurs before UW detected position), when the DPLL on signal is low (DPLL is off) and UW predicted position output occurs, U The / D counter control section 3e sets the EN signal supplied to the U / D counter 3f to "H" and the U / D signal supplied to the control terminal in the up / down counting direction shown to "H". To do.

Further, the clock of the U / D counter 3f (C
L) terminal, the above A. As in the case of, the selector 11 selects the 19.2 MHz clock shown in FIG.
U / D counter 3f is 19.2 MHz from the UW detection position
Count the clock. At this time, the direction signal A (DIR) of the U / D counter control unit 3e is the A.D. The signal of the polarity ("L") representing the opposite direction to the case of is generated.

In this state, when the U / D counter 3f counts up the 19.2 MHz clock generated after the output of the expected UW position and a signal indicating the UW detection position is generated, the U / D counter 3f outputs the signal EN. Is stopped, and the count value at that time is used as the signal B representing the phase difference, and the direction signal (DIR) A from the U / D counter control unit 3e is transmitted through the selectors 5h and 5f. Each is supplied to the control unit 5g. After this, the above A. In the same manner as in the above case, the U / D counter 3f is switched to perform the down-count, the master clock 384 KHz from the selector 11 is down-counted, and the DPLL control unit 5 delays the phase by one (19.2 MHz clock). Is done.

As in the case of FIG. 2, the accuracy determining section 7 of FIG. 5 obtains the direction signal A at the time of reception ON and the signal B representing the phase difference for a plurality of times, calculates the average value thereof, and outputs the value representing the phase difference as U. The signal is set in the / D counter 7d, and its output is output as the phase difference signal D when reception is off and input to the selector 5h. Further, the signal C is output as the direction signal (DIR) and input to the selector 5f. When the reception is off, the selector 5f selects the signal C, the selector 5h selects the signal D, and when the controller 5g performs the correction operation, the U / D is set for each correction.
The counter 7d counts down one by one, and when it becomes 0, the control operation of the correction by the control unit 5g ends.

In the case of another embodiment shown in FIG. 5, a simple structure can be obtained by using a counter without using a plurality of arithmetic units as in the embodiment of FIG.

[0050]

According to the present invention, in a mobile station of a simple portable telephone device, it is possible to establish subordinate synchronization with a base station without affecting voice system and radio system. Further, even when reception is stopped, the synchronized operation can be maintained for a longer period of time by performing the synchronized operation with the previous phase, and the performance of the simplified mobile phone device can be improved.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a diagram showing an example of a phase difference detection operation according to the configuration of the embodiment.

FIG. 4 is a diagram illustrating an operation example of DPLL control.

FIG. 5 is a configuration diagram of another embodiment.

FIG. 6 is a timing chart of another embodiment.

FIG. 7 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1 Synchronization Word (UW) Detection Unit 2 Slot Counter 3 Phase Detection Unit 4 Expected Position Setting Means 5 DPLL Control Unit 6 Oscillator 7 Accuracy Judgment Unit 8 Frequency Divider

Claims (3)

[Claims] 1. A simple portable telephone device for detecting subordinate synchronization by detecting a synchronization word in a slot transmitted from a base station to a mobile station at a constant frame period, for synchronization for detecting a synchronization word from received data. A word detector, a slot counter that counts the master clock in the mobile station having the same frequency as the received data clock to generate timing position information in the slot, and a detection output from the word detector for synchronization. A master clock is input by inputting a phase detection unit that detects a difference between the value of the counter and a preset expected position of the synchronization word, and an output of an oscillator that generates a clock n times the frequency of the master clock. And a digital PLL control unit for generating the phase difference input from the phase detection unit. Based on the signal indicating the direction, the n
A mobile station synchronization control system in a simplified portable telephone device, wherein the phase difference is sequentially eliminated by controlling input of a double clock and generating a master clock divided by n. 2. The phase detecting section according to claim 1,
A comparator for generating a direction (positive or negative) signal by comparing the value of the slot counter with an expected position, a first arithmetic unit for obtaining a difference between the two values, and a first arithmetic unit A second arithmetic unit for multiplying the difference value by n times, and a count value at the time of detecting the synchronization word of a DPLL counter provided in the digital PLL control section for counting a clock having a frequency of n times the clock of the reception data. And a third arithmetic unit for generating a phase difference signal by subtracting or adding the output of the second arithmetic unit with the direction signal from the comparator, and generating a phase difference signal. The phase difference signal from the arithmetic unit is supplied to the digital PLL control unit, and the clock signal from the clock generator having the n-fold frequency is switched on or off according to the direction and the value of the phase difference, and n Input to the frequency divider of Mobile station synchronization control method in the personal handyphone system, characterized by generating a master clock from the vessel. 3. The accuracy determination unit according to claim 1, further comprising an accuracy determination unit to which the phase difference detected by the phase detection unit is input, wherein the accuracy determination unit is a phase difference in a fixed number of frames when reception data is on. Is calculated, and when the received data is in the OFF state, the average value of the calculated phase difference is supplied to the digital PLL control unit for control, and the mobile station synchronization in the simple type portable telephone device is performed. control method.