JP3349459B2 - Clock timing switching device and portable terminal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching device for switching clock timing, and more particularly to a timing switching control between a low-speed clock and a high-speed clock in a device with intermittent operation.

[0002]

2. Description of the Related Art Conventionally, most portable devices are operated by a power source such as a battery, and therefore, perform intermittent operations so that the devices can be operated for a long time.
For example, taking a second generation cordless telephone (hereinafter abbreviated as “PHS”) as an example, as shown in FIGS. 4, 5, and 6,
Incoming information from the public base station is received in a predetermined slot having a section of 0.625 ms in a superframe having a section of 1.2 seconds, and the timing of receiving the incoming information is 1 in 1.2 seconds. There exist times. For example, in a superframe having a section of 1.2 seconds, 12
The LCCH transmission intervals as shown in FIG. 5 are provided, and the LCCH shown in FIG. 5 corresponds to a predetermined TDMA frame,
An LCCH transmission section corresponds to, for example, PCH1.
Therefore, most of the 1.2 seconds of the superframe are in a standby state in which incoming information is not received, and high-speed processing is not required. In this standby state, a low-speed clock (for example, 32.768K) is used to reduce power consumption.
Hz), the operation is switched to a high-speed clock (for example, 384 kHz) immediately before performing the incoming call process for receiving the incoming call information. Then, it is necessary to perform the switching while maintaining the timing to be held when the switching is performed. Therefore, a long time is required for the process for performing the switching, which hinders a reduction in power consumption.

That is, the conventional configuration and its operation will be described. As shown in FIG. 7, a conventional clock timing switching device B comprises a first counter 100, an initial value generator 102, a second counter 104, It has a timing pulse generator 106, a third counter 108, a main controller 110, and a reception controller 112. Here, the first counter 100 performs counting based on a low-speed clock. Here, the low-speed clock is
32.768 kHz, and this 32.768 kHz
Is exactly 125ms by counting just a predetermined number of times
Becomes

That is, the first counter 100 has a capacity of about 5
The count value information is sent to the initial value generator 102 every ms. Here, “about 5 ms” is the reason for the above 32.76.
This is because a low-speed clock of 8 KHz cannot accurately measure 5 ms. Also, the initial value generator 102
Generates an initial value of the second counter 104 according to the count value sent from the first counter 100. The second counter 104 counts according to a high-speed clock, and counts from 0 to 239. Here, the frequency of the high-speed clock is 384 kHz as described above, which is 0.625 ms when counted 240 times. In addition, every time the count of the second counter 30 ends, the timing pulse generator 106
08 and a third counter 10
Each time the count of 8 is completed, a pulse is output. The third counter 108 counts according to the pulse sent from the timing pulse generator 106, and counts from 0 to 7. Further, the main control unit 110 controls the operation of each unit in the clock timing switching device B.

Here, the operation of the clock timing switching device B having the above configuration will be described with reference to FIG. In addition,
In FIG. 8, the vertical solid line in the timing pulse generator indicates a pulse signal. First counter 10
0 sends the count value information to the initial value generator 102 about every 5 ms according to the low-speed clock. Then, the initial value generator 102 generates a predetermined initial value based on the count value sent from the first counter 100. Specifically, a predetermined initial value is calculated according to a predetermined operation formula. This initial value is calculated so that it can be adjusted to the timing of the slot to be received by correcting the error when counting with a low-speed clock.

Here, it is assumed that the slot to which the portable terminal equipped with the clock timing switching device B is allocated is located at the position Q in FIG. Then, main controller 110 roughly grasps the position of the slot to receive the transmission signal from the base station as 1.2 seconds after the previous successful reception, and immediately before the slot to be received. At a switching timing t1 which is one before the switching timing t2, a clock switching signal is output to the second counter 104. That is, the switching timing is
It exists at every timing of about 5 ms counted by the first counter 100.

When the second counter 104 receives the switching signal from the main control unit 110, the second counter 104
02, the initial value calculated is read out, counting is performed based on the high-speed clock from the initial value, and the count value is output to the timing pulse generator 106. Then, when receiving the information having the count value of 239, the timing pulse generator 106 outputs a pulse to the third counter 108. In other words, the timing pulse generator 106 outputs 0.
A pulse is output to the third counter 108 every 625 ms. All the pulses shown in the “timing pulse generator” of FIG. 8 correspond to the pulses sent to the third counter 108. That is, both the long pulse and the short pulse among the pulses shown in the “timing pulse generator” of FIG. 8 are included. Then, the third counter 108 receives 0.625 m from the timing pulse generator 106.
The count value is increased each time a pulse for each s is input, and the count value is output to the timing pulse generator 106. The count value is output from 0. When receiving the information with the count value of 7, the timing pulse generator 106 outputs a pulse to the outside. The long pulse shown in the “timing pulse generator” in FIG. 8 corresponds to this pulse. Then, the reception control unit 112 opens a reception window formed by a filter slightly before the position of the slot to be received, and determines whether or not the received synchronization word matches a previously held synchronization word. If they match, subsequent incoming call processing is performed.

[0008]

However, according to the above-described conventional clock timing switching device, switching from the timing of the low-speed clock to the timing of the high-speed clock is performed as described above, so that at least 5 ms before the slot to receive. The high-speed clock operation time of this time means that the operation is performed with the high-speed clock unnecessarily long. This hinders a reduction in power consumption, which is particularly required for portable devices. On the other hand, if the switching is forcibly performed ignoring the timing of about every 5 ms,
Since the initial value of the counter 108 does not reflect the timing held by the low-speed clock and becomes a specific value, the timing generated by the third counter 108 is shifted due to the switching of the clock timing. .

Therefore, the present invention provides a PHS which performs an intermittent operation.
It is an object of the present invention to provide a clock timing switching device capable of switching from timing using a low-speed clock to timing using a high-speed clock in various devices such as a portable terminal in a short time while maintaining the timing to be held. Things.

[0010]

[0011]

To SUMMARY OF THE INVENTION The first is a clock timing switching device for switching clock timing between the low-speed clock and the high-speed clock, a first counter for measuring a predetermined time by the slow clock A first timing pulse generator that outputs a pulse signal at predetermined intervals based on a value measured by the first counter, and a first initial value that outputs a first initial value based on a value measured by the first counter A generator, a second initial value generator that outputs a second initial value based on a value measured by the first counter,
A clock switching signal output circuit that outputs a clock switching signal at the timing of any one of the pulse signals output by the first timing pulse generator;
A second counter for measuring a predetermined time by a high-speed clock, wherein when a clock switching signal is received, the first counter reads the first initial value from the first initial value generator and measures from the first initial value. Counter, a second timing pulse generator that outputs a pulse signal when the second counter measures a predetermined time, a pulse signal from the first timing pulse generator, and a second timing pulse generator A pulse signal from the second timing pulse generator when a clock switching signal is input from the clock switching signal output circuit to the switching device. And a pulse signal output from the first timing pulse generator or a pulse signal output from the second timing pulse generator. And can the second counter and a third counter for measuring another time, when the second timing pulse generator receives a pulse signal to be output, the second
The second initial value is read from the initial value generator and the second
And a third timing pulse generator that outputs a pulse signal when the third counter measures a predetermined time. In clock timing switching device of the first configuration, first, the first counter measures the predetermined time by the low-speed clock, the first initial value generator, said first
A first initial value is output based on a value measured by the counter. Further, the second initial value generator outputs a second initial value based on the value measured by the first counter. Then, when a clock switching signal is output from the clock switching signal output circuit and the second counter receives the clock switching signal, the second counter reads the first initial value from the first initial value generator and reads the first initial value from the first initial value generator. The measurement is performed from the initial value of. The second counter measures based on a high-speed clock. When the second counter measures a predetermined time, the second timing pulse generator outputs a pulse signal. Then, when the clock switching signal is input to the switch, the switch switches the pulse signal from the second timing pulse generator to the third timing pulse generator.
When receiving the pulse signal, the third counter reads the second initial value from the second initial value generator and counts from the second initial value. The measurement is performed according to the pulse signal output from the second timing pulse generator. Then, when the third counter measures a predetermined time, a pulse signal is output. Until the clock switching signal is input to the switch, the pulse signal output from the first timing pulse generator is input to the third counter, and thus the third counter outputs the signal from the first timing pulse generator. The measurement is performed based on the pulse signal. Thereby, the timing of the pulse signal output from the switch is set as the switchable timing, and the pulse signal from the first timing pulse generator is output from the switch before the clock switching signal is output. If the clock switching signal is output at the switchable timing located immediately before the reception section to be received in the timing, the high-speed clock operation time before the reception section to be received can be reduced by the generation of the first timing pulse. It is shorter than the output interval of the pulse signal from the device. Further, by setting the initial values of the second counter and the third counter respectively, the clock timing can be switched while maintaining the timing to be held in a short time as a whole.

[0012] The second, in the first configuration, the clock switching signal output circuit, the timing of the pulse signal the switch outputs, and outputs the clock switching signal. Third ,
In any one of the first and second configurations, the output interval of the pulse signal output by the first timing pulse generator is a time that is substantially an integral multiple of the time measured by the second counter. And

Further, in the fourth, in the construction of the first through third, the first timing pulse generator outputs a pulse signal every approximately 1.25ms based on the low-speed clock, the The second counter measures a time of 0.625 ms based on a high-speed clock, and the third counter measures a time of 5 ms. Fifth , in any one of the first to fourth configurations, the second timing pulse generator and the third timing pulse are integrally formed. Sixth , in any of the first to fifth configurations, the low-speed clock is
2.768 kHz and the high-speed clock is 384 kHz
It is characterized by being.

A seventh aspect is a portable terminal having a clock timing switching device having any one of the above-described first to sixth configurations, wherein when a clock switching signal is output, the mobile terminal in a predetermined period thereafter. An incoming signal is detected, and when a synchronization word in the incoming signal matches, an incoming process is performed. Thus, the incoming call can be made with the operation time of the high-speed clock as short as possible. Further, the eighth, the configuration of the seventh, characterized in that said mobile terminal is compliant with the PHS.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, a clock timing switching device A according to the present invention includes a first counter 10, a timing pulse generator 12, a first initial value generator 14, a second initial value generator 16, Second
It has a counter 18, a timing pulse generator 20, a switch 22, a third counter 24, a main controller 26, and a reception controller 28.

Here, the first counter 10 counts based on a low-speed clock.
The information of the count value measured about every two slots derived from the low-speed clock, that is, about every 1.25 ms, is sent to the first initial value generator 14, the second initial value generator 16, and the timing pulse generator 12. Here, the low-speed clock is 32.768 KHz. Here, “about 2 slots” and “about 1.25 ms” are defined as 32.76.
This is because accurate measurement cannot be performed with a low-speed clock of 8 KHz.

The timing pulse generator 12 outputs a timing pulse (pulse signal) about every 1.25 ms based on the information of the count value sent from the first counter 10 about every 1.25 ms. The timing pulse generator 12 functions as the first timing pulse generator and the first signal generator.

Further, the first initial value generator 14 generates the second counter 1 according to the count value sent from the first counter 10.
8 is generated. Also, the second initial value generator 16
Generates an initial value of the third counter 24 according to the count value sent from the first counter 10. The second counter 18 counts according to the pulse of the high-speed clock, and counts from 0 to 239. here,
As described above, the frequency of the high-speed clock is 384 kHz, which is 0.625 ms when counted 240 times. That is, the second counter 18 measures one slot time. This second counter 18
Functions as the first measuring means.

The timing pulse generator 20 switches the switch 22 each time the second counter 18 finishes counting.
And outputs a pulse signal to the third counter 24.
The timing pulse is output each time the counting is completed. The timing pulse generator 20 functions as the second timing pulse generator, the third timing pulse generator, the second signal generator, and the third signal generator. Further, the switch 22 sends either the timing pulse sent from the timing pulse generator 12 or the timing pulse sent from the timing pulse generator 20 to the third counter 24 based on the clock switching signal from the main control unit 26. Output. The third counter 24 counts according to the timing pulse sent from the switch 22, and counts from 0 to 7. That is, the third counter 24 measures the time of one frame (5 ms). The third counter 24 functions as the second measuring means.

The main control section 26 controls the operation of each section in the clock timing switching device A. In particular, the main control section 26 sends a clock switching signal to the second counter 18, the third counter 24, and the switch 22. Output. That is, the main control section 26 functions as the clock switching signal output circuit. After outputting the switching signal to the high-speed clock, the main control unit 26 monitors the value of the second counter 18 and the like, and instructs the reception control unit 28 to open the reception window at a predetermined timing. To give instructions.

The reception control unit 28 has a synchronization word determination circuit, a reception window filter, a post-processing circuit, and the like. Here, the synchronization word determination circuit examines the synchronization word received from the base station at the time of high-speed clock operation and determines whether or not the synchronization word matches a previously held synchronization word,
If they match, a pulse is generated. Further, the reception window filter sends only the pulses that enter the reception window among the generated pulses to the post-processing circuit.

The operation of the clock timing switching device A having the above configuration will be described with reference to FIGS. The clock timing switching device A is mounted on a PHS portable terminal, and in a section for receiving an incoming signal from a base station, so-called intermittent reception in which a high-speed clock is operated to perform reception is performed. In a so-called standby state, basically, it is sufficient to operate with a low-speed clock. In FIG. 2, the timing pulse generator 1
2. The vertical solid line in the timing pulse generator 20 indicates a pulse signal.

The first counter 10 sends count value information to the first initial value generator 14, the second initial value generator 16, and the timing pulse generator 12 at about every 1.25 ms according to the low-speed clock. Specifically, the first counter 10
The value of a predetermined upper bit of the value counted according to the low-speed clock is output as a count value. The low-speed clock is always input to the first counter 10.

Then, the timing pulse generator 12
According to the information from the first counter 10, a timing pulse is generated about every two slot intervals. That is, if the timing pulse generator 12 attempts to output a timing pulse every two slot intervals based on the signal sent from the first counter 10, the timing pulse generator 12 becomes 1.2512207 ms, which is an accurate time 1.25 ms for the two slot intervals. Thus, a timing pulse is generated in a cycle including an error. From this, the timing pulse generator 12 has about 2
It is assumed that a timing pulse is generated for each slot section.

The first initial value generator 14 generates a predetermined initial value m based on the count value sent from the first counter 10. Specifically, a predetermined initial value m is calculated according to a predetermined operation formula. The initial value m is calculated so that it can be adjusted to the timing of the slot to be received by correcting the error when counting with a low-speed clock. That is, the initial value m is calculated so that the error of the slot interval can be corrected.

On the other hand, the second initial value generator 16 generates a predetermined initial value n based on the count value sent from the first counter 10. Specifically, a predetermined initial value n is calculated according to a predetermined operation formula. The initial value n is changed from the timing of 5 ms based on the low-speed clock to 5 based on the high-speed clock.
It is calculated so that switching can be appropriately performed at the timing of ms.

The switch 22 operates during the low-speed clock operation time (see FIG. 2).
It has been switched to two sides. That is, the pulse from the timing pulse generator 12 is sent to the third counter 24. This low-speed clock operation time is a state in which the high-speed clock shown in FIG. 1 is not input to the second counter. In this low-speed clock operation time, the switch 22 sends the timing pulse about every two slots sent from the timing pulse generator 12 to the third counter 24. And
When the pulse from the timing pulse generator 12 is sent to the third counter 24, that is, before the clock switching signal is input to the third counter 24, the third counter 24 receives one pulse. Each time the process is performed, a process of increasing the count value by 2 is performed. On the other hand, when the pulse from the timing pulse generator 20 is sent to the third counter 24, that is, when the clock switching signal is
When the input is 4, the third counter 24 increases the count value by one each time one pulse is received. That is, while the pulse is output from the timing pulse generator 12 about every two slots, the pulse is output from the timing pulse generator 20 every slot, and thus such processing is performed. .

Here, it is assumed that the slot to which the portable terminal equipped with the clock timing switching device A is assigned is the slot Pn in FIG. Then, the main control unit 26 outputs a clock switching signal to the second counter 18, the switch 22, and the third counter 24 at a predetermined timing. Here, the clock switching signal is performed at a predetermined timing at a timing of about every two slots generated by the timing pulse generator 12 (this is referred to as “switchable timing”). More specifically, the position of the slot to receive the transmission signal from the base station is set to be 1.2 seconds after the previous successful reception, or the number of slots since the previous successful reception. It is grasped by counting or the like, and the switchable timing immediately before the slot to be received is set as the switching timing. Assuming that the slot to be received is the slot Pn in FIG. 2, the switchable timing immediately before the slot Pn is time S1, and this time S1 is the switching timing. That is, the main control unit 26 outputs the clock switching signal at the timing of the time S1. That is, between the initial time S3 of the slot Pn to be received and the switching timing S1, 1
There is a section t in which the section P 'that is shorter than the slot time and the section of the slot Pn-1 are combined. In addition,
It is assumed that this clock switching signal includes information to instruct switching of the clock timing and information to operate at the timing of the high-speed clock.

When the second counter 18 receives the clock switching signal, the second counter 18 reads the initial value m calculated by the first initial value generator 14, sets the initial value m, and thereafter sets the initial value m. The count is performed based on the high-speed clock, and the count value is output to the timing pulse generator 20. The high-speed clock is output from a high-speed clock output unit (not shown), but the second counter 1 is output slightly before the clock switching signal is output from the main control unit 26.
8 is input. By setting the initial value m in this way, an error in the slot interval due to operation with a low-speed clock is corrected. If there is no error, the initial value m is the value at the start of the counter, ie,
0, in which case there is no section P 'of less than one slot in FIG.

Then, the timing pulse generator 20
When the information of the count value of 239 is received, the pulse is changed to the third pulse.
Output to the counter 24. That is, the timing pulse generator 20 outputs a pulse to the switch 22 every 0.625 ms. All the pulses shown in the “timing pulse generator 20” of FIG. 2 correspond to the pulses sent to the switch 22. That is, both the long pulse and the short pulse among the pulses shown in the “timing pulse generator 20” of FIG. 2 are included.

When the clock switching signal is sent to the switch 22, the switch 22
Switch to the side. Thus, the pulse from the timing pulse generator 20 is sent to the third counter 24, and the pulse from the timing pulse generator 12 is sent to the third counter 2
Not sent to 4.

On the other hand, when the first timing pulse is sent from the timing pulse generator 20 via the switch 22 to the third counter 24, the third counter 24 reads the initial value n calculated by the second initial value generator 16, The initial value n is set, and thereafter counting is performed from the initial value n. Since the clock switching signal is also input to the third counter 24,
When the clock switching signal is received, the incoming timing pulse is from the timing pulse generator 20, so the third counter 24 increases the count value by one each time the timing pulse arrives. By setting the initial value n in this manner, even if switching is performed at a timing between timings of 5 ms, it is possible to appropriately switch from the timing of 5 ms based on the low-speed clock to the timing of 5 ms based on the high-speed clock. ing. When the timing of every 5 ms comes at the same time as the timing when the counter of the second counter 18 ends, the initial value n becomes the value at the start of the counter, that is, 0. Note that the switch 22 is connected to the timing pulse generator 20.
If it is switched to the side, the information to that effect
From the second to the third counter 24, when the information is received, the third counter 24 may increase the count value by one each time a timing pulse from the timing pulse generator 20 arrives. .

Then, the third counter 24 outputs the count value to the timing pulse generator 20. Then, when receiving the information with the count value of 7 from the third counter 24, the timing pulse generator 20 outputs a timing pulse to the outside. That is, the timing pulse generator 20
Outputs a timing pulse every 5 ms. The long pulse shown in the “timing pulse generator 20” in FIG. 2 corresponds to this.

When the clock switching signal is sent from the main control unit 26, the reception control unit 28 receives the incoming signal sent from the base station,
It is determined whether the received synchronization word matches the synchronization word stored in advance. If they match, it is understood that the slot is a slot that the mobile terminal should originally receive. If the synchronization words match, a pulse signal is generated.

The main control unit 26 controls the reception of the opening of the reception window for a predetermined period based on the count values of the second counter and the third counter, a flag indicating that a slot to be received soon is arriving, and the like. Instruct the unit 28. The flag is generated based on the time since the previous reception was successful, the number of slots, and the like. Then, the reception control unit 28
When the main control unit 26 receives an instruction to open the receiving window from the main control unit 26, the receiving window filter performs a process of transmitting a pulse generated by the synchronization word determining circuit to a post-processing circuit for a predetermined time. The predetermined time is a time from the time Sa (see FIG. 3) at the substantially intermediate position in the slot Pn-1 immediately before the slot Pn to be received to the time Sb (see FIG. 3) at the substantially intermediate position in the slot Pn. And That is, the time Sa is a substantially intermediate position between the times S1 and S3,
Time Sb is slightly behind the intermediate position between times S3 and S4. This is because the synchronization word is stored in the first half of each slot, and furthermore, the time is set to a certain margin. Then, a pulse signal output when the synchronization words match, which is based on the synchronization word received in the above-mentioned time zone, is sent to the post-processing circuit, and specific incoming processing is performed.

That is, the operation of the clock timing switching device A of the present embodiment can be summarized as follows. That is, since the timing pulse generator 12 generates a pulse based on the first counter 10 that counts according to the low-speed clock, an error is accumulated in the pulse. However, the error is reset when 125 ms is measured. Next, the counting operation of the first counter 10 is performed. When the timing is switched to the high-speed clock when the error is cleared, the switching time is set to 0, and the second counter 18 and the third counter 24 are switched.
The timing of the switching is maintained by operating. In other words, the initial values m and n may be basically set to 0 to perform the counting operation. In this case, since the second counter 18 actually starts counting at the falling edge of the pulse of the timing pulse generator 12, the initial value m is considered in consideration of the pulse width.
Is set to about 12 instead of 0. When the second counter 18 starts counting at the rising edge of the pulse of the timing pulse generator 12, the initial value m is 0.
Is good. However, when receiving a superframe configured with a channel frame having a period of 5 ms as a minimum unit, switching of clock timing does not always occur when an error is reset. When the switching of the clock timing occurs, the first operating with the low-speed clock
Based on the value of the counter 10, the first initial value generator 14 generates an initial value at the start of counting after clock switching of the second counter 18, and similarly, generates a second initial value based on the value of the first counter 10. The generator 16 generates an initial value at the start of counting after the clock switching of the third counter 24, and sets each initial value in the counter immediately before the counting operation by the high-speed clock, so that the timing before and after the clock timing switching is performed. That is, the switching can be performed while the information is held.

As described above, according to the clock timing switching apparatus A of the present embodiment, the high-speed clock operation time existing before the slot to be received is the sum of the section less than one slot and the section of one slot. As a result, the unnecessary clock operation time does not exceed two slots, and the unnecessary high-speed clock operation time can be reduced as compared with the conventional case. In addition, by setting the initial values of the second counter 18 and the third counter 24, the clock timing can be switched while maintaining the timing to be held in a short time as a whole.

In the above description, the pulse output from the timing pulse generator 12 is described as being about every two slots. However, the present invention is not limited to this, and three or more slots or one slot may be used. That is, any output interval of the timing pulse output from the timing pulse generator 12 can be used as long as the output time is approximately an integral multiple of the time measured by the second counter 18.
For example, when one slot is set, the second counter 18
Is the initial time of the slot to be received. Therefore, the receiving window is opened immediately after the second counter 18 finishes counting.

In the above description, the timing pulse generator 20 outputs a timing pulse for each slot (0.625 ms) and also outputs a timing pulse for every 5 ms.
A timing pulse generator that outputs a timing pulse for each slot based on the count by the second counter 18 and 5 ms based on the count by the third counter 24
The timing pulse generator that outputs a timing pulse for each of the above may be configured differently.

[0040]

According to the clock timing switching device and the portable terminal of the present invention, the initial value of the second counter and the initial value of the third counter are respectively determined, so that the low-speed clock can be maintained while maintaining the timing to be maintained in a short time. The clock timing can be switched from the timing to the timing of the high-speed clock.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock timing switching device according to an embodiment of the present invention.

FIG. 2 is a time chart showing operation timings of the clock timing switching device according to the embodiment of the present invention.

FIG. 3 is an enlarged view of a main part of FIG. 2;

FIG. 4 is an explanatory diagram showing a configuration of a superframe in a PHS radio channel.

FIG. 5 is an explanatory diagram showing LCCH transmission timing in a PHS radio channel.

FIG. 6 is an explanatory diagram showing a configuration of a TDMA frame in a PHS radio channel.

FIG. 7 is a block diagram showing a configuration of a conventional clock timing switching device.

FIG. 8 is a time chart showing operation timing of a conventional clock timing switching device.

[Explanation of symbols]

 A clock timing switching device 10 first counter 12, 20 timing pulse generator 14 first initial value generator 16 second initial value generator 18 second counter 22 switch 24 third counter 26 main control unit 28 reception control unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-9-62396 (JP, A) JP-A-2000-78073 (JP, A) JP-A-10-257004 (JP, A) JP-A-9-18405 (JP, A) JP-A-2000-49682 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 1/06 G06F 1/14 G06F 9/30 330 H04B 7/26 H04M 1 / 72

Claims (8)

(57) [Claims] 1. A clock between a low-speed clock and a high-speed clock.
Clock timing off for switching lock timing
A switching device, wherein a predetermined time is set by a low-speed clock.
A first counter to be measured and a value to be measured by the first counter
1st time which outputs a pulse signal at predetermined intervals based on
Pulse generator and the value measured by the first counter.
A first initial value generator that outputs a first initial value based on the first initial value;
The second initial value is output based on the value measured by the first counter.
A second initial value generator and the first timing pulse
Any pulse in the pulse signal output by the generator
A clock that outputs a clock switching signal at the signal timing
Clock switching signal output circuit and high-speed clock
A second counter for measuring the time of
From the first initial value generator when receiving the
The first initial value is read out and measurement is performed from the first initial value.
The second counter to perform, and the second counter measures a predetermined time
The second timing pulse that outputs a pulse signal
Pulse generator and a pulse from the first timing pulse generator
Signal and the pulse signal from the second timing pulse generator
Switch that switches and outputs the clock
A signal is input from the clock switching signal output circuit to the switch.
The second timing pulse generator
A switch for outputting a pulse signal, and the first timing pulse
Pulse signal and second timing pulse output by the pulse generator
The pulse signal output by the generator.
This is a third counter that measures a different time from the counter.
The pulse signal output by the second timing pulse generator.
Signal is received from the second initial value generator.
2 is read and the measurement is performed from the second initial value.
A third counter, and the third counter measures a predetermined time.
3rd timing pulse which outputs a pulse signal when
And a clock timing generator.
Switching device. 2. The clock switching signal output circuit according to claim 1 ,
At the timing of the pulse signal output from the switch,
2. A lock switching signal is output.
2. The clock timing switching device according to claim 1. 3. An output from said first timing pulse generator.
The second counter measures the output interval of the pulse signal
Claims, characterized in that it is substantially an integral multiple of the time period of
Item 3. The clock timing switching device according to item 1 or 2. 4. The method according to claim 1, wherein the first timing pulse generator has a low level.
A pulse signal is generated approximately every 1.25 ms based on the speed clock.
And the second counter is based on a high-speed clock.
The time of 0.625 ms was measured, and the third
The counter is characterized by measuring a time of 5 ms.
4. A clock timing switch according to claim 1, 2 or 3.
Device. 5. The apparatus according to claim 1, wherein said second timing pulse generator and a third
The feature is that the timing pulse is integrally formed
The clock generator according to claim 1, 2, 3, or 4,
Imming switching device. 6. The low-speed clock is 32.768 kHz.
Wherein the high-speed clock is 384 kHz.
The black-and-white filter according to claim 1 or 2 or 3 or 4 or 5.
Lock timing switching device. 7. The method according to claim 1, wherein
Or a clock timing switching device according to item 6.
A mobile terminal that outputs a clock switching signal
And the incoming signal in a predetermined section after that,
If the sync words in the incoming signal match,
Mobile terminal characterized in that it performs processing. 8. The portable terminal is compliant with PHS.
The mobile terminal according to claim 7, wherein: