JPH0846159A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To facilitate processing of bit line selection transistor by forming bit line selection transistors almost in the same shpae as a selection transistor and then arranging the selection transistor to the position where the selection transistor is moved in parallel in the bit line direction. CONSTITUTION:The bit line selection transistors Qn4, 5 are formed adjacent to NAND cell unit within a memory cell array formed on a p-type well. The source/drain thereof is the n-type diffused layer 4 which forms the source/drain of the selection transistor and the gate electrode thereof is formed by a wiring layer 2 in the same gate length. The bit line selection transistors Qn4, 5 can be formed almost in the same shape by forming them simultaneously with the selection transistor. Processing of the bit line selection transistors can be done easily while keeping the regular shape of the memory cell array by forming the bit line selection transistors Qn4, 5 with the selection transistors in the memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an electrically rewritable non-volatile semiconductor memory device (EEPROM), and more particularly to an EEPROM for writing / erasing a memory cell by a tunnel current. .

[0002]

2. Description of the Related Art As one of the EEPROMs, a NAND cell type EEPROM capable of high integration is known. This is to connect a plurality of memory cells in series so that their sources and drains are shared by adjacent ones.
It is connected to the bit line as a unit. The memory cell usually has a FETMOS structure in which a charge storage layer (floating gate) and a control gate are stacked. The memory cell array is integrated and formed in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to the bit line via the select gate, and the source side is also connected to the common source line via the select gate. The control gates of the memory cells are continuously arranged in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (about 20 V) is applied to the control gate of the selected memory cell, and an intermediate voltage Vpp is applied to the control gate of the memory cell on the bit line side and the select gate on the drain side.
m (= about 10V) is applied, and 0V or an intermediate voltage Vmb (= about 8V) is applied to the bit line according to the data.

When 0V is applied to the bit line, the potential is transferred to the drain of the selected memory cell, and electron injection occurs in the charge storage layer. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is set to "0", for example. When Vmb is applied to the bit line, electron injection does not substantially occur, so the threshold does not change,
Stop negative. This state is "1" in the erased state. It should be noted that data writing is simultaneously performed on the memory cells sharing the control gate.

Data erasing is simultaneously performed on all the memory cells in the selected NAND cell. That is, all the control gates in the selected NAND cell are set to 0V and the p-type well is set to 20V. At this time, the selection gate, the bit line, and the source line are set to 20V with respect to the high voltage applied to the p-type well. By this, the selected NA
In all the memory cells in the ND cell, the electrons in the charge storage layer are p
Emitted into the mold well and the threshold shifts in the negative direction.
All control gates of the memory cells in the NAND cell that are not erased are set to 20V.

For data reading, the control gate of the selected memory cell is set to 0V, the control gates and selection gates of the other memory cells are set to the power supply voltage Vcc (for example, 5V), and whether or not a current flows in the selection transistor is determined. It is done by detecting.

In such a NAND cell type EEPROM, writing / reading is several bytes (up to 512 bytes).
In order to perform simultaneously, a data latch / sense amplifier circuit is provided for each bit line.

However, as the degree of integration is increased, the pitch of the bit lines becomes narrower, and it becomes difficult to arrange the data latch / sense amplifier circuit for each bit line, and one data latch / sense for two bit lines. An amplifier circuit will be provided. This is because the wiring layer and the contact holes can be processed with a regular shape in the memory cell array, but the processing is difficult in the atypical shape portion such as in the peripheral circuit. However, the bit line selection transistor for selecting the bit line and connecting it to the data latch / sense amplifier circuit must be provided for each bit line, which is difficult to process.

Further, since a high voltage of about 20 V is applied to the p-type well for erasing, the bit line is also set to about 20 V via the n-type diffusion layer formed on the surface of the p-type well. The selection transistor must be a high breakdown voltage transistor that can withstand a high voltage of about 20V. This high breakdown voltage transistor has a problem that the transistor size is large such that the gate length is long in order to increase the punch-through breakdown voltage, and the circuit area is increased.

[0010]

As described above, the conventional N
In the AND cell type EEPROM, a bit line selection transistor which must be provided for each bit line even if one data latch / sense amplifier is provided for two bit lines to loosen the minimum processing size in the peripheral circuit. In the processing area of, there was a problem that the minimum processing size could not be loosened. Further, a high breakdown voltage transistor must be provided for each bit line, which causes a problem of increasing the circuit area.

The present invention has been made in consideration of the above circumstances. An object of the present invention is to facilitate processing of a bit line selection transistor and contribute to improvement of reliability of the bit line selection transistor. It is to provide a semiconductor memory device that can be realized.

Another object of the present invention is to provide a semiconductor memory device capable of reducing the number of high breakdown voltage transistors conventionally required for each bit line and reducing the circuit area. To do.

[0013]

A NAND according to the present invention
In the cell-type EEPROM, the bit line selection transistors are made to be almost the same as the selection transistors so as not to disturb the regular shape of the memory cell array and are arranged adjacent to the array. The bit line selection transistor is formed in the p-type well in which the memory cell array is formed. In other words, the select transistor in the memory cell array is cut out and arranged at the end of the memory cell array, and is used as the bit line select transistor. A plurality of bit lines are put together into one signal line through the bit line selection transistor and wired to the peripheral circuit. The gate of the bit line selection transistor as well as the selection transistor is set to 2 during erase.
About 0V is applied.

That is, the present invention (claim 1) is a memory cell comprising a sub-array composed of one or a plurality of memory cells and a selection transistor for selectively connecting the sub-array to a bit line. A unit, a memory cell array arranged in a matrix, and a selected bit signal line provided for each of a plurality of bit lines,
In a semiconductor memory device provided with a bit line selection transistor provided adjacent to a memory cell unit at the same end of the bit line for selectively connecting a plurality of bit lines to a selected bit signal line, bit line selection It is characterized in that the transistor is formed in substantially the same shape as the selection transistor, and the selection transistor is arranged at a position parallel to the bit line direction.

According to the present invention (claim 2), a selective memory comprising a sub-array composed of one or a plurality of memory cells and a selection transistor for selectively connecting the sub-array to a bit line. The cell unit is provided in a memory cell array arranged in a matrix, a first selected bit signal line provided for each of the plurality of bit lines, and one provided for each of the plurality of bit lines. In order to selectively connect the second selected bit signal line and the plurality of bit lines to the first selected bit signal line, the first selected bit signal line is provided adjacent to the memory cell unit at the same end of the bit line. Since the bit line selection transistor and the plurality of bit lines are selectively connected to the second selected bit signal line, the first
A bit line selection transistor and a second bit line selection transistor provided adjacent to the memory cell unit at the same end of the bit line selection transistor opposite to the first bit line selection transistor Is formed in substantially the same shape as the selection transistor, and the selection transistor is arranged in a position parallel to the bit line direction.

Here, the following are preferred embodiments of the present invention. (1) Select transistors and bit line select transistors must be formed at the same time. (2) Select transistor and bit line select transistor
The cross section in the direction perpendicular to the bit line should be formed to have almost the same shape. (3) The memory cell is a memory cell in which a charge storage layer and a control gate are stacked on an insulating film and electrically rewritable. A plurality of memory cells are connected in series to form a NAN.
Constituting a D cell.

Further, the present invention (claim 3) is a memory cell comprising a sub-array composed of one or a plurality of memory cells and a selection transistor for selectively connecting the sub-array to a bit line. A unit, a memory cell array arranged in a matrix, and a selected bit signal line provided for each of a plurality of bit lines,
To selectively connect a plurality of bit lines to the selected bit signal line, a bit line selection transistor provided adjacent to the memory cell unit at the same end of the bit line and a bit line connected to the selected bit signal line In the semiconductor memory device including a control circuit, the memory cell array and the bit line selection transistor are formed on the first semiconductor layer, and the bit line control circuit is formed on the second semiconductor layer.

Further, the present invention (claim 4) is a memory cell comprising a sub-array composed of one or a plurality of memory cells and a selection transistor for selectively connecting the sub-array to a bit line. The unit includes a memory cell array arranged in a matrix, a first selection bit signal line provided for each of the plurality of bit lines, and one unit provided for each of the plurality of bit lines. The first bit provided adjacent to the memory cell unit at the same end of the bit line for selectively connecting the second selected bit signal line and the plurality of bit lines to the first selected bit signal line Since the line select transistor and the plurality of bit lines are selectively connected to the second select bit signal line, the memory cell unit is provided at the same end of the bit line opposite to the first bit line select transistor. A second bit line selection transistor provided adjacently, a first bit line control circuit connected to the first selection bit signal line, and a second bit connected to the second selection bit signal line. In a semiconductor memory device including a line control circuit, a memory cell array, first and second
Forming a bit line selection transistor on the first semiconductor layer, forming a first bit line control circuit on the second semiconductor layer, and forming a second bit line control circuit on the third semiconductor layer. It is characterized by having done.

Here, the following are preferred embodiments of the present invention. (1) The selection transistor and the bit line selection transistor have almost the same shape, the selection transistor and the bit line selection transistor are formed at the same time, and the bit line selection transistor is arranged at a position where the selection transistor is moved in parallel in the bit line direction. . (2) The cross section of the select transistor and the bit line select transistor in the direction perpendicular to the bit line are almost the same shape, and the select transistor and the bit line select transistor are formed at the same time, and the bit line select transistor moves the select transistor in parallel to the bit line direction. Be placed in the specified position. (3) The second semiconductor layer and the third semiconductor layer are the same semiconductor layer. (4) The memory cell is a memory cell in which a charge storage layer and a control gate are stacked on an insulating film and electrically rewritable. A plurality of memory cells are connected in series to form a NAN.
Constituting a D cell. (5) In order to erase the NAND cell, an erase means is applied to the first semiconductor layer, and erase means for controlling the gate electrodes of the select transistor and the bit line select transistor so that the potential difference from the erase voltage is sufficiently small. Be prepared.

Further, the present invention (claim 5) is a memory comprising a sub-array composed of one or a plurality of memory cells and a selection transistor for selectively connecting the sub-array to a bit line. A cell unit has a memory cell array arranged in a matrix, a selected bit signal line provided for each of a plurality of bit lines, and a plurality of bit lines are selectively connected to the selected bit signal line. Therefore, in a semiconductor memory device having a bit line selection transistor provided adjacent to a memory cell unit at the same end of a bit line, the bit line selection transistor is a low breakdown voltage bit line selection transistor provided for each bit line. And a plurality of low withstand voltage bit line selection transistors and a selected bit signal line are connected to each other, one for each selected bit signal line. Vignetting is constituted by a high-voltage bit line select transistor, to form a low-voltage bit line select transistor in the same first semiconductor layer and the memory cell array,
A high breakdown voltage bit line select transistor is formed on the second semiconductor layer.

Here, the following are preferred embodiments of the present invention. (1) The select transistor and the low withstand voltage bit line select transistor have almost the same shape, and the select transistor and the low withstand voltage bit line select transistor are formed at the same time, and the low withstand voltage bit line select transistor is obtained by moving the select transistor in parallel in the bit line direction. Be placed in position. (2) The cross section of the select transistor and the low withstand voltage bit line select transistor in the direction perpendicular to the bit line have almost the same shape.
In addition, the select transistor and the low withstand voltage bit line select transistor are formed at the same time, and the low withstand voltage bit line select transistor is arranged at a position where the select transistor is moved in parallel in the bit line direction. (3) The memory cell is a memory cell in which a charge storage layer and a control gate are stacked on an insulating film and electrically rewritable. A plurality of memory cells are connected in series to form a NAN.
Constituting a D cell. (5) In order to erase the NAND cell, an erase means is applied to the first semiconductor layer, and erase means for controlling the gate electrodes of the select transistor and the bit line select transistor so that the potential difference from the erase voltage is sufficiently small. Be prepared.

[0022]

According to the present invention, the bit line select transistor is formed by the select transistor in the memory cell array, so that the bit line select transistor can be processed while maintaining the regular shape of the memory cell array. This means that if the select transistor can be processed, the bit line select transistor can be automatically processed, and therefore the difficulty of processing the bit line select transistor can be avoided.

By arranging the bit line selection transistors in the memory cell array, the number of signal lines arranged in the peripheral circuit region from the memory cell array region is reduced, and the number of high breakdown voltage transistors provided in the peripheral circuit region is reduced. You can This leads to a reduction in circuit area.

[0024]

First, the basic structure of the present invention will be described before describing the embodiments. FIG. 1 shows a NAN according to the present invention.
It is a figure which shows the equivalent circuit of the memory cell part of D cell type EEPROM.

The four memory cells M1 to M4 are connected in series and connected to the bit line BL via the selection transistor S1. Further, it is connected to the source line via the selection transistor S2. The memory cells sharing the control gates CG (CG1 to 4) form a page, and four pages form one block. This memory cell is called a NAND type memory cell, and includes select transistors S1 and S2 and a memory cell M1.
4 to form a NAND cell type memory cell unit (NAND cell unit).

FIG. 2 is a plan view showing the structure of the memory cell array. The bit line BL is formed of the wiring layer 1 (for example, aluminum), and is wired substantially linearly in parallel with each other. The bit line BL is connected to the NAND cell unit connected to the n-type diffusion layer 4 through the contact hole 5.

The control gate CG is formed of the wiring layer 2 (for example, polysilicon), and is wired substantially at right angles to the bit lines and parallel to each other. The floating gate FG is formed of the wiring layer 3 (for example, polysilicon) and processed in a self-aligned manner with the control gate CG. The select gate SG has a laminated structure of the wiring layers 2 and 3, and is wired in parallel with the control gate CG, and the wiring layers 2 and 3 are connected to each other in the memory cell array.

FIGS. 3 and 4A and 4B are sectional views taken along the lines X-X ', Z-Z' and Y-Y 'of FIG. 2, respectively.
The floating gate FG and the control gate CG are stacked on the p-type well 9 formed in the n-type substrate 10, and the memory cell M is formed using the n-type diffusion layer 4 as a source / drain. The p-type well 9 and the floating gate FG are the tunnel insulating film 1
Insulated at 1. The floating gate FG and the control gate CG are insulated by the inter-gate insulating film 7. The selection transistor S is formed on the p-type well 9 with a selection gate SG having a laminated structure of wiring layers 2 and 3 and an n-type diffusion layer 4 serving as a source / drain. In the selection transistor S,
The p-type well 9 and the select gate SG are insulated by the select gate insulating film 6. Further, the element isolation film 8 separates the adjacent NAND cell units.

The element isolation film 13 separates the memory cell array region from the peripheral circuit region formed on the p-type well 12. In the transistor of the peripheral circuit, the wiring layer 2 formed on the peripheral gate insulating film 16 on the p-type well 12 is used as a gate electrode, the thin n-type diffusion layer 14 and the thick n-type diffusion layer 15 formed therein. Are formed as source / drain.

In the memory cell array, p under the wiring layer 1 is used.
The thickness from the mold well 9 is almost constant. Element isolation film 1
The thickness up to the wiring layer 1 above 3 is smaller than that of the memory cell array. This is because the wiring layers 2 and 3 are not provided between the element isolation film 13 and the wiring layer 1. In such a case, the exposure conditions do not match in the photo-etching process when forming the wiring layer 1 and the wiring layer can be processed on the memory cell array with the minimum processing size, but cannot be processed on the element isolation film 13. There is.

Erasing / deleting this NAND cell type EEPROM
The write / read operation will be described with reference to FIG. Data is erased simultaneously for the memory cells M1 to M4. Erase voltage Verase (~ 20
V), and the control gate CG1 of the selected block
~ 4 is set to 0V. Control gate CG1 of unselected block
Set to 4 for Verase. The bit line BL and the source line are floated. The forward current of the pn junction of the bit line and the source line is almost Verase. Select gate SG
Is set to Verase so that no voltage stress is applied to the select gate insulating film 6. By the erase operation, the potential of the floating gate FG shifts in the positive direction by the tunnel current flowing through the tunnel insulating film 11, the threshold value of the memory cell becomes negative, and the data of the memory cell becomes "1".

At the time of erasing, since the bit line becomes Verase,
Since the n-channel MOS transistors Qn2 to Qn5 connecting the bit line and the circuit controlling the bit line are turned off, the bit line selection signals ENBU1, ENBU2, ENB are set.
D1 and ENBD2 are set to 0V.

At the time of writing, the control voltage CG (for example, CG2) of the selected memory cell is set to the write voltage Vprog.
(Up to 20 V) and other control gates CG1, 3, 4
And select gate SG1 is Vm (~ 10V), select gate S
G2 is 0V. When writing "0", the bit line is 0V, and when writing "1", the bit line is Vmb.
(~ 8V).

In the case of writing "0", the floating gate FG
Potential shifts in the negative direction by the tunnel current flowing through the tunnel insulating film 11, the threshold value of the memory cell becomes positive, and the data of the memory cell becomes "0". In the case of writing “1”, the charge does not move through the tunnel insulating film 11, so that the “1” state is maintained.

At the time of writing when the bit line connected to Qn4 is selected, the bit line selection signal ENBD1 is V
m, Vmb or 0V is supplied to the bit line from the selected bit line control circuit 17 according to the data, and the bit line selection signal ENBD2 is set to 0V. At this time, since the non-selected bit line control circuit formed by the n-channel MOS transistor Qn1 provided at the other end of the bit line and the non-selected bit line connected to Qn3 are connected, the bit line selection signal ENBU2 becomes Vm. , Bit line selection signal ENBU1
Is 0V. The bit line bias signal BLBS also becomes Vm, and becomes the non-selected bit line voltage V which becomes Vmb during writing.
The UBL is transferred to the unselected bit line, and the data in the unselected memory cell is retained as it was before the write operation.

At the time of reading, when the bit line connected to Qn4 is selected, the bit line selection signal ENBD1 is V
The selected bit line control circuit 17 supplies Vcc to the bit line, then ENBD1 becomes 0V, and the bit line becomes floating. After that, the selected control gate (eg, CG2) is set to 0V, and the other control gates CG1, 3, 4 are set to Vcc (eg, 5V). The selection gates SG1 and SG2 are also set to Vcc. When the data in the memory cell is "0", the threshold value is positive and the bit line is V
It remains cc. If the data in the memory cell is "1",
Since the threshold value is negative, the potential of the bit line drops.

After the bit line potential is determined by the data, the bit line selection signal ENBD1 becomes Vcc again, and the selected bit line control circuit 17 senses the bit line data.

During this read operation, the bit line selection signal E
NBU1 and ENBD2 are set to 0V, ENBU2 is Vcc
It is said. Also, the bit line bias signal BLBS is Vcc
Therefore, the voltage VUBL is 0V. Therefore, the non-selected bit line connected to Qn3 is fixed to 0V during the read operation.

From the above description, the bit line selection transistors Qn2 to Qn5 must be high breakdown voltage transistors because the bit line becomes Verase during the erase operation. However, it is not necessary to use the high breakdown voltage transistor during the read / write operation. The following (Table 1) shows a summary of the potential of each part during each operation.

[0040]

[Table 1]

Examples of the present invention will be described below. (Embodiment 1) FIG. 6 shows the N according to the first embodiment of the present invention.
FIG. 3 is a plan view showing the configurations of a memory cell array and a bit line selection transistor of an AND cell type EEPROM. In addition,
The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The bit line selection transistors Qn4, 5 are p
NA is formed in the memory cell array formed on the mold well 9.
It is formed adjacent to the ND cell unit. Its source /
The drain is formed of the same n-type diffusion layer 4 as the source / drain of the selection transistor S, and the gate electrode thereof is formed of the wiring layer 2. The gate length of the bit line selection transistor is the same as the gate length of the selection transistor. Specifically, the bit line selection transistors Qn4 and Qn are connected to the selection transistor S.
By being formed at the same time, the bit line selection transistors Qn4, 5 are formed in substantially the same shape as the selection transistor S.

The bit line selection signals ENBD1 and ENBD2 are wired in the wiring layer 1. The two bit lines are extracted from the memory cell array as selected bit signal lines by the wiring layer 1 via the bit line selection transistors and wired to the selected bit line control circuit 17 described above. The dimensions of the contact hole are the same in the memory cell array, and the dimensions of the n-type diffusion layer around the contact hole are also the same in the memory cell array.
Only the size of the n-type diffusion layer around the contact hole of the wiring layer 1 serving as a signal line to the peripheral circuit is increased.

As described above, according to the present embodiment, the bit line selection transistors Qn4, 5 are constituted by the selection transistors S in the memory cell array, so that the bit line selection transistors are processed while maintaining the regular shape of the memory cell array. Therefore, it is possible to avoid the difficulty of processing the bit line selection transistor. Further, the number of signal lines wired from the memory cell array region to the peripheral circuits is ½ of the number of bit lines, so that the wiring processing accuracy outside the memory cell array can be relaxed. In addition, the dimensions of each wiring, contact hole, and n-type diffusion layer are the same, and the workability is greatly improved.

The present embodiment can be similarly implemented for the bit line selection transistors Qn2,3. (Embodiment 2) FIG. 7 shows the N according to the second embodiment of the present invention.
FIG. 3 is a plan view showing the configurations of a memory cell array and a bit line selection transistor of an AND cell type EEPROM. In addition,
The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The bit line selection transistors Qn4, 5 are p
NA is formed in the memory cell array formed on the mold well 9.
It is formed adjacent to the ND cell unit. Its source /
The drain is formed of the same n-type diffusion layer 4 as the source / drain of the selection transistor S, and the gate electrode thereof is also formed of the same wiring layers 2 and 3 as the selection transistor S. The gate length and width of the bit line selection transistor are the same as the gate length and width of the selection transistor S. Further, the distance from the contact hole to the gate wired in the wiring layers 2 and 3 as the bit line selection signals ENBD1 and ENBD2 also depends on the selection transistor S1.
Is the same as the distance from the select gate SG1 to the contact hole.

Bit line selection transistors Qn4 and Qn5
The width of the n-type diffusion layer 4 connecting the two is the same as the width of the n-type diffusion layer serving as the source line of the memory cell array. The two bit lines are taken out from the memory cell array as selected bit line signal lines by the wiring layer 1 via the bit line selection transistors and wired to the selected bit line control circuit 17. The dimensions of the contact hole are the same in the memory cell array, and the dimensions of the n-type diffusion layer around the contact hole are also the same in the memory cell array.

Also in this embodiment, by forming the bit line selection transistors Qn4, 5 at the same time as the selection transistor S, the bit line selection transistors Qn4, 5 can be formed in substantially the same shape as the selection transistor S. As can be easily understood from FIG. 7, the bit line selection transistor and the selection transistor have the same sectional shape in the direction orthogonal to the bit line. The gate length of the bit line selection transistor may be increased as necessary. Further, the distance between the gate and the contact hole may be increased if necessary. Further, the size of each part can be appropriately changed so as to have a favorable influence on the processing.

According to the present embodiment, the number of signal lines wired from the memory cell array region to the peripheral circuits is half the number of bit lines, and the wiring processing accuracy outside the memory cell array can be relaxed. Also, each wiring, contact hole, n
The dimensions of the mold diffusion layer are uniform, which facilitates processing. Then, the same effect as that of the first embodiment can be obtained.

The present embodiment can be similarly implemented for the bit line selection transistors Qn2,3. Further, in the present embodiment, the NA adjacent to the bit line selection transistor
The ND cell unit is a dummy unit and is not accessed. (Embodiment 3) FIG. 8 shows the N according to the third embodiment of the present invention.
FIG. 3 is a plan view showing the configurations of a memory cell array and a bit line selection transistor of an AND cell type EEPROM. In addition,
The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is very similar to the second embodiment shown in FIG. 7, but in FIG. 7, the width of the signal line formed in the wiring layer 1 drawn out of the memory cell array and wired is halfway. Has been fattened from. On the other hand, in the embodiment shown in FIG. 8, this wiring is once connected to the wiring layer 2 through the contact hole 5 and then returned to the wiring layer 1 through the contact hole. This is because when the wiring layer 1 is processed with the minimum processing size, it is better that the processing sizes are uniform in consideration of the case where a phase shift mask is used.

FIG. 9 is a diagram showing an equivalent circuit of the memory cell array and the bit line selection transistor shown in FIGS. The embodiments are the same in effective equivalent circuits. The bit line select transistors Qn2-5 are formed on the p-type well 9. Therefore, the n-channel MOS transistor Qn1 is a high breakdown voltage transistor. Further, a high breakdown voltage n-channel MOS transistor Qn6 is newly provided.

Although the memory cell is read / written / erased as described with reference to FIG. 5, (1) the bit line activation signal BLENB is Vcc at the time of reading and Vm at the time of writing, especially in this embodiment. , 0V when erased,
(2) Bit line selection signals ENBD1, ENBD2, ENB
U1 and ENBU2 are set to Verase when erased, (3)
The bit line bias signal BLBS is different in that it is set to 0V at the time of erasing.

Further, a high breakdown voltage MOS transistor Qn6 is newly required, but since Qn4 and 5 are required to have a low breakdown voltage, the number of transistors is increased, but the circuit area for forming these transistors Qn4, 5 and 6 is increased. Can be reduced as compared with the conventional one. (Embodiment 4) FIG. 10 is a plan view showing configurations of a memory cell array and a bit line selection transistor of a NAND cell type EEPROM according to a fourth embodiment of the present invention. The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The bit line selection transistors are Qn4, 5
And n channel D type MOS transistors QD3 and Q4, which are formed adjacent to the NAND cell unit in the memory cell array formed on the p type well 9. The source / drain is formed of the same n-type diffusion layer 4 as the source / drain of the selection transistor S, and the gate electrode thereof is also formed of the same wiring layers 2 and 3 as the selection transistor S.

The gate length and width of these bit line select transistors are the same as the gate length and width of the select transistor S. Further, the distance from the contact hole to the gate wired in the wiring layers 2 and 3 as the bit line selection signals ENBD1 and 2 is also the selection gate S of the selection transistor S1.
It is the same as the distance from G1 to the contact hole. The width of the n-type diffusion layer 4 connecting the bit line selection transistors Qn4 and Qn5 is the same as the width of the n-type diffusion layer serving as the source line of the memory cell array.

The two bit lines are taken out from the memory cell array as selected bit signal lines by the wiring layer 1 via the bit line selection transistors and selected bit line control circuit 1
Wired to 7. The dimensions of the contact hole are the same in the memory cell array, and the dimensions of the n-type diffusion layer around the contact hole are also the same in the memory cell array. Only the size of the n-type diffusion layer around the contact hole of the wiring layer 1 serving as a signal line to the peripheral circuit is increased.

As can be easily seen from FIG. 10, the bit line selection transistor and the selection transistor have the same sectional shape in the direction perpendicular to the bit line. The gate length of the bit line selection transistor may be increased as necessary. Further, the distance between the gate and the contact hole may be increased if necessary.
Further, the size of each part can be appropriately changed so as to have a good influence on the processing.

In this embodiment, the bit line selection transistor Q
The same can be applied to n2,3 and QD1,2. According to this embodiment, the number of signal lines wired from the memory cell array region to the peripheral circuit is half the number of bit lines, and the wiring processing accuracy outside the memory cell array can be relaxed. In addition, the dimensions of each wiring, contact hole, and n-type diffusion layer are the same, which facilitates processing.

FIG. 11 is a diagram showing an equivalent circuit of the memory cell array and the bit line selection transistor shown in FIG. The difference from the equivalent circuit of FIG. 9 is that the n-channel MOS transistor Qn2 is used as the bit line selection transistor.
N-channel D type MOS in series with 3, 4 and 5, respectively
This is the point where the transistors QD1, 2, 3, 4 are connected. The thresholds of QD1 to 4 are sufficiently low, and the bit line voltage Vmb at the time of writing "1" can be transferred even if the gate voltage is 0V. As a result, the QDs 1 to 4 can be effectively regarded as resistors in terms of circuit operation.
If 1 to 4 are omitted, the circuit becomes the same as the equivalent circuit in FIG. 9 and the operation is the same.

Bit line select transistors Qn2-5 and Qn
D1 to D4 are formed on the p-type well 9. Therefore, n
Only the channel MOS transistors Qn1 and 6 are high breakdown voltage transistors.

The present invention is not limited to the above embodiments. In the embodiment, the two bit lines are bundled into one signal line by the bit line selection transistor, but the same effect can be obtained when the arbitrary plural bit lines are bundled into one signal line. Further, although an example is shown in which the memory cell array is formed in the p-type well 9 and the peripheral circuit is formed in the p-type well 12, a semiconductor in which the memory cell array is formed regardless of the p-type or n-type, the well, or the substrate. The same effect can be obtained when the layer and the semiconductor layer in which the peripheral circuit is formed are different.

According to the present invention, a bit line select transistor which is a part of the peripheral circuit is formed as a part of the memory cell array adjacent to the memory cell with the same transistor as the select transistor in the memory cell array, and the bit line select transistor is led out to the peripheral circuit. The number of wirings to be formed can be reduced, and the processing of wirings can be facilitated. This is D regardless of EEPROM
The same operation can be performed in various semiconductor memory devices such as RAM, SRAM, EPROM, and ROM.

When the potential of the well or substrate in which the memory cell array is formed is different from that of the well or substrate in which the peripheral circuit is formed in operation, the bit line selection transistor is formed on the well or substrate in which the memory cell array is formed. Therefore, the number of special transistors due to the potential difference can be reduced. This is D regardless of EEPROM
Similar effects can be obtained with various semiconductor memory devices such as RAM, SRAM, EPROM, and ROM. In addition, various modifications can be made without departing from the scope of the present invention.

[0065]

As described above, according to the present invention, the bit line select transistor which is the same transistor as the select transistor in the memory cell array and is a part of the peripheral circuit as a part of the memory cell array adjacent to the memory cell. By forming the wiring, it is possible to reduce the number of wirings drawn to the peripheral circuit and facilitate the processing of wirings and the like.

When the potential of the well or substrate in which the memory cell array is formed is different from that of the well or substrate in which the peripheral circuit is formed in operation, the bit line selection transistor is formed on the well or substrate in which the memory cell array is formed. Therefore, the number of special transistors (high breakdown voltage transistors) associated with the potential difference can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an equivalent circuit of a memory cell portion of a NAND cell type EEPROM according to the present invention.

FIG. 2 is a plan view showing the structure of a memory cell array using NAND cell units.

FIG. 3 is a diagram showing a cross section taken along the line XX ′ of FIG. 2;

FIG. 4 is a diagram showing a cross section taken along line YY ′ and ZZ ′ of FIG. 2;

FIG. 5 is a diagram showing an equivalent circuit of a memory cell array and a bit line control circuit according to the present invention.

FIG. 6 is a NAND cell type EEPR according to the first embodiment.
FIG. 3 is a plan view showing the configurations of an OM memory cell array and bit line selection transistors.

FIG. 7 is a NAND cell type EEPR according to a second embodiment.
FIG. 3 is a plan view showing the configurations of an OM memory cell array and bit line selection transistors.

FIG. 8 is a NAND cell type EEPR according to a third embodiment.
FIG. 3 is a plan view showing the configurations of an OM memory cell array and bit line selection transistors.

FIG. 9 is a diagram showing an equivalent circuit of a memory cell array and a bit line selection transistor in the first to third embodiments.

FIG. 10 is a NAND cell type EEP according to a fourth embodiment.
FIG. 3 is a plan view showing a memory cell array of a ROM and a bit line selection transistor configuration.

FIG. 11 is a diagram showing an equivalent circuit of a memory cell array and a bit line control circuit in the fourth embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Wiring layer 2 ... Wiring layer 3 ... Wiring layer 4 ... N-type diffusion layer 5 ... Contact hole 6 ... Select gate insulating film 7 ... Inter-gate insulating film 8 ... Memory cell array part element isolation film 9 ... P-type well 10 ... N Type substrate 11 ... Tunnel insulating film 12 ... P type well 13 ... Element isolation film 14 ... Low concentration n type diffusion layer 15 ... High concentration n type diffusion layer 16 ... Peripheral gate insulating film 17 ... Select bit line control circuit FG ... Floating gate CG ... Control gate SG ... Selection gate BL ... Bit line M ... Memory cell S ... Selection transistor Qn ... N-channel MOS transistor QD ... N-channel D type MOS transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication H01L 21/8247 29/788 29/792 H01L 29/78 371

Claims (5)

[Claims] 1. A memory cell unit composed of a sub-array composed of one or a plurality of memory cells and a selection transistor for selectively connecting the sub-array to a bit line is arranged in a matrix. The memory cell array, the selected bit signal line provided for each of the plurality of bit lines, and the plurality of bit lines are selectively connected to the selected bit signal line. A bit line select transistor provided adjacent to the memory cell unit, wherein the bit line select transistor is formed in substantially the same shape as the select transistor, and is located at a position where the select transistor is translated in the bit line direction. A semiconductor memory device characterized by being arranged. 2. A sub-array composed of one or a plurality of memory cells and a selected memory cell unit composed of a selection transistor for selectively connecting the sub-array to a bit line are arranged in a matrix. A memory cell array, a first selection bit signal line provided for each of the plurality of bit lines, and a second selection bit signal line provided for each of the plurality of bit lines. A first bit line selection transistor provided adjacent to the memory cell unit at the same end of the bit line for selectively connecting the plurality of bit lines to the first selected bit signal line; This bit line is selectively connected to the second selected bit signal line, so that it is provided adjacent to the memory cell unit at the same end of the bit line opposite to the first bit line selection transistor. And a second bit line selection transistor formed in the same manner, wherein the first and second bit line selection transistors are formed in substantially the same shape as the selection transistor, and the selection transistor is located at a position parallel to the bit line direction. A semiconductor memory device characterized by being arranged. 3. A memory cell unit composed of a sub-array composed of one or a plurality of memory cells and a selection transistor for selectively connecting the sub-array to a bit line comprises a first semiconductor layer. A memory cell array arranged in a matrix above, a selection bit signal line provided for each of a plurality of bit lines, and the plurality of bit lines are selectively connected to the selection bit signal line. Therefore, the bit line selection transistor is provided on the first semiconductor layer adjacent to the memory cell unit at the same end of the bit line, and is connected to the selected bit signal line and is formed on the second semiconductor layer. A semiconductor memory device comprising a bit line control circuit. 4. A memory cell unit composed of a sub-array composed of one or a plurality of memory cells and a selection transistor for selectively connecting the sub-array to a bit line comprises a first semiconductor layer. A memory cell array arranged in a matrix above, a first selection bit signal line provided for each of the plurality of bit lines, and a first selection bit signal line provided for each of the plurality of bit lines. The second selected bit signal line and the plurality of bit lines are selectively connected to the first selected bit signal line, so that the same end of the bit line is adjacent to the memory cell unit and is formed on the first semiconductor layer. The first bit line selection transistor provided and the same end of the bit line opposite to the first bit line selection transistor for selectively connecting the plurality of bit lines to the second selection bit signal line. A second bit line select transistor provided on the first semiconductor layer adjacent to the memory cell unit, and a first bit line select transistor connected to the first select bit signal line and formed on the second semiconductor layer. And a second bit line control circuit connected to the second selected bit signal line and formed on the third semiconductor layer. 5. A memory cell unit composed of a sub-array composed of one or a plurality of memory cells and a selection transistor for selectively connecting the sub-array to a bit line comprises a first semiconductor layer. A memory cell array arranged in a matrix above, a selection bit signal line provided for each of a plurality of bit lines, and the plurality of bit lines are selectively connected to the selection bit signal line. Therefore, a low withstand voltage bit line select transistor provided on the first semiconductor layer at the same end of the bit line adjacent to the memory cell unit and provided for each of a plurality of bit lines, and the plurality of low withstand voltage transistors. In order to connect the bit line select transistor and the selected bit signal line, the bit line select transistor is provided adjacent to the low breakdown voltage bit line select transistor on the second semiconductor layer,
A semiconductor memory device comprising a high breakdown voltage bit line selection transistor provided for each selected bit signal line.