JPH0845946A - Thermal treatment method and device of silicon semiconductor single crystal substrate and semiconductor device - Google Patents

Abstract

PURPOSE:To protect a silicon wafer large in diameter and thickness against crystal defects induced at a thermal treatment of high temperature and to keep a diffusion layer uniform in quality. CONSTITUTION:A silicon wafer is thermally treated through such a manner that it is set small in a temperature rising rate at high temperatures so as to have such a temperature distribution that a thermal stress applied to it is prevented from causing an elastic deformation to it and large in a temperature rising rate in a range of low temperatures so as to make a diffusion layer uniform in quality. By this setup, process-induced defects such as slip lines, etch pits, or the like are prevented from occurring in a thermal treatment carried out at high temperatures, and a diffusion layer is kept uniform in quality.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for heat treating a silicon semiconductor single crystal substrate (hereinafter referred to as a silicon wafer) and a semiconductor device, and is particularly suitable for high temperature heat treatment of a large diameter and thick single crystal substrate. The present invention also relates to a method for heat treating a silicon wafer and its apparatus, and a semiconductor device manufactured by using the method.

[0002]

2. Description of the Related Art In a semiconductor device manufacturing process, a silicon wafer is subjected to various heat treatments. In this heat treatment step, the heat treatment does not impair the uniformity of the composition (dopant concentration). It is also necessary to prevent crystal defects such as slip lines and oxidation-induced defects (OSF) from occurring. As a conventional technique for this purpose, when roughly classified, there are the following three systems. (1) Heat treatment process, particularly for temperature control of temperature increase to and decrease from a predetermined temperature (JP-A-49-
67566, JP-A-49-53763, etc.). (2) Those in which a semiconductor substrate is subjected to special processing to prevent the occurrence of defects (Japanese Patent Publication Nos. 49-12512 and 49-28)
271, Japanese Patent Publication No. 54-2064, Japanese Patent Laid-Open No. 49-4957.
6, JP-A-62-143432, etc.). (3) Heat treatment apparatus for semiconductor substrate, especially for improvement of shape and material of wafer holding jig (Japanese Patent Laid-Open No. 48-66)
76, Actual Development Sho 49-17158, Actual Development Sho 49-7335
4, actual development Sho 49-59464, actual development Sho 49-5826
5, JP-A-4-304652, JP-A-4-88656,
JP-A-5-129214, JP-A-5-114645, and JP-A-5-152228).

[0003]

Recently, a large-diameter substrate (diameter of 150 mm or more) is used in a silicon semiconductor process, and further, in a power device for high withstand voltage and large current,
The thickness of the silicon wafer is 1.5 mm or more and the weight is 60 g.
There are more than that. In the process of such a high breakdown voltage power device, heat treatment is performed at high temperature for a long time in order to form a deep diffusion layer. Further, the process time can be shortened by increasing the temperature of the heat treatment.

In the case of such a large-diameter and thick substrate, the heat treatment control method of slowly changing the temperature at the time of putting in and out of the furnace as shown in, for example, Japanese Patent Application Laid-Open No. 49-67566 has a sufficient effect. Can't get In particular, there is a problem that a temperature distribution is generated in the silicon wafer during the temperature rise, stress more than elastic deformation is generated, and a slip line is generated in the crystal due to the weight of the silicon wafer. It is difficult to prevent the occurrence of process-induced defects. Further, in the high-temperature heat treatment of a large-diameter substrate, the expansion of the diameter due to thermal expansion becomes large, and the matching of the size of the wafer and the jig (dimensional tolerance, uniformity) becomes severe.

An object of the present invention is to provide a silicon wafer heat treatment method and apparatus capable of preventing the occurrence of crystal defects during high temperature heat treatment of a large-diameter thick silicon wafer and ensuring a uniform distribution of dopant such as diffusion. And a semiconductor device manufactured by using the method.

[0006]

According to the present invention, the temperature for heat-treating a silicon semiconductor single crystal substrate can be maintained such that the thermal stress in the silicon semiconductor single crystal substrate does not cause elastic deformation. Disclosed is a heat treatment method for a silicon semiconductor single crystal substrate, which is controlled so that the temperature rising rate becomes smaller as the temperature becomes higher. Also, the present invention
2. While the temperature of the heat treatment is low, a higher heating rate is set within a range of a heating rate capable of maintaining a temperature distribution such that the thermal stress does not cause elastic deformation. Discloses a method for heat treating a silicon semiconductor single crystal substrate.

[0007]

The yield stress at which a silicon single crystal changes from elastic deformation to plastic deformation is smaller at higher temperatures, and sharply decreases above 750 ° C. In particular, this tendency is remarkable in a silicon single crystal produced by the floating zone method (FZ method) in which the oxygen content in the crystal is small. Therefore, by slowing the temperature raising / lowering rate, the entire silicon wafer can be held in a thermal equilibrium state, the thermal stress distribution in the silicon single crystal substrate can be reduced, and the occurrence of crystal defects can be prevented. Further, at a relatively low temperature, even if the temperature rising rate is large and the temperature distribution is generated in the silicon wafer, the yield stress is large, so that the silicon wafer remains elastically deformed and the occurrence of crystal defects can be prevented. Further, by increasing the temperature rising rate of the low temperature portion, the time of low temperature where the segregation coefficient is large can be shortened, and the dispersion of the dopant concentration of the diffusion layer can be reduced.

[0008]

EXAMPLES The present invention will be described in detail below with reference to examples. First, an experiment conducted to improve a heat treatment method for diffusion of a large-diameter and thick silicon wafer will be described.
FIG. 2 shows a heat treatment furnace (diffusion furnace) for a silicon substrate. The diffusion furnace 10 is a horizontal type, and a wafer holder 13 is installed in a quartz process tube 11. The wafer holder 13 is made of silicon carbide, and 50 silicon wafers 12 can be set at a wafer pitch of 5 mm. However, although the two wafers on each end of the wafer holder are the same silicon wafers 12 as the others, they also serve as buffers for heat shielding and so are excluded from the evaluation targets in the following experiments. The soaking length of the furnace is 800 mm, and the temperature uniformity is ± 0.5 ° C. The heat treatment was held for 60 minutes in a nitrogen stream. The nitrogen atmosphere is for preventing the generation of stress due to the formation of the oxide film.

The silicon wafer 12 has a diameter of 150 mm and a thickness of 1.60 mm and is manufactured by the floating zone method.
This is a wafer that is mirror-finished and chamfered. Aluminum dosed 5 × 10 ¹⁵ / c by ion implantation
It is driven with m ² and energy of 100 keV. No mask such as a silicon oxide film is used.

FIG. 3 shows the experimental results of the rate of temperature rise up to each heat treatment temperature and the defect occurrence state of the silicon single crystal substrate 12. Crystal defects were observed by X-ray topography and selective etching. In the figure, ○ marks indicate that no crystal defects were found, and ● marks indicate that crystal defects such as slip lines and etch pits were found. From this result, the following can be understood. (1) In the heat treatment at 750 ° C. or less, even if the wafer is heated at the maximum temperature rising rate of 20 ° C./min or a wafer is rapidly inserted into the furnace set to a predetermined temperature, crystal defects No occurrence is seen. (2) In heat treatment up to 1100 ° C, 4.0 ° C /
Occurrence of crystal defects may be observed at the temperature rising rate of min, which is unstable. Crystal defects (slip lines) are generated from the peripheral portion of the wafer, particularly from the holder contact portion of the silicon wafer toward the center. The occurrence of crystal defects can be prevented at a temperature rising rate of 3.5 ° C./min or less. (3) In the heat treatment up to 1150 ° C, as in the above case, the temperature rising rate of 3.0 ° C / min is unstable at the critical point, and the temperature rising rate of 2.5 ° C / min or less Generation of crystal defects can be prevented. (4) In the heat treatment up to 1250 ° C, as in the above case, the temperature rising rate of 1.5 ° C / min is unstable at the critical point, and the temperature rising rate of 1.0 ° C / min or less Generation of crystal defects can be prevented. It was also clarified that the above results hardly depend on the diffusion time.

FIG. 4 shows the experimental results of the heating rate up to each heat treatment temperature and the sheet resistance distribution of the aluminum diffusion layer of the silicon single crystal substrate 12. The sheet resistance of the diffusion layer was measured at 25 points on the wafer by the four-point probe method. The numbers in the figure indicate variations in sheet resistance within the wafer. From this experiment, it can be seen that at any heat treatment temperature, the slower the heating rate is, the larger the sheet resistance, that is, the variation in the diffusion layer within the wafer, is particularly remarkable when the heat treatment temperature is low. This is because the segregation coefficient of the dopant is large at a relatively low temperature of 900 to 1000 ° C. or less, and if it is kept at a low temperature for a long time, the dopant diffuses outward and forms an oxide film due to a slight amount of oxygen in the atmosphere. It is considered that the variation due to the redistribution of is significant. In order to prevent this, it is necessary to shorten the processing time in the relatively low temperature process, and it is effective to increase the temperature rising rate.

From the above experimental results, it has been found that the following conditions are suitable in consideration of various heat treatment conditions in which the sheet resistance variation within the wafer is small and the above-mentioned conditions for preventing the occurrence of crystal defects. It was From room temperature to 750 ° C, raise the temperature as fast as possible at least 1.5 ° C / min or more. At 750 to 950 ° C, raise the temperature at a rate in the range of 1.5 to 3.5 ° C / min 950 to 1100 ° C. Then, raise the temperature at a rate of 3.5 ° C / min or less. At 1100 to 1150 ° C, raise the temperature at a rate of 2.5 ° C / min or less. At 1150 to 1250 ° C, at a rate of 1.0 ° C / min or less. Raise the temperature

FIG. 1 shows an embodiment of a heat treatment method in consideration of the above conditions. The above conditions (added in the drawing)
While satisfying the above condition, the control method is such that the temperature rising rate decreases as the temperature rises.

With respect to the pn junction and the pnp junction produced by the heat treatment method of this embodiment, a breakdown voltage of 6 to 9 kV was obtained after processing the end portion with a pellet having a diameter of 136 mm. The breakdown voltage is determined by the resistivity and thickness of the silicon wafer. Such high breakdown voltage devices are used in the manufacturing process of thyristors used for high voltage DC power transmission, frequency converters, power converters such as reactive power compensators, and gate turn-off thyristors used for inverters of large capacity rolling mills and vehicles. Applicable.

Next, a heat treatment experiment for forming an oxide film on a silicon wafer will be described. This is because a silicon oxide film (SiO2) is formed on the surface of the silicon wafer to serve as a diffusion mask of phosphorus or boron. The temperature of the experiment was 1150 ° C., the atmosphere was a steam flow of oxygen combustion of hydrogen, and the oxidation time was 100 min, and an oxide film of about 1 μm was formed.

According to this experiment, in the temperature rising process up to 1150 ° C., after first inserting into the furnace set at 750 ° C.,
It became clear that it is preferable to raise the temperature to 00 ° C. at 3.0 / min and then to 1150 ° C. at 1.0 ° C./min. When the temperature is raised to 1150 ° C at 3.0 ° C / min after being inserted into the furnace set at 750 ° C, not only slip lines are generated but also oxidation-induced defects (OSF: Oxidation-induced Stacking Faults) Although 10 ³ were generated, the occurrence of slip lines on the crystal substrate could be completely prevented under the above conditions.
Oxidation-induced defects whose generation peaks at about 10 ^{6 due to} oxidation in the vicinity could be reduced to about 10 ² by oxidation at 1150 ° C. In addition, the pnp junction created by the method of FIG.
When oxidized by the above-mentioned oxide film forming method, deterioration of breakdown voltage of the pn junction and increase of leak current were not observed.

[0017]

According to the present invention, it is possible to prevent the generation of crystal defects during high-temperature heat treatment of a large-diameter thick silicon wafer and to ensure the uniformity of diffusion. Therefore, there is an effect that it is possible to prevent the characteristic defect of the element, particularly the power device, and the reduction of the yield.

[Brief description of drawings]

FIG. 1 is a temperature profile showing an example of a heat treatment method according to the present invention.

FIG. 2 is a diagram showing a configuration of a silicon wafer heat treatment apparatus.

FIG. 3 is a diagram showing an experimental result of a generation state of crystal defects of a silicon wafer due to heat treatment.

FIG. 4 is a diagram showing an experimental result of variations in sheet resistance of a silicon wafer diffusion layer due to heat treatment.

[Explanation of symbols]

 10 Diffusion Furnace 11 Quartz Process Tube 12 Silicon Single Crystal Substrate 13 Wafer Holder

Claims (6)

[Claims] 1. A temperature rising rate for a heat treatment of a silicon semiconductor single crystal substrate is higher as the temperature is higher so that a temperature distribution in which thermal stress in the silicon semiconductor single crystal substrate does not cause elastic deformation can be maintained. A method for heat-treating a silicon semiconductor single crystal substrate, which is controlled to be small. 2. While the temperature of the heat treatment is low, a higher heating rate is set within a heating rate range capable of maintaining a temperature distribution in which the thermal stress does not cause elastic deformation. The heat treatment method for a silicon semiconductor single crystal substrate according to claim 1. 3. The silicon semiconductor single crystal substrate is a substrate manufactured by a floating zone method and has a temperature rising rate of 3.5 ° C./min from 750 ° C. to 1100 ° C.
2.5 ° C / min from 1100 ° C to 1150 ° C
Below 1.0 ° C / min from 1150 ° C to 1250 ° C
The heat treatment method for a silicon semiconductor single crystal substrate according to claim 1, wherein: 4. The silicon semiconductor single crystal substrate is a substrate manufactured by a floating zone method and has a temperature rising rate of 1.5 ° C./min or more at 950 ° C. or less. 2. The heat treatment method for a silicon semiconductor single crystal substrate according to 2. 5. A semiconductor manufactured by subjecting a silicon semiconductor single crystal substrate manufactured by a floating zone method to a diffusion treatment and an oxide film generation treatment using the heat treatment method according to claim 2. apparatus. 6. The temperature rising rate for the heat treatment of the silicon semiconductor single crystal substrate is higher as the temperature is higher so that the temperature distribution in which the thermal stress in the silicon semiconductor single crystal substrate does not cause elastic deformation can be maintained. The first means for controlling the temperature to be small, and the temperature of the heat treatment, within the range of the temperature rising rate that can maintain the temperature distribution such that the thermal stress does not cause elastic deformation while the temperature is low, 2. A heat treatment apparatus for a silicon semiconductor single crystal substrate, comprising: a second means for controlling so as to have a high temperature rising rate.