JPH0843562A - Crystal oscillation electronic clock - Google Patents

Abstract

PURPOSE:To obtain a crystal oscillation electronic clock in which output voltage can be set to an optimum value by providing a constant-voltage circuit with a reference-voltage device and a differential amplifier whose amplification factor is corrected by a resistance array containing a MOS transistor, and storing control data on an output voltage in a memory block in a writable and erasable nonvolatile memory block. CONSTITUTION:The output voltage of a constant-voltage circuit 6 is generated in such a way that a reference voltage generated by a reference-voltage device 8 is amplified by a differential amplifier 9. The amplification factor of the amplifier 9 can be changed arbitrarily by selecting the resistance of a resistance array 7 which is composed of a plurality of resistances and of a plurality of MOS transistors which are connected in parallel with the respective resistances, and the output voltage can be set between the reference voltage and a power-supply voltage. A memory block 10 is provided with a memory cell array 11 which contains an electrically writable and erasable nonvolatile memory. Then, selection information on the array 7 which contains the output voltage of the circuit 6 which is optimum for clock specifications is stored in the array 11, the MOS transistors for the array 7 are controlled by the information, and the output voltage can be set to an optimum value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a crystal oscillator using a logic circuit of a CMOS (complementary field effect) transistor having means for dividing the frequency of the crystal oscillator to a time display device with the crystal oscillator as a time reference. Formula electronic timepieces,
Particularly, when a battery of a type in which the discharge characteristic of the battery voltage fluctuates from 1.8 V to 1.55 V is used, the present invention relates to a structure of a crystal oscillation type electronic timepiece having a constant voltage circuit capable of eliminating this voltage fluctuation. It is a thing.

[0002]

2. Description of the Related Art A quartz oscillator type electronic timepiece using a logic circuit of a CMOS transistor having means for dividing a frequency of the quartz oscillator to a time display device with a quartz oscillator as a time reference, and a discharge characteristic of a battery voltage. Is 1.8V to 1.55V
Equipped with a constant voltage circuit that can eliminate this voltage fluctuation when using a battery that fluctuates up to
A conventional example of a crystal oscillation type electronic timepiece is shown in a circuit block diagram of FIG.

Conventionally, as shown in FIG. 6, an oscillator 71,
Frequency division unit 72, display drive unit 73, and time display device 74
The constant voltage circuit 76 and the battery 75 constitute a crystal oscillation type electronic timepiece.

The voltage of the battery 75 is converted into a constant voltage of 1.5 V or less by the constant voltage circuit 76, and the oscillator 71
Is added to the frequency dividing section 72 to remove the influence of the voltage fluctuation on the oscillation frequency. On the other hand, the voltage of the battery 75 is applied to the display drive unit 73 as it is.

The circuit operation of the constant voltage circuit 76 in FIG. 6 will be briefly described with reference to the circuit diagram of FIG.

MOS transistors 82, 83, 84, 8
5, 86 and a resistor 81, a reference voltage obtained by a current mirror type reference voltage device is applied to the MOS transistor 8
In addition to the line 80 as the input of the differential amplifier composed of 7, 88, 89, 90, 91, the same voltage value as the reference voltage obtained by the current mirror type reference voltage device is applied to the line 95 as the input of the differential amplifier. I am configuring. That is, the output M is adjusted so that the value of the current flowing through the resistor 94 becomes a constant current.
The gate voltage of the OS transistor 92 is taken out and a constant output voltage is applied between the drain of the output MOS transistor 92 and Vdd.

[0007]

The gain of the reference voltage device depends on the amplification degree of each MOS transistor,
If the gain is increased, the stability is improved, but the current consumption is increased and the battery life is shortened.

Therefore, in order to realize a constant voltage circuit with a current consumption of several tens of nA, it is necessary to increase the resistor 81 as the gain is increased.

However, if the resistance 81 is increased, the reference voltage value decreases. Therefore, the resistance 93 and the resistance 9 reach a voltage value at which the oscillator 71 and the frequency divider 72 shown in FIG. 6 can be driven.
It is necessary to amplify the reference voltage by using 4 and 4 to obtain the output voltage.

As described above, in the crystal oscillation type electronic timepiece, the gain, the resistance 81, the resistance 93 and the resistance 94 must be strictly set in order to set the constant voltage value to the best value.

However, variations in element characteristics due to manufacturing variations in MOS transistors and resistors cause an error in the settings of the gain and the resistor, which must be strictly performed. That is, the output voltage and the current consumption of the constant voltage circuit 76 fluctuate due to manufacturing variations, which deteriorates the timepiece performance and the battery life.

Therefore, an object of the present invention is to solve the above-mentioned problems and to supply a constant voltage which most closely meets the timepiece specifications, thereby extending the life due to low current consumption and using a battery with a large voltage fluctuation. It is an object of the present invention to provide a structure of a crystal oscillation type electronic timepiece having good frequency stability.

[0013]

In order to achieve the above object, the crystal oscillation type electronic timepiece of the present invention adopts the structure described below.

The structure of the crystal oscillating electronic timepiece of the present invention comprises an oscillating unit using a crystal oscillator as a time reference source, and a frequency dividing unit for dividing the frequency of the crystal oscillator to the frequency for driving the time display device. A display driving unit for driving the time display device, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, and a memory for storing data for controlling the output voltage of the constant voltage circuit The constant voltage circuit includes a block and a battery, and the constant voltage circuit includes a reference voltage unit, a differential amplifier, a plurality of resistors for correcting the amplification factor of the differential amplifier, and a resistor array including a plurality of MOS transistors connected in parallel to each resistor. In addition, the memory block further includes a memory cell array including a non-volatile memory element that is electrically writable and erasable.

The structure of the crystal oscillating electronic timepiece of the present invention comprises an oscillating unit using a crystal oscillator as a time reference source, and a frequency dividing unit for dividing the frequency of the crystal oscillator to the frequency for driving the time display device. A display driving unit for driving the time display device, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, and a memory for storing data for controlling the output voltage of the constant voltage circuit The constant voltage circuit includes a block and a battery, and the constant voltage circuit includes a reference voltage unit, a differential amplifier, a plurality of resistors for correcting the amplification factor of the differential amplifier, and a resistor array including a plurality of MOS transistors connected in parallel to each resistor. In addition, the memory block further includes a memory cell array including a non-volatile read-only memory element that can be electrically written only once.

[0016]

In the crystal oscillating electronic timepiece of the invention, the output voltage of the constant voltage circuit is supplied by amplifying the reference voltage generated by the reference voltmeter by the differential amplifier. At that time, the amplification factor of the differential amplifier can be arbitrarily changed by selecting the resistors forming the resistor array. That is, the output voltage of the constant voltage circuit can be set within the range of the reference voltage to the power supply voltage.

Therefore, after the semiconductor integrated circuit device is manufactured, the selection information of the resistor array that obtains the output voltage of the constant voltage circuit that best matches the watch specifications is stored in the nonvolatile memory of the memory block. The output voltage of the constant voltage circuit can be set to the optimum value by reading the information written in this memory block as the gate control signal of the MOS transistor forming the resistance array when the power is turned on or immediately after the power is turned on.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A crystal oscillation type electronic timepiece according to an embodiment of the present invention will be described below with reference to the drawings.

First, the structure of the crystal oscillation type electronic timepiece according to the first embodiment of the present invention will be described. FIG. 1 is a circuit block diagram showing the configuration of a crystal oscillation type electronic timepiece according to the first embodiment of the present invention.

As shown in FIG. 1, the crystal oscillating electronic timepiece of the present invention includes an oscillating unit 1 having a crystal oscillator as a time reference source,
A constant voltage is supplied to the frequency division unit 2 for dividing the frequency of the crystal unit to the frequency driven by the time display device, the display drive unit 3, the time display device 4, the oscillation unit 1 and the frequency division unit 2. A constant voltage circuit 6 for storing the data, a memory block 10 for storing data for controlling the output voltage of the constant voltage circuit 6, and a battery 5.

Further, the constant voltage circuit 6 includes a resistor array 7
And a reference voltage unit 8 and a differential amplifier 9.

The memory block 10 is a 3-bit memory cell array 11 having three memory elements having an electrically writable / erasable MONOS (metal-oxide film-nitride film-oxide film-semiconductor) structure, and a data latch circuit 12. A data I / O control circuit 13 for controlling data input / output, a data input terminal 14, an address control circuit 15 for selecting a data input destination, an address input terminal 16, and a write / erase voltage. It is configured by the Vpp terminal 17.

In FIG. 2, M constituting the memory cell array 11 is shown.
1 schematically shows the structure of a gate insulating film of an ONOS memory element. The gate insulating film is a three-layer insulating film called a top oxide film 19, a silicon nitride film 20, and a tunnel oxide film 21 from the gate electrode 18 side.

In the circuit diagram of FIG. 3, the constant voltage circuit 6 shown in FIG.
An example of the resistor array 7 in FIG.

The resistor array 7 includes eight resistors 31, 32, 33, 34, 35, 36, 37, 38 connected in series.
And eight MOS transistors 41, 42, 43, 44, 45, 46, 47, which are connected in parallel to these eight resistors,
48 and a decoder 30.

Next, after the semiconductor integrated circuit device is manufactured, in order to set the output voltage of the constant voltage circuit 6 in FIG. 1 which conforms to the watch specifications, the data written in the memory block 10 is used to set the resistance value in the resistance array 7. The control method will be described with reference to FIGS. 3 and 1.

As for the resistance value, the output from the data latch circuit 12 constituting the memory block 10 is input to the decoder 30, and the MOS transistors 41, 42, 43, 44, 4 are input.
By turning on any one of 5, 46, 47 and 48, eight kinds of resistance values can be selected.

For example, when the data stored in the memory block 10 is (0, 0, 0), this data is M
The decoder 30 is controlled so that the OS transistor 41 is turned on. As a result, the resistance value becomes the resistance value of the resistor 31.

Further, when the data stored in the memory block 10 is (0, 1, 1), the data is the decoder 3
The MOS transistor 44 is turned on via 0, and the resistance values are the resistance 31, the resistance 32, the resistance 33, and the resistance 34.
It becomes the resistance value which added and.

Next, the circuit operation of the constant voltage circuit 6 in FIG. 1 will be described with reference to the circuit diagram of FIG. In FIG. 4, the resistance 65 is a resistance value set in the resistance array 7 shown in FIG.

MOS transistors 52, 53, 54, 5
5, 56 and a reference voltage Vi obtained by a current mirror type reference voltage device composed of a resistor 51 are added to the line 50 as an input of a differential amplifier composed of MOS transistors 57, 58, 59, 60 and 61, and a reference voltage device The same voltage value as the reference voltage Vi obtained from the line 6 is used as the input of the differential amplifier.
7 is added, that is, to the fluctuation of the power supply voltage,
Output MOS so that the current flowing through the resistor 65 is constant
The gate voltage of the transistor 63 is taken out from the node 62, and the drain of the output MOS transistor 63 and VDD are kept at a constant output voltage.

Since the currents flowing through the resistors 64 and 65 are constant, the constant voltage value Vc at the output terminal 66 is Vc = Vi.
X (1 + R64 / R65). Where R64 and R
65 is the resistance value of the resistance 64 and the resistance 65, respectively. That is, the output voltage value of the constant voltage circuit 6 in FIG. 1 is the resistance value ratio R64 / R65 of the resistors 64 and 65.
It is possible to control by changing.

Therefore, changing the value of the resistance set in the resistance array 7 shown in FIG.
Is to change the resistance value of, and also to control the output voltage value.

The output of the constant voltage circuit 6 is the resistance 6 of FIG. 4 as shown in the graph of FIG. 5 showing the relationship between the power supply voltage and the output voltage.
If the ratio of 4 to the resistance 65 is 1, the curve becomes 25 and the resistance 6
When the ratio of 4 to the resistance 65 is 0.5, the curve 26 is obtained, and the output voltage of the constant voltage circuit 6 can be controlled.

Next, a method of writing and erasing data in the memory block 10 will be described with reference to FIG.

To write data to the 3-bit memory cell array 11 in the memory block 10, the Vpp terminal 17 is set to the write potential and the address signal is input to the address input terminal 16.

When the write destination memory element is selected, a data signal is input to the data input terminal 14.

At this time, if the input signal is "1",
A write voltage is applied to the gate of the MONOS memory to write to the memory cell array 11.

When the input signal is "0", MONOS
No write voltage is applied to the gate of the memory and the memory element remains in the non-written state.

In the method of erasing the data of the 3-bit memory cell array 11, all bits can be erased simultaneously by setting the Vpp terminal 17 to the erase potential.

The data of the 3-bit memory cell array 11 can be read into the data latch circuit 12 even when the power is turned on and under the control of the address signal.

In the first embodiment of the present invention, the number of memory elements forming the memory block 10 is 3 bits, but the number of bits may be increased. For example, 4
With respect to the bit, 16 kinds of resistance values can be selected, and by increasing the number of bits, it becomes possible to finely adjust the correction value of the resistance value.

Further, in the first embodiment of the present invention, MONOS is used as a memory element forming the memory cell array 11.
Although the memory device having the structure is used, a high dielectric memory device,
Alternatively, a memory element having an MNOS (metal-nitride film-oxide film-semiconductor) structure or a floating gate type non-volatile memory may be used.

Next, the structure of the crystal oscillation type electronic timepiece according to the second embodiment of the present invention will be described. FIG. 8 shows the second aspect of the present invention.
3 is a circuit block diagram showing a configuration of a crystal oscillation type electronic timepiece in the embodiment of FIG.

As shown in FIG. 8, the crystal oscillating electronic timepiece has an oscillating unit 101 using a crystal oscillator as a time reference source and a frequency divider for dividing the frequency of the crystal oscillator to the frequency driven by the time display device. The unit 102, the display driving unit 103, the time display device 104, the constant voltage circuit 106 for supplying a constant voltage to the oscillating unit 101 and the frequency dividing unit 102, and the output voltage of the constant voltage circuit 106 are controlled. It comprises a memory block 110 for storing data and a battery 105.

Further, the constant voltage circuit 106 comprises a resistor array 107, a reference voltage unit 108, and a differential amplifier 109.

The memory block 110 is a 3-bit memory cell array 111 composed of three read-only memory cells that can be electrically written only once, a data latch circuit 112, and a data read control circuit 113 for controlling data read. And consist of.

Next, the memory operation will be described with reference to the circuit diagram of FIG. 9 showing a part of the circuit of the memory cell which constitutes the memory cell array 111 of FIG.

As shown in FIG. 9, an n-channel MOS transistor (hereinafter referred to as a memory transistor) 120, which is a memory element, includes a drain 121, a source 122,
It is composed of a gate 123 and a substrate electrode 124.
A first resistor 125 is connected between the gate 123 and the source 122, and the gate 123 is connected to the low potential (hereinafter referred to as Vss) of the battery 105 shown in FIG. 8 through the second resistor 126 and the diode 119. There is. Drain 121
Is connected to the high potential (hereinafter referred to as Vdd) of the battery 105 shown in FIG.

Further, information is stored in the memory transistor 120.
A terminal 116 for supplying a high negative write voltage (hereinafter referred to as Vpp) from the outside when writing is performed. This terminal 116 is connected to the source 122 via the bit line 117.
It is connected to the. The bit line 117 and the word line 115 are connected by a third resistor 118.

Information is written by the potential difference V between the source 122 and the drain 121 connected via the bit line 117.
Vpp at which ds (Vdd-Vpp) becomes equal to or higher than the drain breakdown voltage of the memory transistor 120 is supplied from the external power source to the terminal 11
6 is applied to the drain of the memory transistor 120.
This is done by causing a junction breakdown between the substrates. Due to this junction breakdown, the drain 12 of the memory transistor 120 is
1 and the source 122 are electrically short-circuited through the substrate electrode 124.

At the time of writing this information, since a high negative voltage Vpp is applied to the source 122, the diode 1
19 becomes a forward direction and a current flows. From this Vss, the diode 119, the second resistor 126, the first resistor 125,
When a current flows through the path to the source 122, the resistance of the diode 119 is sufficiently smaller than that of the first resistor 125 and the second resistor 126, so that the gate 2
The potential of 3 can take an arbitrary value between Vss-0.6V and Vpp depending on the sizes of the first resistor 125 and the second resistor 126.

That is, the potential difference between the gate 123 and the source 122 can be set to be equal to or higher than the threshold voltage of the memory transistor 120. Therefore, the memory transistor 120 can be written in the ON state.

Generally, the drain breakdown voltage of an enhancement-type n-channel MOS transistor is determined by avalanche breakdown of the drain-substrate junction, electric field concentration on the surface due to the influence of the gate, and parasitic bipolar operation involving minority carrier injection. To be

The mechanism of the junction breakdown itself is the same as that of the junction breakdown PROM. That is, in writing, the drain is reverse-biased at a voltage higher than the drain breakdown voltage, causing a breakdown and causing a current to flow. Since most of the voltage is applied to the thin joint interface, the heat loss in the joint is large, and the temperature of a part of the non-uniform joint rapidly rises due to thermal runaway, leading to destruction.

Junction destruction type P that destroys the junction of the diode
In the ROM, the breakdown voltage is determined only by the avalanche breakdown of the PN junction, whereas in the memory transistor, the drain breakdown voltage is lowered by a plurality of effects as described above.

The graph of FIG. 10 shows the relationship between the drain breakdown voltage and the gate voltage with reference to the source potential. It is a well-known fact that the drain breakdown voltage is lowest when the gate voltage is about ½ of the drain voltage.

As described above, if the ratio of the sizes of the first resistor 125 and the second resistor 126 is appropriately selected and writing is performed with the memory transistor turned on, writing is performed with the drain withstand voltage being the lowest. It is possible to do.

Next, an information reading operation will be described. In this operation description, the potential of the bit line 127 is (Vdd-V
A state higher than ss) / 2 is defined as "1" and a state lower than ss / 2 is defined as "0".

The read of the stored information is performed by the word line 125.
, The resistance value of the junction-disrupted memory transistor is sufficiently smaller than the resistance value of the third resistor 118 because the drain 121 and the source 122 are short-circuited. Therefore, “1” is represented by the bit line 117. Is output from.

On the other hand, the resistance value of the memory transistor in the non-written state in which the junction is not broken is sufficiently larger than the resistance value of the third resistor 118 because the memory transistor 120 is always in the off state. "0" is read out as information.

The constant voltage circuit 1 shown in FIG. 8 is added to the circuit diagram of FIG.
An example of the resistor array 107 in 06 is shown.

The resistor array 107 includes eight resistors 31, 32, 33, 34, 35, 36, 37, which are connected in series.
38 and 8 MOSs connected in parallel to these 8 resistors
Transistors 41, 42, 43, 44, 45, 46, 4
7, 48 and a decoder 30.

Next, after the semiconductor integrated circuit device is manufactured, in order to set the output voltage of the constant voltage circuit 106 in FIG. 8 which conforms to the clock specifications, the data written in the memory block 110 is used to set the resistance value in the resistance array 107. The control method will be described with reference to FIGS. 3 and 8.

For the resistance value, the output from the data latch circuit 112 of the memory block 110 is input to the decoder 30,
MOS transistors 41, 42, 43, 44, 45, 4
Eight kinds of resistance values can be selected by turning on any one of 6, 47 and 48.

For example, when the data stored in the memory block 110 is (0, 0, 0), this data controls the decoder 30 so that the MOS transistor 41 is turned on. As a result, the resistance value becomes the resistance value of the resistor 31.

Furthermore, when the data stored in the memory block 110 is (0, 1, 1), the data turns on the MOS transistor 44 via the decoder 30, and the resistance values are the resistance 31 and the resistance 32. , Resistance 33 and resistance 34 are added.

Next, the circuit operation of the constant voltage circuit 106 in FIG. 8 will be described with reference to the circuit diagram of FIG. In FIG. 4, the resistance 65 is a resistance value set in the resistance array 107 shown in FIG.

MOS transistors 52, 53, 54, 5
5, 56 and a reference voltage Vi obtained by a current mirror type reference voltage device composed of a resistor 51 are applied to the line 50 as an input of a differential amplifier composed of MOS transistors 57, 58, 59, 60 and 61, and a reference voltage The same voltage value as the reference voltage Vi obtained from the converter is used as the input of the differential amplifier for the line 6
7 is added, that is, to the fluctuation of the power supply voltage,
Output MOS so that the current flowing through the resistor 65 is constant
The gate voltage of the transistor 63 is taken out from the node 62, and the drain of the output MOS transistor 63 and VDD are kept at a constant output voltage.

Since the currents flowing through the resistors 64 and 65 are constant, the constant voltage value Vc at the output terminal 66 is Vc = Vi.
X (1 + R64 / R65). Where R64 and R
65 is the resistance value of the resistance 64 and the resistance 65, respectively. That is, the output voltage value of the constant voltage circuit 6 in FIG. 1 is the resistance value ratio R64 / R65 of the resistors 64 and 65.
It is possible to control by changing.

Therefore, the resistor array 107 shown in FIG.
Changing the resistance value set in 4 is changing the resistance value of the resistor 65 shown in FIG. 4, and is also controlling the output voltage value.

As shown in FIG. 5, the output of the constant voltage circuit 106 is a curve 25 when the ratio of the resistance 64 and the resistance 65 of FIG. 4 is 1, and the ratio of the resistance 64 and the resistance 65 is 0.5. In the case of, the curve 26 is obtained, and the output voltage of the constant voltage circuit 106 can be controlled.

In the second embodiment of the present invention, the number of memory elements constituting the memory block 110 has been described as 3 bits, but the number of bits may be increased. For example,
With 4 bits, 16 kinds of resistance values can be selected, and by increasing the number of bits, it becomes possible to finely adjust the resistance value correction amount.

Further, in the second embodiment of the present invention, an n-channel MOS transistor is used as an electrically writable memory element constituting the memory cell array 111. However, a fuse ROM or an anti-fuse ROM is used.
May be used.

[0075]

As described above, according to the present invention,
After the semiconductor integrated circuit device has a constant voltage value that fluctuates due to manufacturing variations, the resistance value can be corrected and the constant voltage value can be set to the optimum value. Therefore, the constant voltage most conforming to the timepiece specifications has a long life due to low current consumption, and the frequency stability can be improved when a battery with large voltage fluctuation is used.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a crystal oscillation type electronic timepiece according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a memory element that constitutes the crystal oscillation type electronic timepiece according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a resistor array that constitutes a crystal oscillation type electronic timepiece according to an embodiment of the present invention.

FIG. 4 is a circuit diagram showing a constant voltage circuit which constitutes a crystal oscillation type electronic timepiece according to an embodiment of the invention.

FIG. 5 is a graph showing the relationship between the power supply voltage and the output voltage of the constant voltage circuit that constitute the crystal oscillation type electronic timepiece according to the embodiment of the present invention.

FIG. 6 is a circuit block diagram showing a crystal oscillation type electronic timepiece in a conventional example.

FIG. 7 is a circuit diagram of a constant voltage circuit that constitutes a crystal oscillation type electronic timepiece in a conventional example.

FIG. 8 is a circuit block diagram showing a crystal oscillation type electronic timepiece according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram showing a memory cell constituting a crystal oscillation type electronic timepiece according to a second embodiment of the present invention.

FIG. 10 is a graph showing a relationship between drain withstand voltage and gate voltage of a memory transistor, showing an example of writing information in a memory cell that constitutes a crystal oscillation type electronic timepiece according to a second embodiment of the present invention.

[Explanation of symbols]

 1 oscillator 2 frequency divider 3 display driver 4 time display device 6 constant voltage circuit 10 memory block

Claims (28)

[Claims] 1. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Section, a constant voltage circuit for supplying a constant voltage to the oscillating section and the frequency dividing section, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Quartz oscillation electronic timepiece. 2. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Is a crystal oscillation type electronic timepiece having a reference voltage unit, a differential amplifier, and a resistor array for correcting the amplification factor of the differential amplifier. 3. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. And a constant voltage circuit for supplying a constant voltage to the oscillator and the frequency divider, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. A memory cell array having a non-volatile memory element that is electrically writable and erasable, and a data I / O control circuit, an address control circuit, and a data latch circuit that control input / output of information to / from the memory cell array and write / erase. Characteristic quartz oscillation type electronic timepiece. 4. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. And a constant voltage circuit for supplying a constant voltage to the oscillator and the frequency divider, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. A crystal oscillation type having a memory cell array having a read-only non-volatile memory element that can be electrically written only once, and a data read control circuit and a data latch circuit for controlling reading of information from the memory cell array. Electronic clock. 5. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. And a constant voltage circuit for supplying a constant voltage to the oscillator and the frequency divider, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Electrically writable and erasable M
A crystal oscillation electronic timepiece having a memory cell array having a memory element having an ONOS (metal-oxide film-nitride film-semiconductor) structure. 6. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. And a constant voltage circuit for supplying a constant voltage to the oscillator and the frequency divider, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. An n-channel MOS transistor, which is a read-only memory element that can be electrically written only once, a memory cell array including a memory cell having a terminal for supplying a write voltage and a resistance for comparing resistance values. Characteristic quartz oscillation type electronic timepiece. 7. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Is a crystal oscillation type electronic timepiece having a resistor array including a plurality of resistors and a MOS transistor connected in parallel to each resistor. 8. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a reference voltage unit, a differential amplifier, and a resistor array that corrects the amplification factor of the differential amplifier, and the memory block has a memory cell array having electrically erasable nonvolatile memory elements, and information to the memory cell array. A crystal oscillation electronic timepiece having a data I / O control circuit for controlling input / output and write / erase of the device, an address control circuit, and a data latch circuit. 9. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a reference voltage unit, a differential amplifier, and a resistance array for correcting the amplification factor of the differential amplifier, and the memory block has a memory cell array having a read-only nonvolatile memory element that can be electrically written only once, and a memory. A crystal oscillation type electronic timepiece having a data read control circuit for controlling reading of information from a cell array and a data latch circuit. 10. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a reference voltage device, a differential amplifier, and a resistor array that corrects the amplification factor of the differential amplifier, and the memory block is a memory having a MONOS (metal-oxide film-nitride film-semiconductor) structure capable of being electrically written and erased. A crystal oscillation type electronic timepiece having a memory cell array having elements. 11. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a reference voltage unit, a differential amplifier, and a resistance array for correcting the amplification factor of the differential amplifier, and the memory block is an n-channel MOS transistor which is a read-only memory element that can be electrically written only once.
A crystal oscillation type electronic timepiece having a memory cell array including a memory cell having a terminal for supplying a write voltage and a resistance for comparing resistance values. 12. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Is a crystal oscillation type electronic timepiece having a reference voltage device, a differential amplifier, a plurality of resistors for correcting the amplification factor of the differential amplifier, and a resistor array including MOS transistors connected in parallel to the respective resistors. 13. An oscillating unit using a crystal unit as a time reference source, a frequency dividing unit for dividing the frequency of the crystal unit up to a frequency for driving the time display device, and a display drive for driving the time display unit. Section, a constant voltage circuit for supplying a constant voltage to the oscillating section and the frequency dividing section, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Writeable and erasable MO
A memory cell array having a memory element having a NOS (metal-oxide film-nitride film-semiconductor) structure, and data I / O for controlling input / output of information to / from the memory cell array and writing / erasing
A crystal oscillation electronic timepiece having a control circuit, an address control circuit, and a data latch circuit. 14. An oscillating unit using a crystal unit as a time reference source, a frequency dividing unit for dividing the frequency of the crystal unit up to a frequency for driving the time display device, and a display drive for driving the time display device. And a constant voltage circuit for supplying a constant voltage to the oscillator and the frequency divider, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. A memory cell array including an n-channel MOS transistor, which is a read-only memory element that can be electrically written only once, a terminal for supplying a write voltage, and a memory cell having a resistance for comparing resistance values, and a memory cell array A crystal oscillating electronic timepiece having a data read control circuit for controlling reading of information from and a data latch circuit. 15. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a resistor array composed of a plurality of resistors and MOS transistors connected in parallel to each resistor, and the memory block has a memory cell array having electrically erasable non-volatile memory elements, and input / output of information to / from the memory cell array. Data I / O for controlling write / erase
A crystal oscillation electronic timepiece having a control circuit, an address control circuit, and a data latch circuit. 16. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a resistance array composed of a plurality of resistances and MOS transistors connected in parallel to the respective resistances, and the memory block has a memory cell array having a read-only non-volatile memory element that can be electrically written only once.
A crystal oscillation type electronic timepiece having a data read control circuit for controlling reading of information from a memory cell array and a data latch circuit. 17. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a resistor array composed of a plurality of resistors and MOS transistors connected in parallel to each resistor, and the memory block has a memory element having an electrically writable / erasable MONOS (metal-oxide film-nitride film-semiconductor) structure. A crystal oscillation type electronic timepiece having a cell array. 18. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a plurality of resistors and a resistor array composed of MOS transistors connected in parallel to each resistor, and the memory block supplies an n-channel MOS transistor, which is a read-only memory element that can be electrically written only once, and a write voltage. A crystal oscillation type electronic timepiece having a memory cell array composed of a memory cell having a terminal for switching and a resistance for comparing a resistance value. 19. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a reference voltage device, a differential amplifier, and a resistor array that corrects the amplification factor of the differential amplifier, and the memory block is a memory having a MONOS (metal-oxide film-nitride film-semiconductor) structure capable of being electrically written and erased. A crystal oscillation having a memory cell array having elements, a data I / O control circuit for controlling input / output of information to and from the memory cell array, an address control circuit, and a data latch circuit. Formula electronic clock. 20. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a reference voltage unit, a differential amplifier, and a resistance array for correcting the amplification factor of the differential amplifier, and the memory block is an n-channel MOS transistor which is a read-only memory element that can be electrically written only once.
A memory cell array including a memory cell having a terminal for supplying a write voltage and a resistance for comparing resistance values; a data read control circuit for controlling reading of information from the memory cell array; and a data latch circuit. Characteristic quartz oscillation type electronic timepiece. 21. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a reference voltage unit, a differential amplifier, a plurality of resistors for correcting the amplification factor of the differential amplifier, and a resistor array composed of MOS transistors connected in parallel to each resistor, and the memory block can be electrically written and erased. A memory cell array having a non-volatile memory element, a data I / O control circuit for controlling input / output of information to / from the memory cell array and an address control circuit, and a data latch circuit. A quartz oscillator type electronic timepiece characterized in that 22. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a reference voltage unit, a differential amplifier, a plurality of resistors for correcting the amplification factor of the differential amplifier, and a resistor array composed of MOS transistors connected in parallel to each resistor, and the memory block can be electrically written only once. A memory cell array having a non-volatile memory element dedicated to read, a data read control circuit for controlling reading of information from the memory cell array, and a data latch circuit. Quartz oscillation electronic watch. 23. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a resistor array composed of a plurality of resistors and MOS transistors connected in parallel to each resistor, and the memory block has a memory element having an electrically writable / erasable MONOS (metal-oxide film-nitride film-semiconductor) structure. Crystal oscillation having a cell array, a data I / O control circuit for controlling input / output of information to / from a memory cell array, an address control circuit, and a data latch circuit Formula electronic clock. 24. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Section, a constant voltage circuit for supplying a constant voltage to the oscillating section and the frequency dividing section, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Multiple resistors and M connected in parallel to each resistor
An n-channel MOS transistor, which is a read-only memory element that has a resistance array composed of OS transistors, and which is electrically writable only once,
A memory cell array including a memory cell having a terminal for supplying a write voltage and a resistance for comparing resistance values; a data read control circuit for controlling reading of information from the memory cell array; and a data latch circuit. Characteristic quartz oscillation type electronic timepiece. 25. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a reference voltage unit, a differential amplifier, a plurality of resistors for correcting the amplification factor of the differential amplifier, and a resistor array composed of MOS transistors connected in parallel to each resistor, and the memory block can be electrically written and erased. Cell array having a memory device having a simple MONOS (metal-oxide film-nitride film-semiconductor) structure, and a data I / O control circuit for controlling input / output and writing / erasing of information to / from the memory cell array. A quartz-oscillation-type electronic timepiece characterized by having a control circuit and a data latch circuit. 26. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, a memory block for storing data for controlling the output voltage of the constant voltage circuit, and a battery. Has a reference voltage unit, a differential amplifier, a plurality of resistors for correcting the amplification factor of the differential amplifier, and a resistor array composed of a plurality of MOS transistors connected in parallel to each resistor, and the memory block is electrically only once. Writable read-only memory device, n-channel MOS
A memory cell array including a memory cell having a transistor, a terminal for supplying a write voltage, and a resistance for comparing resistance values, a data read control circuit for controlling reading of information from the memory cell array, and a data latch circuit are provided. A crystal oscillation type electronic timepiece having. 27. The memory device is a high dielectric memory device,
11. A memory element having a MNOS (metal-nitride film-oxide film-semiconductor) structure or a floating gate type non-volatile memory is used.
The crystal oscillation type electronic timepiece according to claim 13, claim 17, claim 19, or claim 23. 28. The electrically writable memory element is a fuse ROM or an antifuse R.
OM is used, Claim 6, Claim 11,
The crystal oscillation type electronic timepiece according to claim 14, claim 18, claim 20, claim 24, or claim 26.