JPH075278A - Quartz oscillation type electronic time piece - Google Patents

Abstract

PURPOSE:To prolong the life through low current consumption at constant voltage optimum to the time piece specification and improvement in frequency stability during using a battery with large voltage fluctuation by correcting the reference resistance value which is fluctuating due to the scatter of products, and setting the constant voltage value at an optimum value after completing a semiconductor integral circuit device. CONSTITUTION:The electronic time-piece employs a quartz oscillator as a reference time source and provided with a constant voltage circuit 6 having a frequency divider part 2 for dividing the frequency of the quartz oscillator to the frequency for driving a time indication device, a constant voltage circuit 6 equipped with a current mirror type reference voltage meter 8 and a differential amplifier 9 and a memory block 10 having an electrically writable and erasable memory element array 11 with MONOS(metal-oxide film-nitride film- oxide film-semiconductor) structure, a data I/O control circuit 13 for controlling input and output of information and write and erase to the memory element array 11 and an address control circuit 15. The constant voltage circuit 6 is provided with an MOS transistor which is connected in parallel to the resistor with the current mirror type reference voltage meter 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a crystal oscillator using a logic circuit of a CMOS (complementary field effect) transistor having means for dividing the frequency of the crystal oscillator to a time display device with the crystal oscillator as a time reference. Formula electronic timepieces,
In particular, when a battery of a type in which the discharge characteristic of the battery voltage fluctuates from 1.8 V to 1.55 V is used, the configuration of a crystal oscillation type electronic timepiece equipped with a constant voltage circuit capable of eliminating this voltage fluctuation It is about.

[0002]

2. Description of the Related Art A quartz oscillator type electronic timepiece using a logic circuit of a CMOS transistor having means for dividing a frequency of the quartz oscillator to a time display device with a quartz oscillator as a time reference, and a discharge characteristic of a battery voltage. Is 1.8V to 1.55V
Equipped with a constant voltage circuit that can eliminate this voltage fluctuation when using a battery that fluctuates up to
A conventional example of a crystal oscillation type electronic timepiece is shown in a circuit block diagram of FIG.

Conventionally, as shown in FIG. 8, a crystal oscillation type electronic timepiece is constituted by an oscillator 81, a frequency divider 82, a display driver 83, a time display device 84, a constant voltage circuit 86 and a battery 85.

The battery 85 is controlled by the constant voltage circuit 86.
The voltage is converted into a constant voltage of 5 V or less, and this constant voltage is applied to the oscillating unit 81 and the frequency dividing unit 82 to remove the influence of the voltage fluctuation on the oscillating frequency. On the other hand, the display drive unit 83
The voltage of the battery 85 is directly applied to the battery.

The circuit operation of the constant voltage circuit 86 in FIG. 8 will be briefly described with reference to the circuit diagram showing the constant voltage circuit in FIG.

MOS transistors 92, 93, 94, 9
The reference voltage obtained by the current mirror type reference voltmeter composed of 5, 96 and the reference resistor 91 is added to the line 90 as the input of the differential amplifier composed of the MOS transistors 97, 98, 99, 100, 101, and The reference voltage obtained by the current mirror type reference voltmeter is taken out as the gate voltage of the output MOS transistor 102 to output the output MOS transistor 102.
The output voltage between the drain of the transistor 102 and VDD is constant.

[0007]

The gain of the current mirror type reference voltage device depends on the amplification degree of each MOS transistor. If the gain is increased, the stability is improved, but the current consumption is increased. , Battery life will be shortened.

Therefore, in order to realize a constant voltage circuit with a current consumption of several tens of nA, it is necessary to increase the resistance value of the reference resistor 91 as the gain is increased.

As described above, in the crystal oscillation type electronic timepiece, it is necessary to strictly set the gain and the reference resistance 91 in order to set the constant voltage value to the best value.

However, variations in the element characteristics due to manufacturing variations of the MOS transistor and the reference resistor 91 cause an error in the setting of the gain and the reference resistor 91 which must be strictly performed. That is, the output voltage and current consumption of the constant voltage circuit 86 fluctuate due to manufacturing variations, which deteriorates watch performance and battery life.

Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a constant voltage that most conforms to the timepiece specifications, thereby extending the life due to low current consumption and using a battery with large voltage fluctuation. An object of the present invention is to provide a crystal oscillation type electronic timepiece having good frequency stability.

[0012]

In order to achieve the above object, the crystal oscillation type electronic timepiece of the present invention adopts the structure described below.

In the structure of the crystal oscillation type electronic timepiece of the present invention, the crystal oscillator is used as the time reference source, the frequency dividing unit divides the frequency of the crystal oscillator to the frequency driven by the time display device, and the current mirror type reference. A constant voltage circuit composed of a voltage generator and a differential amplifier, a memory element array having a MONOS (metal-oxide film-nitride film-oxide film-semiconductor) structure that is electrically writable and erasable, and information for the memory element array. A constant voltage circuit has a MOS transistor connected in parallel with a reference resistor to a current mirror type reference voltage device, and the gate of the MOS transistor has a memory block. Is controlled by changing the value of the reference resistance to correct the constant voltage value of the constant voltage circuit.

In the structure of the crystal oscillation type electronic timepiece of the present invention, the crystal oscillator is used as the time reference source, and the frequency dividing unit divides the frequency of the crystal oscillator to the frequency driven by the time display device, and the current mirror type reference. The constant voltage circuit includes a voltage regulator and a differential amplifier, a read-only memory cell array that can be electrically written only once, and a memory block including a control circuit that controls data reading. The current mirror type reference voltage device has a MOS transistor connected in parallel with the reference resistor, and the gate of the MOS transistor is controlled by the output from the memory block to change the value of the reference resistor to correct the constant voltage value of the constant voltage circuit. It is characterized by

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A crystal oscillation type electronic timepiece according to an embodiment of the present invention will be described below with reference to the drawings.

[0016]

First Embodiment FIG. 1 is a circuit block diagram showing a crystal oscillation type electronic timepiece according to the first embodiment of the present invention.

As shown in FIG. 1, the crystal oscillating electronic timepiece has an oscillating unit 1 having a crystal oscillator as a time reference source and a frequency divider for dividing the frequency of the crystal oscillator to the frequency driven by the time display device. A unit 2, a display drive unit 3, a time display device 4,
A constant voltage circuit 6 for supplying a constant voltage to the oscillator 1 and the frequency divider 2, a memory block 10 for storing data for controlling the output voltage of the constant voltage circuit 6, and a battery 5. To do.

Further, the constant voltage circuit 6 includes a reference resistor 7 and
It is composed of a current mirror type reference voltage unit 8 and a differential amplifier 9.

The memory block 10 is a 3-bit memory element array 11 including three memory elements having an electrically writable / erasable MONOS (metal-oxide film-nitride film-oxide film-semiconductor) structure and a data latch circuit. 12, a data I / O control circuit 13 for controlling data input / output, a data input terminal 14, an address control circuit 15 for selecting a data input destination, an address input terminal 16, and a write / erase voltage. And a Vpp terminal 17 for

The sectional view of FIG. 3 schematically shows the structure of the gate insulating film of the MONOS memory element which constitutes the memory element array 11. The gate insulating film is an insulating film having a three-layer structure including a top oxide film 36, a silicon nitride film 37, and a tunnel oxide film 38 from the gate electrode 35 side.

An embodiment of the reference resistor 7 in the constant voltage circuit 6 is shown in the circuit diagram of FIG.

As shown in FIG. 6, the reference resistor 7 includes eight resistors 61, 62, 63, 64, 65, which are connected in series.
66, 67, 68 and eight MOS transistors 71, 72, 73, 74, 7 connected in parallel to these eight resistors.
5, 76, 77, 78 and a decoder 60.

Next, after the semiconductor integrated circuit device is manufactured, in order to set the output voltage of the constant voltage circuit 6 in FIG. 1 which conforms to the watch specifications, the data written in the memory block 10 is used to set the reference in the reference resistor 7. A method of controlling the resistance value will be described with reference to FIGS. 6 and 1.

As the reference resistance value, the output from the data latch circuit 12 of the memory block 10 is input to the decoder 60,
MOS transistors 71, 72, 73, 74, 75, 7
By turning on any one of 6, 77, 78, eight types of resistors 61, 62, 63, 64, 65, 6
A resistance value of 6, 67 or 68 can be selected.

For example, when the data stored in the memory block 10 is (0, 0, 0), this data controls the decoder 60 so that the MOS transistor 71 is turned on. As a result, the reference resistance value is resistance 6
The resistance value is 1.

When the data stored in the memory block 10 is (0, 1, 1), the data is the decoder 6
The MOS transistor 74 is turned on via 0, and the reference resistance values are the resistance 61, the resistance 62, and the resistance 63.
And the resistance 64 are added.

When the reference resistance is changed, the output of the constant voltage circuit 6 becomes the curve 69 when the resistance value is increased and the curve 70 when the resistance value is decreased, as shown in the graph of FIG. It is possible to control the voltage.

Next, a method of writing and erasing data in the memory block 10 will be described with reference to FIG.

To write data to the 3-bit memory element array 11 in the memory block 10, the Vpp terminal 17 is set to the write potential and the address signal is input to the address input terminal 16.

When the write destination memory element is selected,
A data signal is input to the data input terminal 14.

At this time, if the input signal is "1",
A write voltage is applied to the gate of the MONOS memory to write to the memory element array 11.

When the input signal is "0", MONOS
No write voltage is applied to the gate of the memory, and the memory element array 11 remains in the non-write state.

In the method of erasing the data of the 3-bit memory element array 11, all bits can be erased at the same time by setting the Vpp terminal 17 to the erase potential.

The data of the 3-bit memory element array 11 can be read into the data latch circuit 12 even when the power is turned on and under the control of the address signal.

In the first embodiment of the present invention, the number of memory element arrays 11 forming the memory block 10 is 3 bits, but the number of bits may be increased.
For example, in 4 bits, 16 kinds of reference resistors can be selected, and by increasing the number of bits, it becomes possible to finely adjust the correction amount of the reference resistance value.

[0036]

[Embodiment 2] Next, the configuration of a quartz oscillation type electronic timepiece according to a second embodiment of the present invention will be described with reference to the circuit block diagram of FIG.

As shown in FIG. 2, the crystal oscillation type electronic timepiece according to the second embodiment of the present invention includes an oscillating section 21 having a crystal oscillator as a time reference source and a frequency of the crystal oscillator of a time display device. A constant voltage circuit 26 for supplying a constant voltage to the frequency dividing unit 22 that divides the frequency to a driving frequency, the display driving unit 23, the time display device 24, and the oscillating unit 21 and the frequency dividing unit 22.
And a memory block 30 for storing data for controlling the output voltage of the constant voltage circuit 26, and a battery 25.

Further, the constant voltage circuit 26 includes the reference resistor 2
7, a current mirror type reference voltage device 28, and a differential amplifier 29.

The memory block 30 has a 3-bit memory cell array 31 composed of three read-only memory cells that can be electrically written only once, a data latch circuit 32, and a data read control circuit 33 for controlling data read. And consist of.

Next, the memory operation will be described with reference to FIG. 4 which shows a part of the circuit of the memory cell which constitutes the memory cell array 31 of FIG.

In FIG. 4, an n-channel MOS transistor (hereinafter referred to as a memory transistor) 40 which is a memory element includes a drain 41, a source 42, a gate 43,
And the substrate electrode 44. A first resistor 45 is connected between the gate 43 and the source 42, and the gate 43 is connected to the low potential (hereinafter referred to as Vss) of the battery 25 in FIG. 2 via the second resistor 46 and the diode 47. . The drain 41 is connected to the high potential of the battery 25 in FIG. 2 (hereinafter referred to as Vdd).

Furthermore, when writing information to the memory transistor 40, a high negative write voltage (hereinafter Vp) is applied from the outside.
(referred to as p) is provided, and this terminal 51 is connected to the source 42 via the bit line 48. The bit line 48 and the word line 50 are connected by a third resistor 49.

To write information, the bit line 4 is connected to the terminal 51.
The potential difference Vds (Vdd−Vpp) between the source 42 and the drain 41 connected via the memory transistor 40 is
The write voltage Vpp that is equal to or higher than the drain withstand voltage is applied to the terminal 51 from the external power source to cause the junction breakdown between the drain of the memory transistor 40 and the substrate. Due to this junction breakdown, the drain 41 and the source 42 of the memory transistor 40 are electrically short-circuited through the substrate electrode 44.

At the time of this writing, since a high negative writing voltage Vpp is applied to the source 42, the diode 47 becomes forward and a current flows. When a current flows from the Vss to the diode 47, the second resistor 46, the first resistor 45, and the source 42, the diode 47
The magnitude of the resistance of the first resistor 45 and the second resistor 4 is
Since it is sufficiently smaller than that of 6, the potential of the gate 43 is the first
Vss− depending on the sizes of the resistor 45 and the second resistor 46 of
It is possible to take any value between 0.6V and Vpp.

That is, it is possible to make the potential difference between the gate 43 and the source 42 equal to or higher than the threshold voltage of the memory transistor 40. Therefore, the memory transistor 4
It is possible to write 0 in the ON state.

In general, the drain breakdown voltage of an enhancement type n-channel MOS transistor is determined by avalanche breakdown of the drain-substrate junction, electric field concentration on the surface due to the influence of the gate, and parasitic bipolar operation involving minority carrier injection. To be

The mechanism of the junction breakdown itself is the same as that of the junction breakdown PROM. That is, in writing, the drain is reverse-biased at a voltage higher than the drain breakdown voltage, causing a breakdown and causing a current to flow. Since most of the voltage is applied to the thin joint interface, the heat loss in the joint is large, and the temperature of a part of the non-uniform joint rapidly rises due to thermal runaway, leading to destruction.

Junction breakdown type P that destroys the junction of the diode
In the ROM, only the avalanche breakdown of the PN junction determines the breakdown voltage, whereas in the memory transistor, the drain breakdown voltage is lowered by a plurality of effects as described above.

The graph of FIG. 5 shows the relationship between the drain withstand voltage and the gate voltage with reference to the source potential. It is well known that the drain breakdown voltage is lowest when the gate voltage is about ½ of the drain voltage.

Thus, the first resistor 45 and the second resistor 4
The size of the memory transistor 4 is selected appropriately.
When 0 is turned on and writing is performed, writing can be performed in a state where the drain breakdown voltage is the lowest.

Next, the operation of reading information will be described. In the following description, the potential of the bit line 48 is (V
A state higher than dd-Vss / 2 is defined as "1", and a state lower than dd-Vss / 2 is defined as "0".

To read the stored information, when the potential of the word line 50 is set to Vss, the resistance value of the junction-disrupted memory transistor becomes the resistance value of the third resistor 49 because the drain 41 and the source 42 are short-circuited. Since it is sufficiently small compared to the above, “1” is output from the bit line 48.

On the other hand, the resistance value of the memory transistor in the non-written state in which the junction is not broken is the third resistance 4 because the memory transistor 40 is always “off”.
Since it is sufficiently larger than the resistance value of 9, "0" is read out as information.

The circuit diagram of FIG. 6 shows one embodiment of the reference resistor 27 in the constant voltage circuit 26.

As shown in FIG. 6, the reference resistor 27 is 8
Serially connected resistors 61, 62, 63, 64, 65,
66, 67, 68 and eight MOS transistors 71, 72, 73, 74, 7 connected in parallel to these eight resistors.
5, 76, 77, 78 and a decoder 60.

Next, in order to set the output voltage of the constant voltage circuit 26 in FIG. 2 which meets the timepiece specifications after the semiconductor integrated circuit device is manufactured, the reference resistance in the reference resistor 27 is used by using the data written in the memory block 30. A value control method will be described with reference to FIGS. 2 and 6.

For the reference resistance value, the output from the data latch circuit 32 of the memory block 30 is input to the decoder 60,
MOS transistors 71, 72, 73, 74, 75, 7
By turning on any one of 6, 77, 78, eight types of resistors 61, 62, 63, 64, 65, 6
A resistance value of 6, 67 or 68 can be selected.

For example, when the data stored in the memory block 30 is (0, 0, 0), this data controls the decoder 60 so that the MOS transistor 71 is turned on. As a result, the reference resistance value is resistance 6
The resistance value is 1.

Furthermore, when the data stored in the memory block 30 is (0, 1, 1), the data “turns on” the MOS transistor 74 via the decoder 60.
In this state, the reference resistance value is the resistance value obtained by adding the resistance 61, the resistance 62, the resistance 63, and the resistance 64.

When the reference resistance is changed, the output of the constant voltage circuit 26 shows a curve 6 when the resistance value is increased as shown in FIG.
When the resistance value is reduced to 9, the curve becomes 70 and the output voltage of the constant voltage circuit 26 can be controlled.

In the second embodiment of the present invention, the number of memory cell arrays 31 forming the memory block 30 has been described as 3 bits, but the number of bits may be increased.

For example, when the memory cell array 3 has 14 bits, 16 kinds of reference resistors can be selected, and by increasing the number of bits, the correction amount of the reference resistance value can be finely adjusted.

[0063]

As described above, according to the present invention,
After the semiconductor integrated circuit device has a reference resistance that fluctuates due to manufacturing variations or the like, the reference resistance value can be corrected and the constant voltage value can be set to the best value. Therefore, when the constant voltage that best matches the watch specifications is used to extend the life due to low current consumption, and when batteries with large voltage fluctuations are used,
The effect is large, such as the improvement of frequency stability.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a crystal oscillation type electronic timepiece according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a crystal oscillation type electronic timepiece according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a memory device array according to a first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a memory cell according to a second embodiment of the present invention.

FIG. 5 is a graph showing an example of writing information in a memory cell according to the second embodiment of the present invention, showing a relationship between a drain breakdown voltage and a gate voltage of a memory transistor.

FIG. 6 is a circuit diagram showing a reference resistor according to an embodiment of the present invention.

FIG. 7 is a graph showing the relationship between the power supply voltage and the output of the constant voltage circuit in the example of the present invention.

FIG. 8 is a circuit block diagram showing a crystal oscillation type electronic timepiece in a conventional example.

FIG. 9 is a circuit diagram showing a constant voltage circuit in a conventional example.

[Explanation of symbols]

 1 oscillator 2 frequency divider 3 display driver 4 time display device 6 constant voltage circuit 10 memory block

Claims (3)

[Claims] 1. A constant unit comprising a crystal unit as a time reference source, a frequency dividing unit for dividing the frequency of the crystal unit up to a frequency for driving a time display device, a current mirror type reference voltage unit and a differential amplifier. A voltage circuit, an electrically erasable MONOS (metal-oxide film-nitride film-oxide film-semiconductor) structure memory element array, and input / output of information to and from the memory element array and data for controlling writing / erasing A constant voltage circuit has a MOS transistor connected in parallel with a resistor in a current mirror type reference voltage device, and a gate of the MOS transistor is connected to the memory block having an I / O control circuit and an address control circuit. A crystal oscillation electronic timepiece characterized by controlling the output to change the resistance value to correct the constant voltage value of a constant voltage circuit. 2. A constant unit comprising a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, a current mirror type reference voltage device and a differential amplifier. It has a voltage circuit, a read-only memory cell array that is electrically writable only once, and a memory block composed of a data read control circuit that controls the reading of data.The constant voltage circuit includes a current mirror type reference voltage device and a resistor. It has MOS transistors connected in parallel,
A quartz oscillation electronic timepiece characterized in that the gate of a MOS transistor is controlled by the output from a memory block to change the resistance value and correct the constant voltage value of a constant voltage circuit. 3. A memory cell that constitutes a read-only memory cell array that can be electrically written only once is for comparing an n-channel MOS transistor which is a memory element, a terminal for supplying a write voltage, and a resistance value. The crystal oscillation type electronic timepiece according to claim 2, which is configured by a resistor.