JPH0837521A - Phase fluctuation absorbing circuit - Google Patents

Abstract

PURPOSE:To suppress the amount of device side received data delayed from transmission line side received data at a minimum without generating even one time of slip concerning the phase fluctuation absorbing circuit provided by using an elastic store memory at a digital transmitter. CONSTITUTION:This circuit is provided with an elastic store 1, write reset pulse generating circuit 2 for outputting a write reset pulse (c) from a transmission line side received clock (b), read reset pulse generating circuit 3 for outputting a read reset pulse (h) from a device inside reference clock (d), and phase fluctuation amount measuring circuit 5 for inputting the transmission line side received clock (b) and the device inside reference clock (d), measuring the mutual phase fluctuation amount and outputting phase fluctuation amount data (e). Besides, a phase comparator circuit 4 is provided to input the write reset pulse (c), read reset pulse (h) and phase fluctuation amount data (e), to monitor the mutual timing relation and to output phase slip information (f) and window information (g).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase fluctuation absorbing circuit, and more particularly to a phase fluctuation absorbing circuit realized by using an elastic store memory in a digital transmission device.

[0002]

2. Description of the Related Art On the side of a station which receives a digital signal with an uncertain phase transmitted from a station which opposes through a digital transmission line, normally, a phase aligning circuit, a frame aligner circuit for aligning the frame phases of the received digital signals,
A circuit called a delay insertion / removal circuit or a phase fluctuation absorption circuit is prepared to provide a slip control function with hysteresis for phase fluctuations (wander) caused by expansion and contraction of the transmission line due to temperature fluctuations. .

Conventionally, there are two types of these circuit systems: a first signal having a phase as it is of a signal received from a digital transmission line, and a second signal having a phase with the first signal having a fixed delay. Are prepared, and one of the two types of signals is selected and written into an elastic store memory for phase alignment or phase fluctuation absorption.
As a conventional technique of these circuit systems, for example, Japanese Patent Laid-Open No. 60-
FIG. 2 of Japanese Patent Application Laid-Open No. 254939,
FIG. 3 of Japanese Unexamined Patent Publication No.
There is a configuration example shown in FIG. 5 and FIG. 5 of JP-A-4-31120. FIG. 7 shows a block diagram as a phase fluctuation absorbing circuit that generically names these conventional circuit systems. This conventional phase fluctuation absorbing circuit detects a frame synchronization pattern from an input digital signal j input through a digital transmission path, establishes frame synchronization, and outputs a write reset pulse k and a write phase comparison pulse m of the input digital signal j. A frame synchronization circuit 10 and an input digital signal j input through the digital transmission line.
And a delay circuit 11-1 composed of a shift register or a RAM (random access memory) for outputting an input digital signal n by delaying the input digital signal n, and a write reset pulse k output from the frame synchronization circuit 10 is set to the same value as the input digital signal j. A delay circuit 11-2 comprising a shift register or a RAM for outputting a write reset pulse p with a predetermined time delay;
A delay circuit 11-3 comprising a shift register or a RAM for delaying the output write phase comparison pulse m by the same predetermined time as the input digital signal j and the write reset pulse k and outputting a write phase comparison pulse q;
A selector 12-1, which is controlled by the selector switching control signal r and selects the input digital signal j input through the digital transmission line or the input digital signal n output from the delay circuit 11-1 and outputs it as the input digital signal s;
Under the control of the selector switching control signal r, the write reset pulse k of the output of the frame synchronization circuit 10 or the delay circuit 1
Selector 12-2 which selects 1-2 output write reset pulse p and outputs it as write reset pulse t
And a selector 12 that selects the write phase comparison pulse m output from the frame synchronization circuit 10 or the write phase comparison pulse q output from the delay circuit 11-3 under the control of the selector switching control signal r and outputs the selected pulse as the write phase comparison pulse u.
-3, a pulse generation circuit 13 for generating and outputting a read reset pulse x in synchronization with the internal reference pulse v, a write phase comparison pulse u of the output of the selector 12-3, and a read reset pulse x of the output of the pulse generation circuit 13. And outputs a selector switching control signal r to output the selector 1
2-1, phase comparison circuit 14 to be supplied to selector 12-2 and selector 12-3, and write reset pulse t
And an elastic store memory 15 which sequentially writes the input digital signal s in synchronization with the write clock w on the basis of the read clock pulse z and sequentially reads out the read data signal y in synchronization with the read clock z on the basis of the read reset pulse x. Is done.

Since the phase of the read reset pulse x output from the pulse generation circuit 13 is irrelevant to the phase of the write reset pulse k or the write phase comparison pulse m output from the frame synchronization circuit 10, the elastic store memory is used. It is necessary to determine whether the write timing and the read timing of No. 15 are in an appropriate state. For this reason, a phase comparison circuit 14 is provided to compare the phases of the read reset pulse x and the write phase comparison pulse u, and select the selector 12 according to the phase difference.
The selector switching control signal r for controlling the selection states of -1 to 12-3 is output. That is, when the phases of the write reset pulse t and the read reset pulse x come close to each other, each of the selectors 12-1 to 12-3 is controlled by the selector switching control signal r to be delayed by the delay circuit 11-1.
Since the output of each of the delay circuits 11-3 is selected, the phases of the write reset pulse t and the read reset pulse x are shifted by the respective delay amounts of the delay circuits 11-1 to 11-3. Stick store memory 15
The writing and reading phases do not have to match. Here, the respective delay amounts of the delay circuit 11-1 to the delay circuit 11-3 are selected to have substantially the same predetermined value according to the phase variation amount of the digital transmission line.

[0005]

In this conventional phase fluctuation absorbing circuit, the phase comparison circuit 14 only operates when the write phase approaches the read phase due to the phase fluctuation of the digital transmission line and immediately before the slip occurs. Since the phase relationship is known, that is, the selector switching control signal r is output, the writing phase and the reading phase to the elastic store memory 15 approach the phase fluctuation of the digital transmission path or less at the time of establishing frame synchronization. In such a case, the slip always occurs once, the read data is erroneous, and the read data signal y is delayed more than necessary with respect to the input digital signal j. Further, the delay amounts of the delay circuits 11-1 to 11-3 are fixed values which are determined in advance in consideration of the amount of phase change due to temperature fluctuation or the like of the digital transmission line, and are therefore input to the elastic store memory 15. When the input digital signal j is input through, for example, network switching of a digital transmission network, the phase of the input digital signal j is delayed according to the jitter wander of each transmission system of the network depending on the transmission system through the network. The amount of change is too large to cover with a predetermined fixed delay amount in the circuits 11-1 to 11-3. Therefore, the delay amount of each of the delay circuits 11-1 to 11-3 in the phase fluctuation absorbing circuit corresponding to the input digital signal j input by the network switching must be changed every time the network is switched, which is not practical. .

[0006]

In the phase fluctuation absorbing circuit according to the present invention, the transmission line side received data inputted from the transmission line side is written to the transmission line side same as the transmission line side received data as a write clock signal with reference to a reset pulse. An elastic that sequentially writes in synchronization with the transmission-path-side reception clock input from the device and also sequentially reads out and outputs the reception data on the device side in synchronization with the reference clock signal in the reception-side device as a read clock signal based on the read reset pulse A store memory, a write reset pulse generating means for generating and outputting the write reset pulse from the transmission path side reception clock, and a phase variation amount of the transmission path side reception clock measured with reference to a reference clock signal in the reception side device. Phase fluctuation that outputs fluctuation amount information Based on the phase fluctuation amount information from the measuring means and the phase fluctuation amount measuring means, the write reset pulse is set as a starting point, and after a predetermined time, the phase difference setting position allowable range of the read reset pulse with respect to the write reset pulse is set and the window is set. Phase comparing means for outputting the information as phase slip information when the read reset pulse is out of the phase difference setting position allowable range, and at a predetermined cycle when the phase slip information is not input from the phase comparing means. The read reset pulse that is self-propelled is generated and output and supplied to the elastic store memory, and when the phase slip information is input from the phase comparison means, the read reset that has been self-propelled and generated and output until then. Reset the pulse and read the above The reset pulse and a read reset pulse generating means for supplying to said elastic store memory the controls to enter the phase difference setting position within the allowable range of the window information supplied from the phase comparing means.

Further, the phase fluctuation absorbing circuit according to the present invention comprises:
The read reset pulse generating means controls the position adjustment of the read reset pulse when the window information is input from the phase comparison means so that the read reset pulse is positioned at the center of the phase difference setting position allowable range.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A transmission line side received data a inputted to an input terminal DI through a digital transmission network is inputted to an input terminal WC through the same digital transmission network as the transmission line side received data a with reference to a write reset pulse c inputted to an input terminal WR. The data is sequentially written in synchronization with the transmission line side reception clock b as an input write clock signal, and is used as a readout clock signal based on a readout reset pulse h output from a readout reset pulse generation circuit 3 to be described later. An elastic store memory 1 that sequentially reads out synchronously and outputs device-side received data i, and generates and outputs a write reset pulse c from a transmission line-side received clock b to output an input terminal WR of the elastic store memory 1 and a read reset described later. The pulse generation circuit 3 and The write reset pulse generation circuit 2 to be supplied to the phase comparison circuit 4 and the phase fluctuation of the transmission line side reception clock b are measured with reference to the reception side device internal reference clock d and, for example, binary data is output as the phase fluctuation amount data e. A phase variation measuring circuit 5 to be supplied to a phase comparing circuit 4 described later, and a permissible range of the phase difference setting position of the read reset pulse h with respect to the write reset pulse c based on the phase variation data e from the phase variation measuring circuit 5. (Hereinafter referred to as a window) t ₂ is set with the trailing edge of the write reset pulse c output from the write reset pulse generation circuit 2 as a starting point, output as window information g, and supplied to a read reset pulse generation circuit 3 described later. And a read reset input from a read reset pulse generating circuit 3 described later. It is determined whether or not the read pulse h is within the window that is within the allowable range of the phase difference setting position, and when the position of the read reset pulse h is out of the window, the phase slip information f is output and a read reset pulse generation circuit to be described later. 3 and the phase slip information f and window information g from the phase comparator 4 and the write reset pulse c output from the write reset pulse generator 2
When the position of the read reset pulse c deviates from the window and the window information g is input from the phase comparison circuit 4, the position of the read reset pulse h is set to the center of the window, that is, the reference. It is composed of the read reset pulse generation circuit 3 which is controlled so as to return it to the position, outputs it, and supplies it to the input terminal RR of the elastic store memory 1 and the phase comparison circuit 4.

Here, the setting of the window in the phase comparison circuit 4 is performed in accordance with the magnitude of the phase variation data e output from the phase variation measurement circuit 5, and the read reset pulse h in the read reset pulse generation circuit 3. The position adjustment to the center of the window is performed when the phase variation is relatively small as in FIG. 2, when the phase variation is medium as in FIG. 3, and when the phase variation is as in FIG. In any case where the amount of fluctuation is relatively large, each read reset pulse h is adjusted so as to be located at the center of each of the windows α ₁ , α ₂ and α ₃ .

With the above configuration, the elastic store memory 1 stores the transmission line side received data a inputted through the digital transmission network on the basis of the write reset pulse c.
Is sequentially written in synchronization with the transmission line side reception clock b input through the same digital transmission network, and is sequentially read out in synchronization with the reception side device internal reference clock d based on the read reset pulse h to output the device side reception data i. I do.

Next, a detailed description will be given with reference to FIG. 5. The transmission line side receiving clock b inputted to the input terminal WC of the elastic store memory 1, the write reset pulse generation circuit 2 and the phase fluctuation amount measurement circuit 5 From this transmission line side reception clock b, the write reset pulse generation circuit 2
At the write reset pulse c shown in FIG.
Is generated and supplied to the input terminal WR of the elastic store memory 1, the phase comparison circuit 4, and the read reset pulse generation circuit 3. Also, the transmission path side reception clock b
Is supplied to the phase fluctuation amount measuring circuit 5 to measure the phase fluctuation amount with respect to the internal reference clock d of the receiving side. As a result, the phase fluctuation amount measuring circuit 5 compares the phase fluctuation amount data e with, for example, binary data. It is supplied to the circuit 4. The phase comparison circuit 4 sets the permissible range of the phase difference setting position of the read reset pulse h with respect to the write reset pulse c according to the phase fluctuation value of the phase fluctuation data e from the phase fluctuation amount measuring circuit 5, that is, as shown in FIG. , A window having a time width t ₂ that is repeated in the same cycle as the read reset pulse h is set and supplied to the read reset pulse generation circuit 3 as window information g.
By comparing the window information g and a read reset pulse h, when crossing a read reset pulse h the window of the phase difference setting position tolerance at a time width t ₂ is -2 -1 or 5 in FIG. 5 And outputs it to the read reset pulse generation circuit 3. Here, the phase slip information f indicated by -1 in FIG. 5 indicates a case where the read reset pulse h deviates from the window in front of the phase difference setting position allowable range, as indicated by -2 in FIG. The phase slip information f indicated by -2 in FIG. 5 indicates a case where the read reset pulse h deviates from the window behind the phase difference setting position allowable range as indicated by -4 in FIG.

The time width t ₁ between the trailing edge of the write reset pulse c in FIG. 5 and the leading edge of the window information g in FIG. 5 is determined by the original specifications of the elastic store memory 1. Is a fixed value,
It has a value substantially equivalent to several clock cycles of the write reset pulse c.

FIG. 6 is a block diagram showing the internal configuration of the read reset pulse generation circuit 3, which comprises a counter 30 and a reset pulse generator 31. here,
The counter 30 divides the frequency of the internal reference clock d of the receiving side input to the clock input terminal CK, and normally outputs a read reset pulse h of a constant period, for example, 8 KHz, and runs by itself. Further, when the phase slip information f is input from the phase comparison circuit 4, the reset pulse generator 31 receives the first first write reset pulse c input from the write reset pulse generation circuit 2 and the phase comparison circuit 4. With the window information g input from the counter 30, a reset pulse β is output to return the read reset pulse h output from the counter 30 to the center of the window which is the reference position, and is supplied to the reset input terminal R of the counter 30.

In this way, when the phase slip information f occurs at the leading edge of the window information g, as in the case of -1 in FIG. 5, for example, the reading indicated by -2 in FIG. 5 at that time. The reset pulse h is reset to return the read reset pulse h to the reference position located at the center of the window information g at this time as shown by -3 in FIG. 5, and as in the case of -2 in FIG. , If the phase slip information f occurs at the trailing edge of the window information g, the read reset pulse h shown at -4 in FIG. 5 at that time is reset to read reset as shown at -5 in FIG. The pulse h is returned to the reference position located at the center of the next window information g.

Here, the read reset pulse h is returned to the reference position located at the center of the window information g even if the read reset pulse h is shifted from the reference position to either the leading edge or the trailing edge of the window. This is because the margin of the deviation becomes the same for both.

In this manner, when the transmission path side reception data a and transmission path side reception clock b input to the elastic store memory 1 are input by switching networks having different jitter wanders for each transmission system. However, the phase difference between the write reset pulse c and the read reset pulse h is appropriately controlled in response to the jitter wander of each transmission system of the network, that is, the read reset pulse h is automatically controlled to always be located at the center of the window. To adjust,
The transmission line side received data a can be written and read out and the device side received data i can be output without generating a single slip in the elastic store memory 1.

[0017]

As described above, according to the present invention, the phase difference between the write reset pulse and the read reset pulse is properly controlled in accordance with the jitter wander that is possessed by each transmission system of the digital transmission network. It is possible to write and read the transmission path side reception data and output the apparatus side reception data without causing a single slip. Therefore, it is possible to minimize the delay amount of the device-side received data with respect to the transmission-path-side received data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a phase fluctuation absorbing circuit according to one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining an operation when the amount of phase fluctuation is relatively small in the phase fluctuation absorbing circuit of the embodiment.

FIG. 3 is a waveform diagram for explaining an operation in the case where the amount of phase fluctuation is medium in the phase fluctuation absorbing circuit of the embodiment.

FIG. 4 is a waveform chart for explaining an operation when the amount of phase fluctuation is relatively large in the phase fluctuation absorbing circuit of the embodiment.

FIG. 5 is a waveform diagram for explaining the operation of the phase fluctuation absorbing circuit of the same embodiment.

FIG. 6 is a block diagram showing an internal configuration of a read reset generation circuit in the phase fluctuation absorption circuit of the embodiment.

FIG. 7 is a block diagram showing a conventional phase fluctuation absorbing circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Elastic store memory 2 Write reset pulse generation circuit 3 Read reset pulse generation circuit 4 Phase comparison circuit 5 Phase fluctuation amount measurement circuit a Transmission line side received data b Transmission line side reception clock c Write reset pulse d Receiver side internal reference clock e Phase Fluctuation data f Phase slip information g Window information h Read reset pulse i Device-side received data

Claims (2)

[Claims] 1. The transmission path side received data inputted from the transmission path side is written in sequence while synchronizing with the transmission path side received clock inputted from the same transmission path side reception data as a write clock signal with reference to a reset pulse. An elastic store memory for sequentially reading and outputting device-side received data in synchronization with a reference clock signal in the receiving side device as a read clock signal while writing and reading a reset pulse, and the write reset from the transmission side reception clock Write reset pulse generating means for generating and outputting a pulse, phase fluctuation amount measuring means for measuring phase fluctuation amount of the transmission path side reception clock with reference to the reference clock signal in the reception side device, and outputting phase fluctuation amount information, From the phase fluctuation amount measuring means Based on the phase variation information, a predetermined time after the write reset pulse is set as a starting point, a phase difference setting position allowable range of the read reset pulse with respect to the write reset pulse is set and output as window information, and the read reset pulse has the phase difference. A phase comparison unit that outputs phase slip information when the phase slip information is out of the set position allowable range; and a self-propelled read reset pulse that is generated and output in a predetermined cycle when the phase slip information is not input from the phase comparison unit. When the phase slip information is input from the phase comparing means and supplied to the elastic store memory, the read reset pulse which has been generated and output by itself is reset and the read reset pulse is compared with the phase comparison information. Input from the means Read-out reset pulse generation means for controlling the window information to be within the permissible range of the phase difference setting position and supplying the window information to the elastic store memory. 2. The read reset pulse generating means controls the position adjustment of the read reset pulse when the window information is input from the phase comparing means so that the read reset pulse is positioned at the center of the phase difference setting position allowable range. The phase fluctuation absorbing circuit according to claim 1, wherein: