JPH0834563B2 - Character / pattern memory playback device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a character / pattern storage / reproduction device capable of storing an image pattern such as a title character or a graphic, and outputting the image pattern superimposed on another image. Is.

[Prior art]

In recent years, the demand for home video cameras has increased with the spread of home VTRs, and the demand for multifunctional and editing functions of home video cameras has increased.

Among these functions, the impose for inserting a title or the like, the telop, and the like are one of the most requested functions.

Hereinafter, a conventional telop device for inserting a title and the like will be described with reference to FIG. In FIG.
(1) is a video signal input terminal, (2) is a detection circuit for extracting character / pattern information, (3) is a sync separation circuit for separating a sync signal from the video signal input, (4) is a serial-parallel conversion circuit, ( 5) is a parallel-serial conversion circuit 1, (6) is a memory, (7) is a reference clock oscillation circuit, (8) and (9) are vertical counters and horizontal counters for instructing the addresses of the memory (6), ( 10) is a frequency dividing circuit for controlling the up / down timing of the vertical counter (8) and the horizontal counter (9) from the sync separation circuit (3) and the oscillation circuit (7), (11) is a controller, (12)
Is a user command signal such as a switch, (13) is a character superimposing circuit for superimposing character / pattern information on another video signal, and (14) is a video signal output terminal.

First, the main flow of the character / pattern signal will be described. The video signal input from the video signal input terminal (1) is converted into a digital signal by the detection circuit (2) at the same time that a synchronization signal is generated by the synchronization separation circuit (3). This digital signal is converted into a digital signal of 8 bits by the serial / parallel conversion circuit (4) and stored in the memory (6). A digital signal of 8 bits or the like, which is information such as characters and patterns stored in the memory (6), becomes a serial digital signal by the parallel-serial conversion circuit (5) and is superimposed on the original video signal by the character superimposing circuit (13). Output to the video output terminal (14).

In order to realize the above operation, a reference clock is created by the oscillator circuit (7) of this circuit, and this reference clock is supplied to the serial-parallel conversion circuit (4) and the parallel-serial conversion circuit (5) to convert the conversion timing. give. Also,
This clock is frequency-divided by the frequency dividing circuit (10) and then supplied to a horizontal counter (9) which is an addressing counter for the lower bits of the memory (6) to address the memory (6). The carry signal of the horizontal counter (9) is supplied to a vertical counter (8), which is a higher-order bit addressing counter of the memory (6), and addresses the memory (6). Further, the controller (11) is designated by a command signal (12) such as a switch to write or read a character / pattern. As a result, the controller (11) has a memory (6), a serial-parallel conversion circuit (4), a parallel-serial conversion circuit (5), a horizontal counter (9), a vertical counter (8), a frequency dividing circuit (10), and an oscillation circuit. (7) is set to the operating or non-operating state. The controller (11) resets the horizontal counter (9) and the vertical counter (8) at the start point of one field with the sync signal supplied by the sync separation circuit (3) as a reference, and patterns and characters in the screen are displayed. Correlation is made between the positions such as and the address of the memory (6). Here, the read operation timing from the memory will be described. For example, in the case of an 8-bit memory, the result is as shown in FIG. 7, and the serial data block (a) corresponding to 1 bit of the memory, that is, 1 pixel.
On the other hand, the address of the memory is changed every 8 pixels.
Further, the parallel-serial conversion timing is performed by the load pulse (b), and the reading from the memory is performed by the latch pulse 1 (d) until the next load pulse (b) arrives.
Perform during the period displayed in.

[Problems to be solved by the invention]

Although the conventional character / pattern storage / reproduction device has been described above, the conventional character / pattern storage / reproduction device cannot reproduce the character / pattern information with a border.

An object of the present invention is to provide a character / pattern storage / reproduction device capable of storing character / pattern information and reproducing with a trim in a home video camera or the like.

 It is to provide a character / pattern storage / reproduction device.

[Means for solving the problem]

A character / pattern storage / reproduction device according to the present invention is
Character pattern for digitizing the input video signal and storing the character / pattern information in the memory, reading the character / pattern information from the memory, and adding and superimposing the new second input video signal to output the video signal. In the memory reproducing device, an address adder for deriving a signal for reading out the character / pattern information of the current time and the data of the horizontal scanning period before and after the address in one addressing cycle, and once in one addressing cycle by this address adder A memory capable of reading a plurality of bits, three parallel / serial conversion circuits for converting the read data of the three horizontal scanning periods into serial digital signals, respectively, and a current time of the three serial digital signals. One serial digital signal corresponding to the character / pattern information of A first delay circuit for delaying, a first OR circuit for adding three serial digital signals, and a second delay circuit for delaying the signal of the first OR circuit by the same amount as the delay amount of the first delay circuit, The third delay circuit and the second and third
A gate circuit for enabling the output of the delay circuit of
According to the second OR circuit for adding the outputs of the OR circuit and the outputs of the second and third delay circuits, and the output of the second OR circuit,
It is provided with predetermined fixed information and means for switching the new second input video signal.

[Action]

The characters and pattern information that has been stored can be replayed with a border.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a character / pattern storage / reproduction device according to the present invention. In FIG.
(1) is a video signal input terminal, (2) is a detection circuit for extracting character / pattern information, (3) is a sync separation circuit for separating a sync signal from the video signal input, (4) is a serial-parallel conversion circuit, ( 5) is a parallel-serial conversion circuit 1, (6) is a memory, (7) is a reference clock oscillation circuit,
(8) and (9) are a vertical counter and a horizontal counter for instructing the address of the memory (6), (12) is a command signal of a user such as a switch, and (13) is character / pattern information with other video signals. Character superposition circuit for superposition, (1
4) is a video output terminal, (11) is an input of the command signal (12) and the sync signal from the sync separation circuit (3), and the timing and memory for counting and resetting the vertical counter (8) and the horizontal counter (9) (6) A controller for controlling reading and writing, (15) an address adder for reading the preceding and following H periods, and (16) and (17) parallelizing the data read from the preceding and following H periods. Parallel / serial conversion circuit 2 for parallel conversion, parallel / serial conversion circuit 3, (18) is parallel / serial conversion circuit 1
A first delay circuit for delaying the signal from (5), (19) parallel-serial conversion circuits 1 (15), 2 (16), 3 (17)
The first OR circuit for adding the signals of (20) and (21) is the first
Second delay circuit for delaying the signal from the OR circuit (19),
Third delay circuit, (23) second delay circuit, gate circuit for enabling output of third delay circuit, (24) first OR circuit (19), second delay circuit (20), third delay circuit A second OR circuit for adding the outputs of the circuit (21), (26) is a fixed potential for providing the luminance for the trimming, and (25) is a switch for switching between the fixed potential (26) and the input video signal.

In FIG. 1, the signal of the video signal input terminal (1) is stored in the memory (6) under the control of the controller (11) by the command signal (12), and read from the memory (6) at the time of other video input signal, The operation of adding in the character superimposing circuit (13) and outputting from the video signal output terminal (14) is the same as the conventional example. Now, in order to match the vertical screen position with the trimming signal superimposing operation at the time of reproduction described below, the vertical address at the time of writing to the memory (6) is a signal from the controller (11) as a precondition. B ₀ ) to "H"
By doing so, the value (n) +1 of the vertical counter (8) is set in the address adder (15).

When the operation mode is Borderless, the signal B ₀ from the controller (11) becomes “H”, B ₁ becomes “L” when reading the memory (6), and the vertical address value is read by the address adder (15). Numerical value of vertical counter (8) (assumed to be n) +1
Then, the data of the address that coincides with that at the time of writing is read from the memory (6). Taking the case of 8 bits as an example, the 8-bit parallel data read from the memory (6) is processed by the parallel-serial conversion circuit 1 (5).
Converted to serial data.

At this time, the control signal (X) from the controller (11) resets the parallel-serial conversion circuits 2 (16) and 3 (17), and the output becomes "L". The serial data is delayed by the first delay circuit (18) by a time corresponding to the edge (t _{1 in} FIG. 4). Here, in order to correct the difference between t ₁ at this time and one cycle of writing and reading (8 serial clocks in this example), the reading start is made 8 serial clocks + t ₁ before writing. . Next, the output of the first OR circuit (19) is output from the parallel-serial conversion circuit 1 by the operation of the control signal (X).
The serial signal from (5) remains unchanged. This serial signal is delayed by t ₁ in the second delay circuit (20) and controls the switch (25) via the second OR circuit (24). At this time, the gate circuit (23) is closed by the control signal (Y) from the controller (11) and each output is "L". Due to the above, the other video input signal is transmitted to the first delay circuit (1
The output signal of (8) (character / pattern information to be superimposed) becomes a signal of the same timing as the output signal of the second OR circuit (24) and is superimposed with a fixed potential (26) that determines the brightness of the border with the switch (25). Further, it is superimposed on the output signal of the first delay circuit (18) by the character superimposing circuit (13) and output from the video signal output terminal (14) as the same character pattern information superimposing signal without borders as in the conventional case.

When the operation mode is trimmed, the timing of reading from the memory (6) is the numerical value (n) of the vertical counter (8) at the time 1/3 before one cycle of reading as shown in FIG.
The data in the memory (6) at the +1 address is latched by the latch pulse 1 (d), and the memory at the address n at the time of 1/3 in the read cycle and the address at the address n + 2 at the time 1/3 later (6) Data are latched by latch pulses 2 and 3, respectively, and parallel / serial conversion is performed simultaneously with the next load pulse (c). Of course, at this time, the parallel / serial conversion circuit 2 is controlled by the control signal (X) from the controller (11).
(16) and 3 (17) are enabled. Of the converted serial signals, the n + 1 serial signals are delayed by the first delay circuit (18) by a predetermined amount t ₁ (horizontal trimming amount) (k in FIG. 4) and supplied to the character superimposing circuit (13). It On the other hand, the converted n + 1, n, n + 2 serial signals are the first O
It is added in the R circuit (19). This is as shown in FIG. 3, and by adding the H signals before and after the H line currently being scanned, a signal including a vertical trimming signal is obtained. Then, the output of the first OR circuit (19) is passed through the second delay circuit (20) and the third delay circuit (21) to delay each by t ₁ , and each output is delayed by the second OR circuit (24). The addition results in a signal (q in FIG. 4) that includes a horizontal trimming signal as shown in FIG. Of course, at this time, the controller (11)
The control signal (Y) from (3) controls to enable the gate circuit (23).

The other input video signal is switched (25) by the output signal of the second OR circuit (24) including the trimming signal.
Then, it is switched to a fixed potential that determines the luminance of the edge, and further superimposed on the output of the first delay circuit (k in FIG. 4) by the character superimposing circuit (13), as shown in (e) of FIG. The video signal is output from the video signal output terminal (14) as a video signal on which bordered character / pattern information is superimposed. This time,
It goes without saying that the border of arbitrary brightness can be obtained by appropriately setting the value of the fixed potential (26).

〔The invention's effect〕

As described above, according to the present invention, the first input video signal is digitized and the character / pattern information is stored in the memory, and the character / pattern information is read from the memory to obtain a new second input video signal. In a character / pattern storage / playback device that outputs a video signal by adding and superposing
An address adder that derives a signal for reading out the character / pattern information of the current time and the data of the horizontal scanning period before and after it in one addressing cycle, and a plurality of bits at a time in one addressing cycle by this address adder A readable memory, three parallel / serial conversion circuits for converting the read data of the three horizontal scanning periods into serial digital signals, and character / pattern information of the current time of the three serial digital signals A first delay circuit for delaying one serial digital signal corresponding to the above in the time axis direction, a first OR circuit for adding three serial digital signals, and a first delay circuit for delaying the signal of the first OR circuit. Second and third delay circuits for delaying the same amount as the circuit delay amount, and outputs of the second and third delay circuits are enabled. A gate circuit, a second OR circuit that adds the outputs of the first OR circuit and the outputs of the second and third delay circuits, and predetermined fixed information and the above-mentioned fixed information according to the output of the second OR circuit. Since a new second input video signal switching means is provided, a clear character / pattern information video (video) signal can be reproduced even on a screen having a low contrast between the input video (video) signal and character / pattern information.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a memory read timing diagram, FIG. 3 is a diagram showing an example of a vertical trimming signal, and FIG. 4 is an explanation of a horizontal trimming signal. FIG. 5 and FIG. 5 are diagrams of an example of title superimposition, and FIGS. 6 and 7 are a conventional configuration and a memory read timing diagram, respectively. 15: address adder, 16: parallel / serial conversion circuit 2, 17: parallel / serial conversion circuit 3, 18: first delay circuit, 19: first OR circuit, 20: second delay circuit, 21: third Delay circuit, 23: Gate circuit, 24: Second OR circuit, 25: Switch, 26: Fixed potential In the drawings, the same reference numerals indicate the same or corresponding portions.

Claims (1)

[Claims] 1. A first input video signal is digitized to store character / pattern information in a memory, and the character / pattern information is read out from this memory and added and superimposed on a new second input video signal to produce a video. Characters that output signals
In a pattern memory reproducing apparatus, an address adder for deriving a signal for reading out character / pattern information of the current time and data of horizontal scanning periods before and after the current address in one addressing cycle, and the one addressing cycle by the address adder. , A memory that can read a plurality of bits at a time, three parallel-serial conversion circuits that convert the read data of the three horizontal scanning periods into serial digital signals, and of these three serial digital signals Character of current time
The first delay circuit that delays one serial digital signal corresponding to the pattern information in the time axis direction, the first OR circuit that adds the three serial digital signals, and the signal of this first OR circuit Second and third delay circuits that delay the same amount as the delay amount of the first delay circuit, a gate circuit that enables the outputs of the second and third delay circuits, and an output of the first OR circuit, A second OR circuit for adding the outputs of the second and third delay circuits, and means for switching between the predetermined fixed information and the new second input video signal according to the output of the second OR circuit. A character / pattern storage / reproduction device characterized by being equipped with.