JPH02266771A - Character and pattern storage and reproducing device - Google Patents

Abstract

PURPOSE:To fringe and reproduce character and pattern information by reading out and synthesizing signals of preceding and succeeding horizontal scanning in one read cycle of a memory and providing a delay circuit for the direction of the time base also and providing a switching circuit for switching between another video input and a fixed potential. CONSTITUTION:An address adder 15 which reads out signals of preceding and succeeding horizontal (H) periods and parallel-serial converting circuits 16 and 17 for parallel- serial conversion of data read out in preceding and succeeding H periods are provided. Data in a memory 6 of horizontal scanning lines preceding and succeeding the current horizontal scanning line are read out approximately simultaneously by the address adder 15 and are converted into serial signals by parallel-serial converting circuits 16 and 17 and are delayed in the horizontal direction by plural delay circuits 18, 20, and 21 and are added by OR circuits 19 and 24, and the fixed potential to determine the luminance of the fringe and the input video signal are switched by a switch 25, and the fringe signal of character and pattern information is superimposed. Thus, a distinct character and pattern information video signal is reproduced with the input video signal and character and pattern information even in the case of a picture of less contrast.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a character/pattern storage/reproduction device that can store image patterns such as title characters or figures, and output them overlaid on other images. It is.

[Prior art]

In recent years, with the spread of home VTRs, the demand for home video cameras has increased, and there has been an increasing demand for home video cameras to have multiple functions, editing functions, and the like.

Among these functions, functions such as "impose" and "text bar" for inserting into titles, etc. are particularly requested.

A conventional telop device for inserting titles and the like will be described below with reference to FIG. In Figure 6, (1
) is a video signal input terminal, (2) is a detection circuit that extracts character/pattern information, (3) is a synchronization separation circuit that separates a synchronization signal from the video signal input, (4) is a serial-parallel conversion circuit, (5) is parallel-serial conversion circuit 1,
+61 is memory, (7) is reference clock oscillation circuit,
(8), (91 is a vertical counter and a horizontal counter respectively commanding the address of the memory (6), the synchronous separation circuit (3) and the transmitting circuit (3) to the vertical counter (8),
A frequency dividing circuit, α, which controls the up/down timing of the horizontal counter (9) is a controller 1. v3 is a command signal from a user such as a switch, (131 is a character superimposition circuit for superimposing text/butter/tone information with other video signals,
04J is a video signal output terminal.

First, we will explain the main flow of characters and Bakun signals. A video signal inputted through a video signal input terminal (1) is converted into a digital signal by a detection circuit (2) at the same time as a synchronization signal is created by a synchronization separation circuit (3). This digital signal is converted into an 8-bit digital signal by the serial-parallel conversion circuit (4) and is stored in the memory (
6). Furthermore, digital signals such as 8 bits, which are information such as characters and patterns stored in the memory (6), are transferred to the parallel-to-serial conversion circuit (5). This results in a serial digital signal, which is superimposed on the original video signal by the circuit bias and output to the video output terminal.

In order to realize the above operation, the oscillation circuit (
A reference clock is created in step 7), and this reference clock is supplied to the serial-to-parallel conversion circuit (4) and the parallel-to-serial conversion circuit (5) to provide conversion timing. Also 1
, this clock is divided by the frequency divider rii circuit aΦ and then supplied to the horizontal counter (9) which is the addressing counter for the lower bit/1 of the memory (6).
). The carry signal of the horizontal counter (9) is supplied to the vertical counter tel, which is an addressing counter for the upper pit of the memory (6).
Specify the address. Further, the controller circle is designated by a command signal 0 or the like from a switch or the like to write or read characters/patterns.

As a result, the controller αD includes a memory (6), a serial-to-parallel conversion circuit (4), a parallel-to-serial conversion circuit (5), a horizontal counter (9), a vertical counter (8), a frequency divider circuit a [with], an oscillation circuit ( 7) to be activated or deactivated.

The controller (controller) operates the horizontal counter (9) and vertical counter (8) at the starting point of one velvet based on the synchronization signal supplied by the synchronization separation circuit (3), and calculates the pattern on the screen. Correlation is established between the position of characters, etc. and the address of the memory (6). Here, the read operation timing from the memory will be explained.

For example, in the case of an 8-bit memory, the memory address is changed every 8 pixels with respect to the serial data clock fal corresponding to 1 bit of the memory, ie, 1 pixel, as shown in FIG. Furthermore, the parallel-to-serial conversion timing is performed by the load pulse (bl), and reading from the memory is performed during the period indicated by the launch pulse 1 (dl) until the next load pulse peak arrives.

[Problem that the invention is trying to solve]

The conventional character/pattern storage/reproduction device has been described above, but the conventional character/pattern storage/reproduction device
It was not possible to play back the pattern information with a border.

An object of the present invention is to provide a character/pattern storage/reproduction device that can store character/pattern information and reproduce it with borders in a home video camera or the like.

The purpose is to fabricate a character/pattern memory/reproduction device.

(Means for solving the problem) During one cycle read period of the memory, the previous horizontal scanning (hereinafter referred to as H) signal is also read and synthesized, a delay circuit is also provided in the time axis direction, and the signal is fixed with other video inputs. Provide a switching circuit with the potential.

[For production]

You can add borders to the memorized character/pattern information and play it back.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a character/pattern storage/reproduction device according to the present invention. In Figure 1, i
ll is a video signal input terminal, (2) is a detection circuit that extracts character/pattern information, (3) is a synchronization separation circuit that separates a synchronization signal from the video signal input, (4) is a serial-parallel conversion circuit, (5) is parallel serial conversion circuit 1
, (61 is memory, (7) is reference clock oscillation circuit, +
81. +91 is a vertical counter and a horizontal counter that respectively command the address of the memory (6), (b) is a command signal from a user such as a switch, ■ is a character superimposition circuit for superimposing character/pattern information with other video signals, a~ is the video output terminal, 0υ is the command signal side and the period separation circuit (3
) inputs the synchronization signal from the controller, and controls the count and reset timing of the vertical counter (8) and horizontal counter (9), as well as the reading and writing of the memory (6). address adder, (to), fin is a parallel-to-serial conversion circuit 2 that converts data read from the previous and following H periods into parallel to serial, and a parallel-to-serial conversion circuit 3; Ql is a parallel-to-serial conversion circuit 1. (5) is the first delay circuit that delays the signal from the parallel-to-serial converter 1 (to), the first OR circuit that adds the signals of 2Q19.3αη, @, (21) is the first A second delay circuit that delays the signal from the OR circuit (2), a third delay circuit, (2)
3) is a gate circuit that enables the outputs of the second delay circuit and third delay circuit, and (24) is a gate circuit that adds the outputs of the first OR circuit Ql, the second delay circuit (to), and the third delay circuit (21). (25) a fixed potential that provides brightness for borders; and (26) a switch that switches between the fixed potential (25) and the input video signal.

In Fig. 1, the signal of the video signal input terminal +11 is stored in the memory (6) under the control of the controller aO according to the command signal @.
The operations are the same as in the conventional example, such as storing them in the video signal, reading them out from the memory (6) at the time of other video input signals, adding them in the character superimposition circuit 0, and outputting them from the video signal output terminal (2). Now, in order to match the screen position in the vertical direction with respect to the border signal superimposition operation during playback, which will be explained next, as a precondition, the vertical address when writing to the memory (6) is the signal (Bo) from the controller aD. By setting "H" to "H", address adder α inputs the value (n
)+1.

When the operation mode is without borders, the signal Be from the controller αυ is “H” when reading from the memory (6).
, BI becomes "L", and the vertical address value is the value of the vertical counter (8) (referred to as n) + 1 in the address adder OIj.
Then, the data at the address that matches the data at the time of writing is read from the memory (6). Taking the case of 8 bits as an example, 8 bit parallel data read from the memory (6) is converted by the parallel/serial converter circuit 1 (5) as follows.
Converted to serial data.

At this time, the control signal (X) from the controller αυ causes the parallel-to-serial conversion circuits 2α1. 3αη is reset and the output becomes “L”. The serial data is delayed by the first delay circuit (2) by a time corresponding to the border (1+ in FIG. 4). Here, in order to correct the difference between t at this time and one cycle of writing and reading (in this example, 8 serial clocks), the start of reading is set 8 serial clocks t1 before writing. .

Next, the output of the first OR circuit α becomes the serial signal directly from the parallel-to-serial conversion circuit 1 (5) due to the operation of the control signal (X). This serial signal is delayed by t1 in the second delay circuit (to) and sent to the second OR circuit (24
) to control the switch (25). At this time, the gate circuit (23
) is closed and each output becomes L". Due to the fact that it is 0 or more, other video input signals are signals with the same timing as the output signal (superimposed character/pattern information) of the first delay circuit α. The output signal of the second OR circuit (24) is superimposed with the fixed potential (26) that determines the brightness of the border by the switch (25), and further superimposed with the output signal of the first delay circuit 01 in the character superimposition circuit (to). The video signal is outputted from the video signal output terminal Q41 as a character-pattern superimposed signal without borders, as in the conventional case.

When the operation mode is with border, read I from memory (6), timing is read IJ3 as shown in Figure 2.
'Loss of vertical counter (8) in 1/30 hour before cycle (
iI(n) → Latch the data in memory (6) at address -1 with latch pulse 1(d), read address n at time 173 in one read cycle, and address n+2 at 1/3 of the next cycle. The data in the address memory (6) is latched with a wrap pulse of 2.3, and then the next load pulse (0
) at the same time 6 times, and two parallel serials once a month. Of course, at this time, the control signal (X) from con)i:i-raa+)
Parallel/serial conversion circuit 2αi, 3(11
Ha4 is enabled. Among the converted serial signals, the fi -1-1 serial signal is delayed by a predetermined amount tr (horizontal fluctuation amount) in the first delay circuit tJ.
k) in FIG. 4 is supplied to the character superimposition circuit 03. - The converted serial signals of n+l+n+n"2 are added in the first OR circuit 0. This is as shown in Figure 3, and the H signals before and after the 11 lines currently being scanned are added. This results in a signal containing a vertical flapping signal.

Next, this first OR circuit α output and the second delay circuit (a)
, the third delay circuit (21) is delayed by t, respectively →
By adding the respective outputs in the second OR circuit (24), a signal (CI in FIG. 4) including a horizontal fluctuation signal is obtained as shown in FIG. Of course, at this time,
A control signal (Y) from the controller αB controls the data circuit (23) to enable it.

Other input video signals are
The output signal from the second OR circuit (24) containing The video signal 2 is superimposed with the character/pattern information shown in FIG. 5 (+(11) in FIG. At this time, it goes without saying that by appropriately setting the value of the fixed potential 26), it is possible to set the brightness at any desired level.

〔Effect of the invention〕

As described above, according to the present invention, the parallel-to-serial converter circuit reads out and adds the data of the horizontal scanning line after the current horizontal scanning line at approximately the same time using the addition l and at-Inos adder. Convert it to a serial signal, delay it horizontally using multiple delay circuits, add it using an OR circuit, and switch between the fixed potential and the input video signal using a switch.
Since the turret can be used to superimpose a border signal of text/pattern information, it is possible to reproduce a clear text/pattern information video signal even on a screen with little contrast between the input video signal and text/pattern information.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a memory read timing diagram, Fig. 3 is a diagram showing an example of a vertical border signal, and Fig. 4 is an explanation of a horizontal border signal. 5 shows an example of title weight, and FIGS. 6 and 7 show the configuration and memory read timing diagram of a conventional example, respectively. 15: Near address adder, 16: Parallel/serial conversion circuit 2.17: Parallel/serial conversion circuit 3.18:
1st delay circuit, 19: 1st OR circuit, 20: 2nd delay circuit, 21: 3rd delay circuit, 23: Gate circuit, 24:
Second OR circuit 25: switch, 26: fixed potential Note that in the figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A sync separator circuit that separates the sync signal in the input video signal, a controller that generates a timing signal based on the sync signal obtained from the sync separator circuit, and a binarizer for character/pattern information superimposed on the video signal. detection circuit,
A serial-to-parallel conversion circuit that converts this binary signal into a parallel digital signal, a memory that stores this parallel digital signal, and an address addition that reads out the previous and next horizontal scanning periods in one address designation cycle of reading from this memory. , three parallel-to-serial conversion circuits that convert the read data of the three horizontal scanning periods into serial digital signals, and one serial digital signal corresponding to character/pattern information among these three serial digital signals. a first delay circuit that delays the above three serial digital signals in the time axis direction; a first OR circuit that adds the three serial digital signals;
Add the second and third delay circuits that each delay by the same amount as the delay amount of the delay circuit, the gate circuit that enables the second and third delay circuit outputs, the first OR circuit output, and the second and third delay circuit outputs. a second OR circuit that uses the output signal of the second OR circuit to switch between another video input signal and a fixed potential; and a switching circuit that adds and superimposes the output signal of this switching circuit and the output signal of the first delay circuit for reproduction. What is claimed is: 1. A character/pattern storage/reproduction device comprising a circuit for superimposing image information such as characters/patterns and border information of this image information on an input video signal.