JPH08339955A - Pattern formation - Google Patents

Pattern formation

Info

Publication number
JPH08339955A
JPH08339955A JP7146267A JP14626795A JPH08339955A JP H08339955 A JPH08339955 A JP H08339955A JP 7146267 A JP7146267 A JP 7146267A JP 14626795 A JP14626795 A JP 14626795A JP H08339955 A JPH08339955 A JP H08339955A
Authority
JP
Japan
Prior art keywords
film
film thickness
photoresist
exposure time
optimum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP7146267A
Other languages
Japanese (ja)
Inventor
Hirobumi Fukumoto
博文 福本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP7146267A priority Critical patent/JPH08339955A/en
Publication of JPH08339955A publication Critical patent/JPH08339955A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate lowering of production efficiency caused by stoppage of a manufacturing device and much effort required for treatment by obtaining a measured film thickness value by measuring a film thickness of a workpiece film and obtaining an optimum exposure time for obtaining an optimum pattern width, based on it. CONSTITUTION: A photoresist film is formed by applying photoresist on a workpiece film formed on a substrate. A photoresist film is exposed for a specified time. A resist pattern of a specified configuration is formed by developing an exposed photoresist film. Relation between a film thickness of a workpiece film and an exposure time for obtaining an optimum pattern width is obtained and a measured film thickness value is obtained by measuring a film thickness of a workpiece film before photoresist is applied. An optimum exposure time corresponding to a measured film thickness is obtained and a specified time is set for an optimum exposure time. Thereby, an optimum exposure time is obtained without performing a treatment for a pilot substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、フォトレジスト膜を用
いるパターン形成方法に関し、特に半導体素子の作成に
おける微細加工などに有用なフォトリソグラフィを用い
たパターン形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern forming method using a photoresist film, and more particularly to a pattern forming method using photolithography which is useful for microfabrication in the production of semiconductor elements.

【0002】[0002]

【従来の技術】フォトレジスト膜を用いたパターン形成
方法においては、基板上に形成されたSiO2 膜やSi
3 4 膜等の被加工膜の膜厚の変動に起因して、フォト
レジスト膜と被加工膜との多重干渉が発生するので、被
加工膜の膜厚の変動に伴ってパターン寸法が変動すると
いう現象が確認されている。
2. Description of the Related Art In a pattern forming method using a photoresist film, a SiO 2 film or a Si film formed on a substrate is used.
Multiple interference between the photoresist film and the film to be processed occurs due to the change in the film thickness of the film to be processed such as a 3 N 4 film. Therefore, the pattern dimension varies with the film thickness of the film to be processed. It has been confirmed that the phenomenon occurs.

【0003】そこで、前述したパターン寸法の変動を解
決する方法としてパイロット処理法が知られている。
Therefore, a pilot processing method is known as a method for solving the above-mentioned variation in pattern size.

【0004】図3は、前記のパイロット処理法のフロー
チャートを示しており、まず、パイロット基板にフォト
レジスト膜を塗布した後、該フォトレジスト膜に対して
パターン露光及び現像を行ない、その後、パターン寸法
の測定を行なう。この測定結果から適正露光時間を求
め、該適正露光時間に基づいて製品ロットの半導体素子
のフォトレジスト膜に対して露光を行なうものである。
FIG. 3 shows a flow chart of the above-mentioned pilot processing method. First, a photoresist film is applied to a pilot substrate, and then the photoresist film is subjected to pattern exposure and development. Measure. The proper exposure time is obtained from the measurement result, and the photoresist film of the semiconductor element of the product lot is exposed based on the proper exposure time.

【0005】[0005]

【発明が解決しようとする課題】しかるに、前記のパイ
ロット処理法は、各製品ロット毎にパイロット基板を用
いて適正露光時間を設定するため、パイロット基板に対
する処理が終わるまで、製品ロットに対する処理を行な
うことができず、製造装置がストップして生産効率が低
下すると共に、処理に多くの労力が必要になると言う問
題がある。
However, in the above-described pilot processing method, since the proper exposure time is set by using the pilot substrate for each product lot, the product lot is processed until the pilot substrate is processed. However, there is a problem in that the manufacturing apparatus is stopped, the production efficiency is reduced, and a lot of labor is required for processing.

【0006】また、前記のパイロット処理法において
は、インライン化を行なった場合、パイロット基板に対
する適正露光時間を露光工程にフィードバックすること
はかなりな困難が伴うものと予想される。
Further, in the above-mentioned pilot processing method, it is expected that it will be considerably difficult to feed back an appropriate exposure time for the pilot substrate to the exposure process when in-line processing is performed.

【0007】前記に鑑み、本発明は、パイロット基板に
対する処理を経ることなく最適な露光時間を求め、これ
により、製造装置がストップすることに伴う生産効率の
低下を解消すると共に処理に多くの労力が必要にならな
いようにすることを目的とする。
In view of the above, the present invention seeks an optimum exposure time without performing processing on a pilot substrate, thereby eliminating the decrease in production efficiency due to the stop of the manufacturing apparatus, and much labor for processing. The purpose is not to need.

【0008】[0008]

【課題を解決するための手段】図2は、フォトレジスト
膜の膜厚が1.22μmのときの被加工膜であるSiO
2 の膜厚とパターン寸法との関係を示している。図2か
ら、フォトレジスト膜の膜厚の変動がなくても、被加工
膜の膜厚が変化するとパターン寸法がサインカーブで変
化することが分かる。
FIG. 2 shows a SiO 2 film to be processed when the thickness of the photoresist film is 1.22 μm.
2 shows the relationship between the film thickness of 2 and the pattern size. From FIG. 2, it can be seen that even if the film thickness of the photoresist film does not change, the pattern dimension changes as a sine curve when the film thickness of the processed film changes.

【0009】半導体素子の製造プロセスにおいて、被加
工膜の膜厚は製品ロット間において一定ではない。これ
は、主として、基板上に被加工膜をデポジションするC
VD装置が枚葉式でなくバッチ式であるためと考えられ
る。
In the manufacturing process of semiconductor devices, the film thickness of the film to be processed is not constant between product lots. This is mainly C for depositing the film to be processed on the substrate.
It is considered that the VD device is a batch type rather than a single-wafer type.

【0010】前記2つの理由により、製品ロット毎にパ
イロット処理を行なわざるを得ないと考えられる。
Due to the above two reasons, it is considered that the pilot process must be performed for each product lot.

【0011】そこで、本件発明者は、被加工膜の膜厚と
最適なパターン幅が得られる露光時間との関係を予め求
めておくと共に、被加工膜の膜厚を予め測定しておき、
被加工膜の膜厚の測定値に基づき露光時間を設定する
と、最適な露光時間が得られることを見い出し、該知見
に基づき本発明を想到するに至ったものである。
Therefore, the inventor of the present invention obtains the relationship between the film thickness of the film to be processed and the exposure time for obtaining the optimum pattern width in advance, and measures the film thickness of the film to be processed in advance.
It was found that the optimum exposure time can be obtained by setting the exposure time based on the measured value of the film thickness of the film to be processed, and the present invention has been devised based on the finding.

【0012】具体的に請求項1の発明が講じた解決手段
は、パターン形成方法を、基板上に形成された被加工膜
の上にフォトレジストを塗布してフォトレジスト膜を形
成するフォトレジスト膜形成工程と、前記フォトレジス
ト膜に対して所定時間の露光を行なう露光工程と、露光
されたフォトレジスト膜を現像して所定形状のレジスト
パターンを形成するパターン形成工程とを備え、前記露
光工程は、被加工膜の膜厚と最適なパターン幅が得られ
る露光時間との関係を求めておくと共に、前記フォトレ
ジストを塗布する前の被加工膜の膜厚を測定して測定膜
厚値を求めておき、前記関係から前記測定膜厚値と対応
する最適露光時間を求め、前記所定時間を前記最適露光
時間に設定する工程を有している構成とするものであ
る。
[0012] Specifically, the solution means taken by the invention of claim 1 is a pattern forming method, wherein a photoresist is applied on a film to be processed formed on a substrate to form a photoresist film. The exposure step includes a forming step, an exposure step of exposing the photoresist film for a predetermined time, and a pattern forming step of developing the exposed photoresist film to form a resist pattern having a predetermined shape. The relationship between the film thickness of the film to be processed and the exposure time for obtaining the optimum pattern width is obtained, and the film thickness of the film to be processed before applying the photoresist is measured to obtain the measured film thickness value. In addition, it is configured to have a step of obtaining an optimum exposure time corresponding to the measured film thickness value from the relationship and setting the predetermined time to the optimum exposure time.

【0013】請求項2の発明は、前記最適露光値を正確
にするべく、請求項1の構成に、前記フォトレジスト膜
形成工程は、前記フォトレジスト膜の膜厚が目標膜厚値
に対して±5nm以内の範囲内になるよう前記フォトレ
ジストを塗布する工程を有している構成を付加するもの
である。
According to a second aspect of the present invention, in order to make the optimum exposure value accurate, in the structure of the first aspect, in the photoresist film forming step, the film thickness of the photoresist film with respect to the target film thickness value is set. A structure having a step of applying the photoresist so as to be within a range of ± 5 nm is added.

【0014】[0014]

【作用】請求項1の構成により、被加工膜の膜厚と最適
なパターン幅が得られる露光時間との間には一定の関係
があるので、被加工膜の膜厚を測定して測定膜厚値を求
め、該測定膜厚値と前記の関係とから露光時間を求める
と、該露光時間は最適なパターン幅が得られる最適露光
時間になる。
According to the structure of claim 1, there is a fixed relationship between the film thickness of the film to be processed and the exposure time for obtaining the optimum pattern width. When the thickness value is obtained and the exposure time is obtained from the measured film thickness value and the above relationship, the exposure time becomes the optimum exposure time for obtaining the optimum pattern width.

【0015】請求項2の構成により、フォトレジスト膜
の膜厚が目標膜厚値に対して±5nm以内の範囲内であ
るため、被加工膜の膜厚と最適なパターン幅が得られる
露光時間との間の関係をより細かく且つ正確に求めるこ
とができる。
According to the structure of claim 2, the film thickness of the photoresist film is within ± 5 nm with respect to the target film thickness value, so that the film thickness of the film to be processed and the optimum pattern width are obtained. The relationship between and can be obtained more finely and accurately.

【0016】[0016]

【実施例】以下、本発明の一実施例に係るパターン形成
方法を図1のフローチャートを参照しながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A pattern forming method according to an embodiment of the present invention will be described below with reference to the flowchart of FIG.

【0017】まず、ステップ1において、シリコン基板
上にデポジションされた被加工膜、例えばシリコン酸化
膜(以下、SiO2 膜と称する)の膜厚を測定して測定
膜厚値を得る。
First, in step 1, the film thickness of a film to be processed, for example, a silicon oxide film (hereinafter referred to as a SiO 2 film) deposited on a silicon substrate is measured to obtain a measured film thickness value.

【0018】次に、ステップ2において、前記SiO2
膜の上にフォトレジスト膜を1.22μmの膜厚に塗布
する。ここでは、i線用のライトダイ入りフォトレジス
トのような中反射基板用のレジストを用いている。
Next, in step 2, the SiO 2
A photoresist film having a thickness of 1.22 μm is applied on the film. Here, a resist for a medium-reflection substrate such as a photoresist for a light die for i-line is used.

【0019】次に、ステップ3において、シリコン基板
上にデポジションされたSiO2 膜の膜厚と露光時間と
の関係から最適露光時間を設定する。図2は、厚さ1.
22μmのフォトレジスト膜をSiO2 膜上に塗布した
後、SiO2 膜の膜厚を200nm〜350nmの間で
変化させたときのパターン寸法の変化を示している。図
2から明らかなように、目標寸法が0.5μmのライン
パターンにおけるSiO2 膜の膜厚においては、最大で
0.12μmのパターン変化(ΔP)が観察される。
Next, in step 3, the optimum exposure time is set from the relationship between the film thickness of the SiO 2 film deposited on the silicon substrate and the exposure time. FIG. 2 shows the thickness 1.
After the photoresist film 22μm was coated on the SiO 2 film, it shows a change in pattern size when changing the film thickness of the SiO 2 film between 200 nm to 350 nm. As is apparent from FIG. 2, a maximum pattern change (ΔP) of 0.12 μm is observed in the thickness of the SiO 2 film in the line pattern having the target dimension of 0.5 μm.

【0020】[0020]

【表1】 [表1]は図2のデータを基にSiO2 膜の膜厚を30
0nm〜340nmの間で5nm毎に変化させたときの
0.5μmラインパターン形成に必要な露光時間を示し
ている。ここで、被加工基板上にデポジションしたSi
2 膜の目標膜厚は320nmであり、この膜厚のとき
の最適露光時間は360msecである。[表1]に示
すように、0.5μmラインパターンを形成する最適露
光時間は、SiO2 膜の膜厚の変化に伴って変動するこ
とが分かる。SiO2 膜の膜厚と最適露光時間との関係
をデータベースにして、シリコン基板上にデポシジョン
されたSiO2 膜の膜厚をモニターすることにより、最
適露光時間を設定することができる。
[Table 1] [Table 1] shows that the thickness of the SiO 2 film is 30 based on the data of FIG.
The exposure time required for forming a 0.5 μm line pattern when changing every 5 nm between 0 nm and 340 nm is shown. Here, Si deposited on the substrate to be processed
The target film thickness of the O 2 film is 320 nm, and the optimum exposure time for this film thickness is 360 msec. As shown in [Table 1], it can be seen that the optimum exposure time for forming the 0.5 μm line pattern varies with the change in the film thickness of the SiO 2 film. And the relationship between the film thickness and the optimal exposure time of the SiO 2 film in the database, by monitoring the thickness of Deposhijon been SiO 2 film on the silicon substrate, it is possible to set the optimum exposure time.

【0021】次に、ステップ4において、シリコン基板
上のフォトレジスト膜に対して前記の最適露光時間の露
光を行なった後、現像を行なう。
Next, in step 4, the photoresist film on the silicon substrate is exposed for the optimum exposure time and then developed.

【0022】以上説明したように、本発明のパターン形
成方法は、パイロット処理省略方法を採用しているた
め、従来のパイロット処理方法と比較して、製造装置が
ストップすることによる生産効率の低下を抑制できると
共に、パイロット処理の手順に多くの労力をかける必要
がなくなる。
As described above, since the pattern forming method of the present invention adopts the pilot processing omission method, the production efficiency is reduced due to the stop of the manufacturing apparatus as compared with the conventional pilot processing method. It can be suppressed and does not require much effort on the pilot procedure.

【0023】また、本発明のパターン形成方法は、シリ
コン基板上にデポジションされた膜がSiO2 膜ではな
く、例えばSi3 4 膜等のように、フォトレジストと
多重干渉が発生するような膜をシリコン基板上にデポジ
ションする場合に有効に活用できる。
Further, in the pattern forming method of the present invention, the film deposited on the silicon substrate is not the SiO 2 film but is a Si 3 N 4 film or the like, which causes multiple interference with the photoresist. It can be effectively used when depositing a film on a silicon substrate.

【0024】[0024]

【発明の効果】請求項1の発明に係るパターン形成方法
によると、被加工膜の測定膜厚値と、被加工膜の膜厚と
最適なパターン幅が得られる露光時間との間の関係とか
ら求められる露光時間は、最適なパターン幅が得られる
最適露光時間であるため、パイロット基板に対する処理
を経ることなく最適な露光時間が求められるので、製造
装置がストップすることに伴う生産効率の低下を解消で
きると共にパターン形成処理に要する労力を低減するこ
とができる。
According to the pattern forming method of the first aspect of the present invention, the relationship between the measured film thickness value of the film to be processed and the film thickness of the film to be processed and the exposure time at which the optimum pattern width is obtained. Since the exposure time required from is the optimum exposure time to obtain the optimum pattern width, the optimum exposure time is required without processing the pilot substrate. And the labor required for the pattern forming process can be reduced.

【0025】請求項2の構成により、被加工膜の膜厚と
最適なパターン幅が得られる露光時間との間の関係をよ
り細かく且つ正確に求められるので、前記の関係から求
められる最適露光時間もより正確なものになる。
According to the structure of claim 2, since the relationship between the film thickness of the film to be processed and the exposure time for obtaining the optimum pattern width can be obtained more finely and accurately, the optimum exposure time obtained from the above relation can be obtained. Will also be more accurate.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係るパターン形成方法を示
すフローチャート図である。
FIG. 1 is a flowchart showing a pattern forming method according to an embodiment of the present invention.

【図2】基板上にデポジションされたSiO2 の膜厚と
パターン寸法との関係を示す図である。
FIG. 2 is a diagram showing a relationship between a film thickness of SiO 2 deposited on a substrate and a pattern dimension.

【図3】従来のパターン形成方法を示すフローチャート
図である。
FIG. 3 is a flowchart showing a conventional pattern forming method.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板上に形成された被加工膜の上にフォ
トレジストを塗布してフォトレジスト膜を形成するフォ
トレジスト膜形成工程と、 前記フォトレジスト膜に対して所定時間の露光を行なう
露光工程と、 露光されたフォトレジスト膜を現像して所定形状のレジ
ストパターンを形成するパターン形成工程とを備え、 前記露光工程は、被加工膜の膜厚と最適なパターン幅が
得られる露光時間との関係を求めておくと共に、前記フ
ォトレジストを塗布する前の被加工膜の膜厚を測定して
測定膜厚値を求めておき、前記関係から前記測定膜厚値
と対応する最適露光時間を求め、前記所定時間を前記最
適露光時間に設定する工程を有していることを特徴とす
るパターン形成方法。
1. A photoresist film forming step of forming a photoresist film by coating a photoresist on a film to be processed formed on a substrate, and an exposure step of exposing the photoresist film for a predetermined time. And a pattern forming step of developing the exposed photoresist film to form a resist pattern of a predetermined shape, wherein the exposing step includes a film thickness of a film to be processed and an exposure time for obtaining an optimum pattern width. Is obtained, and the film thickness of the film to be processed before applying the photoresist is measured to obtain a measured film thickness value, and the optimum exposure time corresponding to the measured film thickness value is calculated from the relationship. A method for forming a pattern, comprising the step of obtaining and setting the predetermined time to the optimum exposure time.
【請求項2】 前記フォトレジスト膜形成工程は、前記
フォトレジスト膜の膜厚が目標膜厚値に対して±5nm
以内の範囲内になるよう前記フォトレジストを塗布する
工程を有していることを特徴とする請求項1に記載のパ
ターン形成方法。
2. In the photoresist film forming step, the film thickness of the photoresist film is ± 5 nm with respect to a target film thickness value.
The pattern forming method according to claim 1, further comprising a step of applying the photoresist so as to be within the range.
JP7146267A 1995-06-13 1995-06-13 Pattern formation Withdrawn JPH08339955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7146267A JPH08339955A (en) 1995-06-13 1995-06-13 Pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7146267A JPH08339955A (en) 1995-06-13 1995-06-13 Pattern formation

Publications (1)

Publication Number Publication Date
JPH08339955A true JPH08339955A (en) 1996-12-24

Family

ID=15403879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7146267A Withdrawn JPH08339955A (en) 1995-06-13 1995-06-13 Pattern formation

Country Status (1)

Country Link
JP (1) JPH08339955A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4508457B2 (en) * 2000-04-06 2010-07-21 三星電子株式会社 Exposure time adjustment system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4508457B2 (en) * 2000-04-06 2010-07-21 三星電子株式会社 Exposure time adjustment system

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