JPH08335589A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To reduce a parasitic capacitance produced between a gate electrode which has an approximately T-shaped cross section and a channel region and improve the high frequency characteristics of a field effect transistor. CONSTITUTION: A semiconductor device 1 has a gate electrode 21 which is provided on the channel region 12 of a semiconductor substrate 11, has overhangs 22 on both sides of its upper part and has an approximately T-shaped cross section, source/drain regions 23 and 24 which are formed in the upper layer of the semiconductor substrate 11 on both sides of the gate electrode 21 and source/drain electrodes 25 and 26 which are connected to the source/drain regions 23 and 24. In the semiconductor device 1, a nearly vacuum state enclosed spaces 27 and 28 are provided at least between the semiconductor substrate 11 and the overhangs 22 of the gate electrode 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention In a field effect transistor having a so-called mushroom-shaped gate electrode having a substantially T-shaped cross section, the present invention has reduced the parasitic capacitance generated between the upper portion of the mushroom-shaped gate electrode and the channel region. The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002]

2. Description of the Related Art Basics of GaAs field effect transistor,
(1992) Masumi Fukuda, Yasutake Hirachi (Corona) p. 59
As disclosed in -60, in the field effect transistor, the gate electrode is formed of a so-called mushroom type (or T type) gate electrode in order to prevent an increase in the gate resistance due to the miniaturization of the gate length. . This gate electrode is formed by forming a thin contact portion with the channel which becomes the gate length and forming a thick upper portion of the gate electrode in order to reduce the gate resistance.

[0003]

However, as shown in FIG. 6, in the field effect transistor 60 having the mushroom-shaped gate electrode 61, the gate electrode 61 is used.
The parasitic capacitance CG between the upper part 62 and the semiconductor substrate 63
There is a problem that the high frequency characteristics of the field effect transistor 60 are deteriorated by S and CGD.

[0004]

SUMMARY OF THE INVENTION The present invention is a semiconductor device and a method of manufacturing the same which are made to solve the above problems. A semiconductor device includes a gate electrode having a substantially T-shaped cross section, which is provided on a channel region formed on a semiconductor substrate and has projecting portions on both upper sides thereof, and source / drain regions formed on the semiconductor substrate on both sides of the gate electrode. A semiconductor device having a source / drain electrode connected to the semiconductor device, wherein at least a closed space is provided between the semiconductor substrate and the protruding portion of the gate electrode.

In the method of manufacturing a semiconductor device, in the first step, a gate electrode having a substantially T-shaped cross section having overhang portions on both upper sides is formed on a channel region of the semiconductor substrate, and then the gate electrode is formed on the semiconductor substrate. After forming the first insulating film for covering, etching back is performed to expose the upper portion of the gate electrode. Then, in a second step, a second insulating film is formed to cover the exposed upper part of the gate electrode, and in a third step, a resist film is formed on the second insulating film, and then a region where the source / drain electrodes are formed is formed. A first opening is opened in the resist film to form a resist pattern. Then, in the fourth step, the second insulating film is etched from the first opening to form the second opening, and then in the fifth step,
The first insulating film up to the gate electrode is removed from the second opening.
Then, in a sixth step, after depositing a metal for electrodes and closing the second opening, the resist pattern is removed and the metal for electrodes on the resist pattern is removed to form source / drain electrodes.

[0006]

In the above semiconductor device, the channel region formed in the semiconductor substrate and the cross section T having the protruding portions on both sides of the upper portion are formed.
Since the closed space is provided between the gate electrode and the projecting portion of the gate electrode, the dielectric constant therebetween is reduced, and the parasitic capacitance is reduced.

In the above manufacturing method, after the first insulating film covering the gate electrode having a substantially T-shaped cross section is formed on the semiconductor substrate,
A second insulating film is formed after exposing the upper part of the gate electrode. Then, after forming the second opening in the second insulating film,
By removing the first insulating film up to the gate electrode from the opening, a space is formed between the channel region and the projecting portion. Further, the electrode metal is deposited by the vapor deposition method to close the second opening, and then the resist pattern is removed and the electrode metal on the resist pattern is removed to form the source / drain electrodes. Department is the source
Blocked by the drain electrode. Therefore, the space is closed by the channel region, the source / drain electrodes, the second insulating film, and the gate electrode.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the schematic sectional view of FIG.

As shown in FIG. 1, a channel region 12 is formed on the front surface side of the semiconductor substrate 11, and a gate electrode 21 is formed on the channel region 12. The gate electrode 21 has a substantially T-shaped cross section with protrusions 22 provided on both sides of the upper portion. The semiconductor substrate 11 on both sides of the channel region 12 has source / drain regions 23,
24 are formed. The field effect transistor is formed as described above.

Further, the source / drain regions 23, 24
A first insulating film 31 is formed on the semiconductor substrate 11 except above and on the channel region 12. Further, the second insulation is formed on the semiconductor substrate 11 so as to form spaces on the source / drain regions 23 and 24 and the channel region 12 and to connect to the upper part of the first insulating film 31 and the upper part of the gate electrode 21. The film 32 is formed. Openings 33, 34 are formed in the second insulating film 32 on the source / drain regions 23, 24, and the openings 33, 34 are formed.
And the source / drain regions 23, 2
Source in the state of connecting to 4 (for example, ohmic connection)
Drain electrodes 25 and 26 are formed.

Therefore, the above space (hereinafter, the closed space 2
7 and 28) are formed by the channel region 12, the gate electrode 21, the second insulating film 32, and the source / drain electrodes 25 and 26 formed on the semiconductor substrate 11. The closed spaces 27, 28 are in a substantially vacuum state, and the pressure of the atmosphere is, for example, about 10 μPa or less.

In the semiconductor device 1, the closed spaces 27 and 28 between the channel region 12 formed in the semiconductor substrate 11 and the overhanging portion 22 of the gate electrode 21 are almost in a vacuum state.
Since the above is provided, the dielectric constant between them is close to 1. Therefore, the channel region 12 and the overhanging portion 22
The parasitic capacitance between and becomes small. Therefore, the high frequency characteristics of the transistor are improved by about 30% as compared with, for example, a transistor in which the silicon oxide film is embedded between the gate electrode and the channel region.

Next, an example of a method of manufacturing the field effect transistor having the gate electrode having a substantially T-shaped cross section will be described with reference to the manufacturing process chart of FIG. In the figure, the same components as those described in FIG. 1 are designated by the same reference numerals.

As shown in FIG. 2A, the channel region 12 is formed on the front surface side of the semiconductor substrate 11 by, for example, an ion implantation method. Next, a resist is applied on the semiconductor substrate 11 to form the first resist film 51, and then the first resist film 51 is exposed (for example, electron beam exposure), developed, baked, etc.
For example, the first resist pattern 53 is formed by opening the first resist opening 52 having a maximum size of about 0.2 μm.

Next, as shown in (2) of FIG.
After forming a second resist film 54 by applying a resist having a developability different from that of the resist film 51, the second resist film 54 having a maximum of about 0.6 μm is formed by exposure (for example, i-line reduction projection exposure), development and baking. A second resist pattern 56 is formed by opening the resist opening 55 so that the first resist opening 52 is exposed.

Subsequently, as shown in FIG. 2C, a gate metal 57 is deposited by a vapor deposition method to fill the first resist opening 52 with the gate metal 57 and to
The gate metal 57 is embedded up to the middle of the resist opening 55. At that time, the gate metal 57 is also deposited on the second resist pattern 56.

Then, by the lift-off method,
By removing the second resist patterns 53 and 56, as shown in (4) of FIG. 2, the so-called mushroom-shaped gate electrode 21 having a substantially T-shaped cross section with an overhang 22 is completed. The size of the gate electrode 21 is
For example, the height h from the channel region 12 to the lower surface of the overhang 22 is 0.1 μm, the gate length Lg is 0.2 μm,
The thickness t of the overhanging portion 22 above the gate electrode 21 is t = 0.
The length is 4 μm and the length Lc in the gate length direction is 0.6 μm. After that, a source layer is formed on the upper layer of the semiconductor substrate 11 on both sides of the gate electrode 21 by ion implantation, for example.
Drain regions 23 and 24 are formed.

Next, a first embodiment of the method of manufacturing the semiconductor device 1 of the present invention will be described with reference to manufacturing process diagrams (No. 1) and (No. 2) of FIGS. In the figure, the same components as those described in FIG. 1 are designated by the same reference numerals.

First, in the first step, as shown in (1) of FIG. 3, by the step described in FIG.
1 is formed on the channel region 12 of the semiconductor substrate 11.
After that, for example, a polyimide resin is applied to the semiconductor substrate 11 to a thickness of 0.8 μm to form a first insulating film 31 that covers the gate electrode 21. Source / drain regions 23 and 24 are formed in the upper layer of the semiconductor substrate 11 on both sides of the gate electrode 21.

Subsequently, as shown in (2) of FIG. 3, the first insulating film 31 is ashed (ashed) in oxygen plasma to etch back the first insulating film 31 to form an upper portion of the gate electrode 21. Expose. In the etching back at this time, the first insulating film 31 is left with a thickness of 0.3 μm. As a result, the gate electrode 21 is removed from the first insulating film 31 to 0.2
Expose about μm.

Next, as shown in FIG. 3C, the second step is performed. In this step, the second insulating film 32 that covers the upper portion of the gate electrode 21 exposed on the first insulating film 31 is formed. The second insulating film 32 is formed, for example, by plasma chemical vapor deposition (hereinafter, chemical vapor deposition is referred to as CVD.
It is formed by depositing a silicon nitride film to a thickness of 0.2 μm by the chemical vapor deposition method.

Subsequently, a third step shown in FIG. 3D is performed. In this step, a resist is applied on the second insulating film 32 to form a resist film 41, and then exposure, development, baking, etc. are performed to form a resist film 41 in the region where the source / drain electrodes are formed. The first opening 42,
43 is opened to form a resist pattern 44.

Then, a fourth step shown in FIG. 4A is performed. In this step, the second insulating film 32 is etched from the first opening portions 42 and 43 by etching, for example, reactive ion etching, and the second opening portion (opening in FIG. 1) is formed in the second insulating film 32. (Corresponding to parts 33 and 34)
35 and 36 are formed.

Then, the fifth step shown in FIG. 4B is performed. In this step, the first insulating film 31 under the second insulating film 32 is etched through the second openings 35 and 36 with an organic alkaline solvent [eg, tetramethylammonium hydroxide (TMAH)], and the gate electrode 2 is removed.
Retreat to side 1. At this time, the etching of the first insulating film 31 also proceeds on the side opposite to the gate electrode 21. Further, the first insulating film 31 is removed by ashing in oxygen plasma until the side portion of the gate electrode 21 is completely exposed. In this ashing, since the ashing is performed in the direction in which the opening diameters of the first opening portions 42 and 43 of the resist pattern 44 increase, the opening diameter increases. Here, since the first insulating film 31 is previously etched by the organic alkaline solvent, the resist pattern 44 on the gate electrode 21 remains.

Thereafter, the sixth step shown in FIG. 4C is performed. In this step, the electrode metal 45 is deposited by the vapor deposition method so that the first openings 42 and 43 of the resist pattern 44 are substantially filled and the second openings 35 and 36 are filled. Then an organic solvent (eg acetone)
By the lift-off method in
4 is removed, and the electrode metal 45 deposited on the resist pattern 44 is removed. As a result, as shown in (4) of FIG. 4, the source / drain electrodes 25 and 26 are formed from the remaining electrode metal (45).

Although polyimide is used as the first insulating film 31 and silicon nitride is used as the second insulating film 32 in the above description, it is possible to etch the first insulating film 31 using the second insulating film 32 as a mask. If so, the film types of the first and second insulating films 31 and 32 are not limited to the above. For example,
It is also possible to use silicon nitride for the first insulating film 31 and silicon oxide for the second insulating film 32. In this case, sulfur hexafluoride (SF ₆ ) is used as an etching gas to form the second openings 33 and 34 in the second insulating film 32, and the first insulating film 31 is further etched, A similar process is possible.

The first insulating film 31 made of polyimide
Is performed by two processes of etching with an organic alkali solvent and ashing in oxygen plasma. However, it is also possible to perform the etching with only an organic alkali solvent. However, this process requires separate ashing for enlarging the first openings 42, 43 of the resist pattern 44. The resist pattern 44 is formed to have a thickness sufficient to remain in the thickness direction even after ashing.

According to the first embodiment described above, the semiconductor substrate 11
A so-called mushroom-shaped gate electrode 21 having a substantially T-shaped cross section is provided on the channel region 12 formed in the above. The source / drain electrode (source electrode) 25 and the source / drain electrode ( A drain electrode) 26 is formed. Moreover, the space between the gate electrode 21 and the source / drain electrodes 25 and 26 is the semiconductor substrate 1
The closed space 27 is closed by the first and second insulating films 32, the gate electrode 21, and the source / drain electrodes 25 and 26. Since this closed space has a pressure atmosphere almost equal to the vacuum deposition atmosphere, the pressure is 10 μPa or less, and the space is almost in a vacuum state. As a matter of course,
If the vacuum deposition atmosphere has a lower pressure, the state of the closed space 27 also has a higher vacuum. Since the field effect transistor having such a structure is obtained, the dielectric constant between the overhanging portion 22 and the channel region 12 can be reduced, and the generation of parasitic capacitance can be suppressed.

Here, the capacitance between the opposing electrodes will be examined. The capacitance between the electrodes facing each other is expressed by the equation (1).

[0030]

## EQU1 ## C = ε S / d (1) (where C is capacitance, ε is dielectric constant, S is electrode area,
d represents the distance between the electrodes. )

Assuming that the vacuum permittivity is ε ₀ , the permittivity of a silicon nitride film, which is a material usually used as an interlayer insulating film, is ε _SiN = 7.5 ε ₀ , and the permittivity ε of a silicon oxide film is ε ₀ . _SiO2 = 3.9ε ₀ . Therefore, by setting the atmosphere between the gate electrode 21 and the channel region 12 in a nearly vacuum atmosphere (state in which the dielectric constant is close to 1), it is possible to significantly reduce the parasitic capacitance 2 and obtain good high frequency characteristics. To be

Next, a second embodiment will be described with reference to the manufacturing process chart of FIG. In the figure, the same components as those described in the first embodiment of the manufacturing method are designated by the same reference numerals.

The second embodiment is a method of forming the source / drain electrodes 25 and 26 by dry etching instead of the lift-off method in the first embodiment.
That is, up to FIG. 4A of the first embodiment is the same as the above description.

After that, as shown in FIG. 5A, after forming the second openings 35 and 36 in the second insulating film 32, as a fifth step, a resist pattern 44 (portion indicated by a chain double-dashed line) is formed. Remove in organic solvent (eg acetone).

Next, as shown in FIG. 5B, the first insulating film 31 under the second insulating film 32 is made to recede at least to the gate electrode 21 side by ashing in oxygen plasma, and the side portion of the gate electrode 21 is removed. Stops when it is completely exposed. In this ashing, the first insulating film 31 is also etched in the direction opposite to the gate electrode 21.

Next, a sixth step shown in FIG. 5C is performed. In this step, 0.8 μm of electrode metal 45 for forming source / drain electrodes is formed on the entire surface by vapor deposition.
Deposit to a thickness of about m. At this time, the electrode metal 45 is deposited so as to be connected (ohmic connection) to the source / drain regions 23 and 24.

Thereafter, as shown in (4) of FIG. 5, a resist pattern 46 is formed on the deposited electrode metal 45 by an ordinary lithography technique in which resist coating, exposure, development and baking are performed. Subsequently, the deposited electrode metal 4 is formed by etching (for example, dry etching) using the resist pattern 46 as a mask.
The portion indicated by the two-dot chain line of 5 is removed, and the source / drain electrodes 25 connected to the source / drain regions 23, 24
26 is formed.

Although not shown, the resist pattern 46 is then removed with an organic solvent (eg acetone). In this way, a structure similar to that of the first embodiment can be obtained.

As described above, also in the second embodiment, the same structure as that of the first embodiment can be obtained, so that the same effect as that described in the first embodiment can be obtained. Further, in the manufacturing method of the second embodiment, after removing the resist pattern 44, ashing for retracting the first insulating film 31 is performed, so that it is possible to set the ashing time with a margin.
Therefore, the process can be stabilized.

The manufacturing method described in the first and second embodiments can be applied to all field effect transistors having the gate electrode 21 having a substantially T-shaped cross section.

[0041]

As described above, according to the semiconductor device of the present invention, a field effect transistor having a channel region formed in a semiconductor substrate and a gate electrode having a substantially T-shaped cross section with protrusions on both upper sides. Since the closed space is provided between the gate electrode and the projecting portion of the gate electrode, it is possible to reduce the dielectric constant therebetween and reduce the parasitic capacitance. Therefore, the high frequency characteristics of the semiconductor device can be improved.

According to the manufacturing method of the present invention, the first insulating film is formed in such a manner that the upper portion of the gate electrode having the eaves-like portion formed on the channel region of the semiconductor substrate and having a substantially T-shaped cross section is exposed. Then, the second insulating film is formed, the second opening is formed in the second insulating film, and then the first insulating film is removed from the second opening to the gate electrode. A space is formed in. Furthermore, since the source / drain electrodes are formed after the electrode metal is deposited by the vapor deposition method to close the second opening, the second opening can be closed by the source / drain electrode. Therefore, the space can be formed in a closed state by the channel region, the source / drain electrodes, the second insulating film, and the gate electrode.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a manufacturing process diagram of a gate electrode.

FIG. 3 is a manufacturing process diagram (1) of the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram (2) of the first embodiment of the present invention.

FIG. 5 is a manufacturing process drawing of the second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a problem.

[Explanation of symbols]

 1 Semiconductor Device 11 Semiconductor Substrate 12 Channel Region 21 Gate Electrode 22 Overhang 23 Source / Drain Region 24 Source / Drain Region 25 Source / Drain Electrode 26 Source / Drain Electrode 27 Closed Space

Claims (5)

[Claims] 1. A gate electrode having a substantially T-shaped cross section, which is provided on a channel region formed on a semiconductor substrate and has protrusions on both sides of an upper portion, and source / drain formed on the semiconductor substrate on both sides of the gate electrode. A semiconductor device comprising a region and a source / drain electrode connected to the source / drain region, characterized in that a closed space is provided at least between the semiconductor substrate and the protruding portion of the gate electrode. apparatus. 2. The semiconductor device according to claim 1, wherein the closed space is in a substantially vacuum state. 3. The semiconductor device according to claim 1, wherein the closed space includes the semiconductor substrate, the gate electrode, an insulating film formed so as to cover the gate electrode, and the semiconductor film from the surface of the insulating film. A semiconductor device, comprising: the source / drain electrodes reaching the source / drain regions of a substrate. 4. A gate electrode having protruding portions on both sides of an upper portion and having a substantially T-shaped cross section is formed on a channel region formed on the semiconductor substrate, and then a gate electrode is formed on the semiconductor substrate in a state of covering the gate electrode. A first step of forming a first insulating film and subsequently etching back the first insulating film to expose an upper portion of the gate electrode; and a second step of covering the exposed upper portion of the gate electrode on the first insulating film. A second step of forming an insulating film; a resist film formed on the second insulating film;
A third step of forming a resist pattern by forming a first opening in the resist film in a region where a drain electrode is formed; and etching the second insulating film from the first opening to form the second insulating film. A fourth step of forming a second opening in the first opening, a fifth step of removing the first insulating film from the second opening to the gate electrode, and a second metal opening for depositing the second opening. After closing, the sixth step of removing the resist pattern and forming a source / drain electrode with the electrode metal left by removing the electrode metal on the resist pattern. Device manufacturing method. 5. A gate electrode having protruding portions on both sides of an upper portion and having a substantially T-shaped cross section is formed on a channel region formed on the semiconductor substrate, and then, a gate electrode is formed on the semiconductor substrate in a state of covering the gate electrode. A first step of forming a first insulating film and subsequently etching back the first insulating film to expose an upper portion of the gate electrode; and a second step of covering the exposed upper portion of the gate electrode on the first insulating film. A second step of forming an insulating film; a resist film formed on the second insulating film;
A third step of forming a resist pattern by opening a first opening in the resist film in a region where a drain electrode is formed; and etching the second insulating film from the first opening to form the second insulating film. A fourth step of forming a second opening in the first step, and a fifth step of removing the first insulating film from the second opening to the gate electrode after removing the resist pattern
And a step of depositing a metal for an electrode by a vapor deposition method to block the second opening, forming a resist pattern on the deposited metal film for an electrode, and then performing etching using the resist pattern as a mask. And a sixth step of forming the source / drain electrodes by removing the metal film for electrodes described above.