JPH08331757A - Overcurrent limiting circuit - Google Patents

Abstract

PURPOSE: To detect an overcurrent of a semiconductor element to be protected and thereby to prevent oscillation during a feedback control by a method wherein an output current of an overcurrent detecting circuit is turned back, an output current of a power transistor drive circuit is extracted in accordance with the turn-back current and thereby the feedback control is conducted so that a power transistor may be brought into an off-state. CONSTITUTION: When a load impedance lowers as is the case with short- circuiting of a load and an output current of power FET (transistor) 10 and a current thereof for detection increase and when the current flowing into an overcurrent detecting circuit 14 from a terminal 10b for current detection of the power FET 10 exceeds a reference current flowing through a second reference current source 142 (i.e., in an overcurrent), this is detected by the overcurrent detecting circuit 14 and an output current from the overcurrent detecting circuit 14 is turned back by a current mirror circuit 16. This turn-back current flows to a resistance element 17, an output current of a power FET drive circuit 13 is thereby extracted to a grounding node and the power FET 10 is subjected to a feedback control so that it may be brought into an off-state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overcurrent limiting circuit for detecting and protecting an overcurrent of a semiconductor device, and more particularly, it is formed on the same chip as a voltage-driven power transistor having a multi-cell structure. The present invention relates to an overcurrent limiting circuit.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional example of an overcurrent limiting circuit of a power MOSFET (insulated gate type field effect transistor) formed in an integrated circuit (IC). In FIG.
Reference numeral 10 is a DMOS (double diffusion type) power FET having a multi-source structure (first source 10a, second source 10b), the drain of which is connected to the power supply terminal 20 and the first source (current output terminal). ) 10a is a back gate and a current output terminal (external load connection terminal) 11 of the IC
It is connected to the. Reference numeral 12 is a load circuit connected to the current output terminal 11.

Reference numeral 13 is a power FET drive circuit for controlling the gate potential of the power FET by turning on / off the supply output of the charging current to the gate capacitance C of the power FET according to the power FET drive control signal.

Reference numeral 21 is connected to a second source (current detection terminal) 10b of the power FET and is connected to the current detection terminal 10b.
It is an overcurrent detection circuit that detects and outputs the amount of current of the detection current flowing in the case of overcurrent. This overcurrent detection circuit 21
Is the difference between the detection current flowing through the current detection terminal 10b of the power FET 10 and the reference current of the reference current source 141, and detects and outputs the amount of current when the detection current exceeds the reference current. It is configured by a current comparison circuit that operates.

Reference numeral 22 is a voltage conversion circuit using a resistance element which converts the detection current of the current detection circuit 21 into a voltage signal and outputs it. A voltage amplifier circuit 23 controls the gate potential of the power FET 10 by amplifying the voltage output of the resistance element 22 and drawing a current corresponding to the output voltage from the output current of the power FET drive circuit 13 to the ground potential. Is.

In the above structure, during normal operation, the load impedance is, for example, 12Ω, the applied voltage of the power supply terminal 20 is, for example, 12V, and the pulse signal input of the power FET drive circuit 13 is changed between 0V and, for example, 5V. The pulse signal output changes between 0V and 20V, for example. At this time, when 20 V is applied to the gate of the power FET 10, the current output terminal 10a of the power FET 10
1A flows into the power FET 10, and about 1/1000 of the current (about 1 mA) flows into the current detection terminal 10b of the power FET 10.

When the load impedance decreases due to a load short circuit, the output current of the power FET 10 increases, and the detection current exceeds the reference current (overcurrent), the overcurrent detection circuit 21 is connected. The voltage conversion circuit 22 and the voltage amplification circuit 23 protect the power FET 10 by performing feedback control so that the output current of the power FET drive circuit 13 is extracted and the power FET 10 is turned off.

However, the overcurrent limiting circuit having the above configuration includes the voltage amplifying circuit 23 in the power FET feedback control path and has a large gain, so that the control operation during feedback control becomes unstable and may oscillate. .

FIG. 4 shows that in the circuit of FIG. 3, the power supply voltage is applied to the power supply terminal 20 when the load is short-circuited, and the power FE
It shows how the waveform of the drain-source current IDS of the power FET 10 becomes unstable when the control operation of the T feedback control path becomes unstable and the overcurrent limiting circuit oscillates.

[0010]

As described above, in the conventional overcurrent limiting circuit, the gain of the voltage amplifying circuit included in the feedback control path of the protected semiconductor element is large. There is a problem that oscillation may occur during feedback control during overcurrent detection.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an overcurrent limiting circuit capable of preventing oscillation when detecting an overcurrent of a semiconductor element to be protected and performing feedback control. And

[0012]

SUMMARY OF THE INVENTION An overcurrent limiting circuit of the present invention is a voltage drive type power transistor having a multi-cell structure, and a control electrode capacitance of the power transistor is charged according to a drive control signal for the power transistor. A power transistor drive circuit for controlling the control electrode potential of the power transistor by controlling on / off of a current supply output, and a detection connected to the current detection terminal of the power transistor and flowing to the current detection terminal By overturning the output current of the overcurrent detection circuit that detects and outputs the current amount of the working current at the time of overcurrent, and by pulling out the output current of the power transistor drive circuit according to this turning back current And a control circuit for controlling the control electrode potential of the power transistor. And butterflies.

[0013]

[Function] When the load impedance of the power transistor decreases, the output current of the power transistor increases, and when the current for current detection exceeds the reference current (during overcurrent), the overcurrent detection circuit detects this. The control circuit extracts the output current of the power transistor drive circuit and performs feedback control so as to turn off the power transistor, thereby protecting the power transistor.

At this time, the power transistor feedback control path including the overcurrent detection circuit and the control circuit constitutes a current control path, does not include the voltage amplifier circuit, and has a low gain, so that the overcurrent of the power transistor is reduced. The operation at the time of detecting and performing feedback control does not become unstable, and the oscillation of the overcurrent limiting circuit can be prevented.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an overcurrent limiting circuit of an IC-formed power FET according to an embodiment of the present invention.

In FIG. 1, reference numeral 10 denotes a DMOS type power FET having a multi-source structure ((first source 10a, second source 10b), the drain of which is connected to a power supply terminal 20 and the first source ( Current output terminal) 1
0a is connected to the back gate and the current output terminal (external load connection terminal) 11 of the IC. Reference numeral 12 is a load circuit connected to the current output terminal 11.

The power FET 1 is controlled by turning on / off the supply output of the charging current to the gate capacitance C of the power FET 10 according to the power FET drive control signal.
It is a power FET drive circuit for controlling the gate potential of 0.

Reference numeral 14 denotes an overcurrent detection circuit connected to the second source (current detection terminal) 10b of the power FET, which indicates the amount of the detection current flowing through the current detection terminal 10b at the time of overcurrent. A current that is detected and output, and the difference between the detection current and the reference current of the reference current source 142 is calculated to detect and output the amount of current when the detection current exceeds the reference current. It is composed of a comparison circuit.

As an example of the overcurrent detection circuit 14,
A first NPN transistor Q1 having an emitter connected to the current output terminal 10a of the power FET 10, a first reference current source 141 connected between the collector of the first NPN transistor Q1 and a ground node, and First N
A second NPN transistor Q2 whose base / emitter is connected to the collector / base of the PN transistor Q1 and whose collector is connected to the ground node, and a power FE
The emitter is connected to the current detection terminal 10b of T10,
A third NPN transistor Q3 having a base connected to the base of the first NPN transistor Q1;
Second reference current source 142 connected between the collector of the NPN transistor Q3 and the ground node. Here, the reference current flowing through the second reference current source 142 and the reference current flowing through the first reference current source 141 are designed to be substantially the same.

Reference numeral 15 folds back the output current of the overcurrent detection circuit 14 and, according to the foldback current, the power FE.
The control circuit controls the potential of the control electrode of the power FET 10 by drawing the output current of the T drive circuit 13.

The control circuit 15 includes an overcurrent detection circuit 14
Output current of the MOS type current mirror circuit 16 (in this example, the power FET 10
A DMOSFET having the same structure as is used. )
And a resistance element 17 that generates a voltage corresponding to the output current of the current mirror circuit 16 and draws the output current of the power FET drive circuit 13 and supplies it to the ground potential.

The current mirror circuit 16 may be constructed by using a bipolar transistor, but it is desirable that the output side transistor has a high withstand voltage characteristic that can withstand the output voltage of the power FET drive circuit 13.

In the above structure, during normal operation, the load impedance is, for example, 12Ω, the voltage applied to the power supply terminal 20 is, for example, 12V, and the pulse signal input of the power FET drive circuit 13 changes between 0V and, for example, 5V. The pulse signal output changes between 0V and 20V, for example.

At this time, 20 is applied to the gate of the power FET 10.
When V is applied, 1 A flows to the current output terminal 10a of the power FET, and about 1/1000 of that (1 mA
Current flows to the current detection terminal 10b of the power FET. In this state, the current flowing from the current detection terminal 10b of the power FET into the overcurrent detection circuit 14 and the reference current flowing into the second reference current source 142 are balanced, and the output current from the overcurrent detection circuit 14 is in balance. However, the current mirror circuit 16 is in the off state.

On the other hand, the load impedance is lowered such as when the load is short-circuited, the output current and the detection current of the power FET 10 are increased, and flow into the overcurrent detection circuit 14 from the current detection terminal 10b of the power FET. When the current exceeds the reference current flowing through the second reference current source 142 (at the time of overcurrent), the overcurrent detection circuit 14 detects it and the output current from the overcurrent detection circuit 14 is returned by the current mirror circuit 16. . This return current flows through the resistance element 17, so that the output current of the power FET drive circuit 13 is extracted to the ground node, and feedback control is performed so that the power FET 10 is turned off. This makes the power FE
T10 is protected.

At this time, the power FET feedback control path consisting of the overcurrent detection circuit 14, the current mirror circuit 16, and the resistance element 17 constitutes a current control path, does not include a voltage amplifier circuit, and has a low gain. Therefore, power FET10
The operation when the feedback control is performed by detecting the overcurrent of is not unstable, and the oscillation of the overcurrent limiting circuit can be prevented. Further, since the power FET feedback control path performs current control, it has the advantages that the number of elements used is small, the configuration is simple, and the parameter of circuit characteristics can be easily set.

In the circuit of FIG. 1, when the power supply voltage is applied to the power supply terminal 20 in the load short-circuited state, the control operation of the power FET feedback control path is stably performed, and the drain / source of the power FET is shown in FIG. It shows that the waveform of the inter-current IDS is stable.

The overcurrent limiting circuit of the present invention is not limited to the DMOS power FET of the above-described embodiment, but is a voltage drive type power supply having a multi-cell structure including an IGBT (insulated gate bipolar transistor) having a multi-emitter structure. It is applicable to transistors.

[0029]

As described above, according to the overcurrent limiting circuit of the present invention, it is possible to prevent oscillation when detecting the overcurrent of the semiconductor element to be protected and performing feedback control.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an overcurrent limiting circuit of a power FET according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing that the waveform of a drain-source current IDS of a power FET is stable when a power supply voltage is applied to a power supply terminal when a load is short-circuited in the circuit of FIG.

FIG. 3 is a circuit diagram showing a conventional power FET overcurrent limiting circuit.

FIG. 4 is a waveform diagram showing that the waveform of the drain-source current IDS of the power FET is unstable when a power supply voltage is applied to the power supply terminal in the load short circuit state in the circuit of FIG.

[Explanation of symbols]

10 ... DMOS type power FE having multi-source structure
T, 10a ... First source (current output terminal) of power FET, 10b ... Second source (current detection terminal) of power FET, 11 ... Current output terminal of IC, 12 ... Load circuit, 13 ... Power FET Drive circuit, 14 ... Overcurrent detection circuit, 141, 142 ... Reference current source, 15 ... Control circuit, 1
6 ... Current mirror circuit, 17 ... Resistance element, 20 ... Power supply terminal, C ... Gate electrode capacitance of power FET.

Claims (3)

[Claims] 1. A voltage drive type power transistor having a multi-cell structure, and on / off control of a charge current supply output to a control electrode capacitance of the power transistor according to a drive control signal for the power transistor. A power transistor drive circuit for controlling the control electrode potential of the power transistor, and a current detection terminal connected to the current detection terminal of the power transistor, for detecting the current amount at the time of overcurrent of the detection current flowing in the current detection terminal. An overcurrent detection circuit for outputting, and a control circuit for folding back the output current of the overcurrent detection circuit and controlling the potential of the control electrode of the power transistor by drawing out the output current of the power transistor drive circuit according to the folding current. An overcurrent limiting circuit comprising: 2. The overcurrent limiting circuit according to claim 1, wherein the overcurrent detection circuit is connected to a current detection terminal of the power transistor, and includes a detection current and a reference current source that flow in the current detection terminal. An overcurrent limiting circuit, wherein a difference from a reference current is taken to detect and output a current amount when the detection current exceeds the reference current. 3. The overcurrent limiting circuit according to claim 1, wherein the voltage drive type power transistor having the multi-cell structure is a double diffusion type insulated gate power field effect transistor having a multi-source structure, The control circuit receives the output current of the overcurrent detection circuit,
An overcurrent limiting circuit comprising: a current mirror circuit that returns the input current; and a resistance element that causes the output current of the power transistor drive circuit to flow according to the output current of the current mirror circuit.