JP3470648B2 - Driver circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

The driver circuit of the present invention can be used for driving a main switch such as a switching power supply.

[0002]

2. Description of the Related Art Conventionally, a switching power supply consists of a control voltage pulse and a main switch driving voltage pulse.
Since the w levels are different, a driver circuit with a level shift function is required. Therefore, an example shown in FIG. 8 is known as an example of adding a level shift function to a driver circuit. The voltage buffer composed of the NPN transistor 8 and the PNP transistor 9 shown in the figure is well known, for example, "2.
It is disclosed on page 41. As the isolator 81 having a level shift function, a digital insulating coupler or the like is well known.

[0003]

In the driver circuit shown in FIG. 8, the isolator 81 is required to shift the low level V1 of the input voltage pulse to the low level V3 of the voltage buffer output pulse. Further, in the inverter 82, the high level V of the voltage buffer output pulse
There is a problem that the auxiliary power source V4 for setting 4 is required, and the number of parts increases.

An object of the present invention is to provide a simple driver circuit.

[0005]

The above object is to provide a logic circuit to which a first voltage pulse signal is input and a second voltage pulse signal is output, and a second voltage pulse signal which is connected to the logic circuit. Between a switching current source that outputs a current pulse signal based on the voltage buffer, a voltage buffer that is connected to the switching current source and that inputs the current pulse signal, and a potential lower than the low level of the voltage buffer input and the first voltage pulse signal Can be achieved by a driver circuit having an impedance connected to.

The voltage buffer is composed of a complementary emitter follower circuit having an NPN transistor and a PNP transistor, and a diode is connected between the base of the NPN transistor and the base of the PNP transistor. Preferred to achieve.

A further object of the present invention is to connect a logic circuit to which a first voltage pulse signal is input and a second voltage pulse signal is output, and a logic circuit which is connected to the logic circuit and which has a current pulse based on the second voltage pulse signal. A switching current source that outputs a signal, a voltage buffer that is connected to the switching current source and that inputs a current pulse signal, and is connected between the input of the voltage buffer and a potential lower than the low level of the first voltage pulse signal. This can be achieved by a driver circuit having an impedance, a MOS transistor whose gate is connected to the output of the voltage buffer, and an overcurrent protection circuit which detects an overcurrent of the MOS transistor and draws out the current of the switching current source.

Further, the above object is to provide a first PNP transistor having an emitter connected to a first power supply, a first resistor connected between the base and the emitter of the first transistor, and a first voltage pulse. Is input and a second resistor connected between a logic circuit that outputs a second voltage pulse and the collector of the first transistor, a base of the first PNP transistor collector, and an emitter of the first resistor. It can be achieved by a switching current source circuit having a second PNP transistor connected to the base of the PNP transistor and outputting a current pulse from the second PNP transistor based on the voltage pulse output from the logic circuit. .

Further, the above object is to provide a transformer and a detection circuit for detecting a secondary side output of the transformer and outputting a detection signal.
A control circuit for inputting the detection signal and outputting a first voltage pulse; and a logic circuit for inputting the first voltage pulse signal,
A switching current source connected to the logic circuit for outputting a current pulse signal, a voltage buffer connected to the switching current source for inputting a current pulse signal, an input of the voltage buffer and a potential lower than the low level of the first voltage pulse signal. And a driver circuit that has an impedance connected between the first voltage pulse signal and outputs the voltage pulse, and the voltage pulse output from the driver circuit is input to switch the primary side of the transformer. It can be achieved by a control device having a switching circuit.

According to the present invention, when the current source outputs the current IH in response to the first voltage pulse, the current IH flows through the impedance and the potential difference R · IH is generated across the impedance.
In addition, R is a resistance value of impedance. Therefore, NP
Base potential (V3 + R · IH) of N transistor is NP
When VBE exceeds the emitter potential of the N transistor, the NPN transistor turns on. On the other hand, P
The base potential of the NP transistor is VB more than the emitter potential
Since it goes high by E, the PNP transistor is turned off.
As a result, the driver output of the present invention becomes High level.
This High level voltage is (V3 + R · IH-VBE)
Becomes On the other hand, when the current source outputs the current IL,
The impedance current IL flows, and the base potential of the NPN transistor becomes (V3 + R · IL). N at this time
The difference between the base potential and the emitter potential of the PN transistor is {R. (IL-IH) + VBE}, which is lower than the VBE of the NPN transistor, so the NPN transistor is turned off. On the other hand, when the base potential of the PNP transistor becomes lower than the emitter potential by VBE, PN
The P transistor turns on. Therefore, the PNP transistor turns on and the NPN transistor turns off. As a result, the output pulse of the driver goes low. this
The low level voltage becomes (V3 + R.IL + VBE) because the PNP transistor is turned on. From the above, the low level V1 of the input voltage pulse is the low level of the output voltage pulse.
As a level, a potential V of (V3 + RIL + VBE)
It has been converted to a voltage level based on 3. Furthermore, the high level of the output voltage pulse is (V3 + R.IL-VB
E).

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 shows a first embodiment of a driver circuit according to the present invention.

In FIG. 1, 1 is an input terminal of a voltage pulse whose low level and high level are V1 and V2, 2 is an inverter, 3 is a first power source, 4 is a second power source, and 5 is a switching current source. , 7 is a first resistor, 8 is a first NPN transistor, 9 is a first PNP transistor, 10 is a third power supply, 11 is a driver output terminal of a voltage pulse whose Low level is the potential V3, and 25 is a first 5 power supply.

The input terminal, the output terminal, and the first terminal of the inverter 2
The power source terminal and the second power source terminal of the input terminal 1,
It is connected to the voltage pulse input terminal of the switching current source 5, the second power source 4 and the first power source 3. The positive and negative nodes of the switching current source 5 are connected to the second power supply 4 and the base of the first NPN transistor 8. First N
The collector, base and emitter of the PN transistor 8 are the fifth power supply 25 and the first PNP transistor 9 respectively.
Is connected to the base and driver output terminal 11. First
The collector and emitter of the PNP transistor 9 of
Is connected to the power source 10 and the driver output terminal 11. One and the other of the first resistor 7 are connected to the base of the first PNP transistor 9 and the third power supply 10.

A voltage higher than that of the first power source 3 is applied to the second power source 4, a voltage lower than that of the first power source 3 is applied to the third power source 10, and the potential 25 of the fifth power source is The one NPN transistor and the first PNP transistor provide the potential required for operation. Further, for example, a capacitive load is connected to the driver output terminal 11.

The operation of this circuit will be described. When a voltage pulse is input to the pulse input terminal 1, the inverter 2 outputs an inverted voltage pulse, which is input to the switching current source 5. The switching current source 5 outputs a current pulse in response to the input of the inversion voltage pulse. Inversion voltage pulse
At the low level, the switching current source 5 outputs the high level IH current. Further, when the inversion voltage pulse is at the high level, the switching current source 5 outputs the current at the low level IL. When the current pulse is at high level IH,
A current IH flows through the first resistor 7, and a potential difference R ·
IH occurs. When the base potential (V3 + R · IH) of the first NPN transistor 8 exceeds the emitter potential of the NPN transistor 8 by VBE, the NPN transistor 8 is turned on. On the other hand, since the base potential of the first PNP transistor 9 becomes higher than the emitter potential by VBE, it is turned off. As a result, the driver output 11 is Hi
gh level. This High level voltage is (V3 + R
・ IH-VBE). On the other hand, the switching current source 5
Outputs a current IL, the current IL flows through the first resistor 7, and the base potential of the first NPN transistor is (V3 +
R ・ IL). At this time, the difference between the base potential and the emitter potential of the first NPN transistor 8 is {R ·
(IL-IH) + VBE}, which is lower than VBE of the first NPN transistor 8, so that the first NPN transistor 8 is turned off. On the other hand, when the base potential of the first PNP transistor 9 becomes lower than the emitter potential by VBE, the first PNP transistor 9 turns on. Therefore, the first PNP transistor 9 turns on and the first PNP transistor 9 turns on.
NPN transistor 8 turns off. As a result, the output 11 of the driver becomes low level. This low level voltage becomes (V3 + R.IL + VBE).

FIG. 2 shows the input voltage pulse, output voltage pulse and current pulse waveform of the switching current source of this driver circuit.

12 is an input voltage pulse (pulse input terminal 1
Voltage), 13 is an output voltage pulse (driver output terminal 1
1 voltage), and 14 are current pulses of the switching current source 5. The high level of the output voltage pulse 13 is (V3
+ R · IH-VBE), and the Low level is (V3 + R
・ IL + VBE). As you can see from this figure, V1
The input voltage pulse whose reference potential is V is converted into an output voltage pulse whose reference potential is V3. Further, the high level of the output pulse can be arbitrarily set by the resistance value R of the first resistor 7 and the current value IH of the switching current source 5.

According to the present invention, the number of parts can be reduced, and since only the transistors, the diodes and the resistors can be used, the integrated circuit can be easily formed.

(Second Embodiment) FIG. 3 shows a second embodiment of the driver circuit according to the present invention.

In the figure, 1 is an input terminal of a voltage pulse whose low level and high level are V1 and V2, 2 is an inverter, 3 is a first power source, 4 is a second power source, 5 is a switching current source, 6 is a first diode, 7 is a first resistor, 8 is a first NPN transistor, and 9 is a first PN.
P-transistor, 10 is a third power supply, 11 is a driver output terminal of a voltage pulse whose Low level is the potential V3, 25
Is a fifth power source. The input terminal, the output terminal, the first power supply terminal and the second power supply terminal of the inverter 2 are an input terminal 1, a voltage pulse input terminal of the switching current source 5, respectively.
It is connected to the second power source 4 and the first power source 3. The positive and negative nodes of the switching current source 5 are connected to the second power supply 4 and the base of the first NPN transistor 8.
The collector, base and emitter of the first NPN transistor 8 are the fifth power supply 25 and the first diode 6 respectively.
Is connected to the anode and the driver output terminal 11. The collector, base and emitter of the first PNP transistor 9 are connected to the third power supply 10, the cathode of the first diode 6 and the driver output terminal 11, respectively. First
One and the other of the resistor 7 are connected to the cathode of the first diode 6 and the third power supply 10.

A voltage higher than that of the first power source 3 is applied to the second power source 4, a voltage lower than that of the first power source 3 is applied to the third power source 10, and the potential of the fifth power source 25 is The one NPN transistor and the first PNP transistor provide the potential required for operation. Further, for example, a capacitive load is connected to the driver output terminal 11.

The operation of this circuit is almost the same as that of the first embodiment. The difference from the first embodiment is that the high level of the driver output pulse is (V3 + R.multidot.R) due to the first diode 6.
IH + Vd−VBE). The forward voltage of the first diode is Vd. When the current pulse is at the high level IH, the current IH flows through the first diode 6 and the first resistor 7, and the base potential of the first NPN transistor becomes (V3 + R · IH + Vd). When this base potential exceeds the emitter potential of the first NPN transistor by VBE, the first NPN transistor 8 turns on.
Therefore, the emitter potential of the first NPN transistor becomes (V3 + R · IH + Vd−VBE). On the other hand, the base potential of the first PNP transistor 9 is (V3
+ R · IH) and the emitter potential (V3 + R · IH +
Since VBE−Vd≈0 for Vd−VBE),
The first PNP transistor is turned off. Therefore, the potential of the pulse output terminal 11 is (V3 + R · IH + Vd−VB
E).

On the other hand, when the current pulse is at the low level IL, the current IL flows through the first diode 6 and the first resistor 7, and the base potential of the first NPN transistor is (V3
+ R · IL + Vd). At this time, the difference between the base potential and the emitter potential of the first NPN transistor is {R · (IL-IH) + VBE}, and the first NPN transistor is
Since it is below VBE of the transistor, the first NPN transistor 8 is turned off. On the other hand, the difference between the base potential and the emitter potential of the first PNP transistor 9 is {R. (IL-IH) + VBE-Vd}, the first PNP transistor 9 is turned on, and the first NPN transistor 8 is turned on. Turns off. As a result, the output pulse of the driver is
Low level. This low level voltage is the first P
Since the NP transistor 9 is turned on, (V3 + R.IL
+ VBE). In the case of this embodiment, since Vd and VBE are approximately equal to about 0.7 V, the high level of the output voltage pulse is (V3 + R · IH). As a result, the high level of the output voltage pulse is not affected by VBE of the first NPN transistor. Further, when the first PNP transistor 9 is off, the voltage between the base and the emitter thereof is suppressed to almost 0, so that there is an advantage that switching from off to on becomes fast.

(Embodiment 3) FIG. 4 shows a driver circuit according to a third embodiment of the present invention.

The basic structure of this embodiment is almost the same as that of the second embodiment, and the difference from the second embodiment is that the switching current source 5 is embodied by a PNP transistor and a resistor. A load such as an nMOS is connected to the pulse output terminal 11.

In the figure, 16 is a second resistor, 17 is a second PNP transistor, 18 is a third resistor, 19 is a third PNP transistor, 50 is a damping resistor, 5
Reference numeral 1 is an nMOS, 52 is an inductance, and 53 is a first connection terminal. Incidentally, 50 and 51 are loads of the driver circuit of the present invention. The potential of the fifth power supply 25 may be any potential required for operating the first NPN transistor and the first PNP transistor.

Input terminal, output terminal, first of inverter 2
The power source terminal and the second power source terminal of the input terminal 1,
One of the third resistor 18, the second power source 4 and the first power source 3
Connected to. The collector, base and emitter of the second PNP transistor 17 are connected to the other of the third resistors 18, one of the second resistors 16 and the second power supply 4, respectively. The other of the second resistors 16 is connected to the second power supply 4. The collector, base and emitter of the third PNP transistor 19 are connected to the base of the first NPN transistor 8, the collector of the second PNP transistor 17 and the base of the second PNP transistor 17, respectively.
The collector, base and emitter of the first NPN transistor 8 are the fifth power supply 25 and the first diode 6 respectively.
Is connected to the anode and the driver output terminal 11. The collector, base and emitter of the first PNP transistor 9 are connected to the third power supply 10, the cathode of the first diode 6 and the driver output terminal 11, respectively. First
One and the other of the resistor 7 are connected to the cathode of the first diode 6 and the third power supply 10. Damping resistor 5
One and the other of 0 are driver output terminal 11 and nMOS
It is connected to the gate of 51. The source and drain of the nMOS 51 are connected to one of the third power supply 10 and the inductance 52. The other end of the inductance 52 is connected to the first connection terminal 53.

The operation of this circuit is almost the same as that of the second embodiment, and the difference from the second embodiment is only the part of the switching current source. The circuit operation of the switching current source of this embodiment will be described below.

When the output of the inverter 2 is at the low level V1, the base potential of the third PNP transistor 19 is substantially equal to V1 and the third PNP transistor 19 is turned on. When the third PNP transistor 19 turns on, the second
An electric current starts to flow in the resistor 16 and the potential difference is generated across the resistor 16. This potential difference is VB of the second PNP transistor 17.
When E is exceeded, the second PNP transistor turns on,
A substantially constant current flows through the third PNP transistor 19. Assuming that the constant current of the third PNP transistor 19 at this time is IH, there is a relation of IH = VBE1 ÷ R1. Note that VBE1 is the V of the second PNP transistor 17.
In BE, R1 is the resistance value of the second resistor 16.

The output of the inverter 2 is at the high level V
When it is 2, the base potential of the third PNP transistor 19 is substantially equal to V2, and the third PNP transistor 19 is turned off. If the collector current of the third PNP transistor 19 at this time is IL, IL = 0. Therefore, according to the output pulse of the inverter 2, the switching current source sets the high level to VBE1 ÷ R1 and the low level to 0.
Output the current pulse. The subsequent operation of the driver circuit is the same as that of the second embodiment.

According to this means, the same effect as the second embodiment can be obtained.

(Fourth Embodiment) FIG. 5 shows a fourth embodiment of the driver circuit according to the present invention.

The basic structure of this embodiment is almost the same as that of the third embodiment, and the difference from the third embodiment is that it is between the base of the second PNP transistor 17 and the emitter of the third PNP transistor. This is the point where the anode and cathode of the second diode 20 are connected.

Input terminal, output terminal, first of inverter 2
The power source terminal and the second power source terminal of the input terminal 1,
One of the third resistor 18, the second power source 4 and the first power source 3
It is connected to the. The collector, base and emitter of the second PNP transistor 17 are respectively the third resistor 18
On the other hand, it is connected to one of the second resistors 16 and the second power source 4. The other of the second resistors 16 is connected to the second power supply 4. The anode and cathode of the second diode 20 are connected to the base of the second PNP transistor 17 and the emitter of the third PNP transistor 19. The collector and the base of the third PNP transistor 19 are the base and the second PN of the first NPN transistor 8.
It is connected to the collector of the P-transistor 17. First
The collector, base and emitter of the NPN transistor 8 are connected to the fifth power supply 25, the anode of the first diode 6 and the driver output terminal 11, respectively. The collector, base and emitter of the first PNP transistor 9 are connected to the third power supply 10, the cathode of the first diode 6 and the driver output terminal 11, respectively.
One and the other of the first resistor 7 are connected to the cathode of the first diode 6 and the third power supply 10. One and the other of the dipping resistor 50 are connected to the driver output terminal 11 and the gate of the nMOS 51. nMOS51
The source and drain of are connected to one of the third power supply 10 and the inductance 52. Inductance 52
The other of is connected to the first connection terminal 53.

The operation of this circuit is almost the same as that of the third embodiment, and the difference from the third embodiment is the logical threshold value of the switching current source. In the case of the present embodiment, the voltage decreases by the forward voltage of the second diode compared to the logic threshold value of the third embodiment.
This increases the noise margin for the second power supply V2.

According to this structure, the same effect as that of the third embodiment is obtained, and the noise margin for the second power supply 4 is increased.

(Embodiment 5) FIG. 6 shows a driver circuit according to a fifth embodiment of the present invention.

The basic structure of this embodiment is almost the same as that of the fourth embodiment, and the difference from the fourth embodiment is the load nM.
The point is that the overcurrent protection function of the OS is added.

In the figure, 21 is a second NPN transistor, 22 is a fourth resistor, 23 is a second connection terminal, and 2 is a second connection terminal.
Reference numeral 4 is a sense resistor.

Input terminal, output terminal, first of inverter 2
The power source terminal and the second power source terminal of the input terminal 1,
One of the third resistor 18, the second power source 4 and the first power source 3
It is connected to the. The collector, base and emitter of the second PNP transistor 17 are respectively the third resistor 18
On the other hand, it is connected to one of the second resistors 16 and the second power source 4. The other of the second resistors 16 is connected to the second power supply 4. The anode and cathode of the second diode 20 are connected to the base of the second PNP transistor 17 and the emitter of the third PNP transistor 19. The collector and the base of the third PNP transistor 19 are the base and the second PN of the first NPN transistor 8.
It is connected to the collector of the P-transistor 17. First
The collector, base and emitter of the NPN transistor 8 are connected to the fifth power supply 25, the anode of the first diode 6 and the driver output terminal 11, respectively. The collector, base and emitter of the first PNP transistor 9 are connected to the third power supply 10, the cathode of the first diode 6 and the driver output terminal 11, respectively.
One and the other of the first resistor 7 are connected to the cathode of the first diode 6 and the third power supply 10. One side and the other side of the damping resistor 50 are connected to the driver output terminal 11 and the gate of the nMOS 51. nMOS51
The source and drain of are connected to one of the sense resistor 24 and one of the inductance 52. The other end of the inductance 52 is connected to the first connection terminal 53.
The collector, base and emitter of the second NPN transistor 21 are connected to the base of the first PNP transistor 9, one of the fourth resistors 22 and the third power supply 10, respectively. The other side of the sense resistor 24 is connected to the third power supply 10.

The operation principle of this embodiment is almost the same as that of the fourth embodiment, but the difference from the fourth embodiment is that nM.
This is an operation when an overcurrent flows through the OS 51. nMOS
When an overcurrent flows through 51, a potential difference is generated across the sense resistor 24, the second NPN transistor 21 is turned on, and the current flowing through the first resistor 7 is extracted. Therefore, even if the switching current source 5 outputs the current pulse IH, no potential difference is generated across the first resistor 7, the first NPN transistor is turned off, and the first PNP transistor is turned on.
As a result, the output voltage pulse of the driver circuit always maintains the low level, and the nMOS 51 is turned off. This allows
It is possible to prevent breakdown of the nMOS 51 due to overcurrent.

According to this structure, the same effect as that of the fourth embodiment can be obtained, and the breakdown of the nMOS 51 due to the overcurrent can be prevented.

Incidentally, 21 is not limited to the NPN transistor as in this embodiment.

(Embodiment 6) FIG. 7 shows an application example of the driver circuit of this embodiment, which is an example in which the present invention is applied to a DC-DC converter.

In the figure, 54 is a driver circuit of the present invention, 55 is a circuit for controlling a DC-DC converter, and 56 is a circuit.
Is a detection circuit for detecting the secondary side output of the DC-DC converter, 57 is the primary side filter of the DC-DC converter, 5
8 is a first DC power supply, and 59 is a DC-DC converter.
Secondary-side rectification and filter circuit, 60 is a load of the DC-DC converter, and 61 is a second DC power supply. The second DC power supply 61 is a power supply for operating the detection circuit 56, the control circuit 55, and the driver circuit 54.

The input terminal 1, driver output terminal 11, second power supply 4, first power supply 3, second connection terminal 23 and fifth power supply 25 of the driver circuit 54 are respectively control circuits 55.
Output terminal, one of the damping resistors 50, the positive electrode of the second DC power supply 61, the negative electrode of the second DC power supply 61, the nMOS 5
1 and the first connection terminal 53.
The input terminal, the first power supply terminal and the second power supply terminal of the control circuit 55 are the output terminal of the detection circuit 56 and the second DC terminal, respectively.
It is connected to the positive electrode of the power supply 61 and the negative electrode of the second DC power supply 61. The first input terminal, the second input terminal, the first power supply terminal and the second power supply terminal of the detection circuit 56 are each 2
It is connected to the first output of the secondary side rectification and filter circuit 59, the second output of the secondary side rectification and filter circuit 59, the positive electrode of the second DC power supply 61 and the negative electrode of the second DC power supply 61. The positive electrode and the negative electrode of the first DC power source 58 are each 1
It is connected to the first input terminal and the second input terminal of the secondary filter circuit 57. First of the primary side filter circuit 57
The output terminal and the second output terminal of are connected to the other of the first connection terminal 53 and the sense resistor 24, respectively. One and the other of the load 60 are the secondary side rectification and filter circuit 5
9 and a second output of the secondary rectification and filter circuit 59.

The operation of this embodiment will be described. Detection circuit 56
Detects the output on the secondary side and outputs the detected output to the control circuit 5.
Give feedback to 5. The control circuit 55 transmits a signal as a voltage pulse to the pulse input terminal 1 of the driver circuit 54 so as to make the output on the secondary side constant. Assuming that this voltage pulse is a voltage pulse such as 12 in FIG. 2, the pulse output terminal 11 of the driver circuit 54 is V1 as indicated by 13 in FIG.
The potential of the nMOS 51 is level-shifted to the voltage pulse of which the reference voltage is V3. This causes the nMOS 51 to switch and output a voltage to the secondary side of the DC-DC converter.

According to the driver circuit of the present invention, the DC-DC converter can be miniaturized because it can be constructed with a small number of parts.

[0049]

As described above, according to the present invention, a driver having a simple structure can be realized, which contributes to downsizing and cost reduction of a DC-DC converter.

[Brief description of drawings]

FIG. 1 is a first embodiment of a driver circuit of the present invention.

FIG. 2 is a diagram for explaining the operation of the first embodiment.

FIG. 3 is a second embodiment of the driver circuit of the present invention.

FIG. 4 is a third embodiment of the driver circuit of the present invention.

FIG. 5 is a fourth embodiment of the driver circuit of the present invention.

FIG. 6 is a fifth embodiment of the driver circuit of the present invention.

FIG. 7 is an application example of the driver circuit of the present invention.

FIG. 8 is a conventional example of a driver with a level shift function.

[Explanation of symbols]

1 ... input terminal, 2 ... inverter, 3 ... first power source, 4 ...
Second power source, 5 ... Switching current source, 6 ... First diode, 7 ... First resistor, 8 ... First NPN transistor, 9 ... First PNP transistor, 10 ... Third power source, 11 ... Output terminal, 12 ... Input voltage pulse, 13 ... Output voltage pulse, 14 ... Switching current source 5 current pulse, 16 ... Second resistance, 17 ... Second PNP transistor, 18 ... Third resistance, 19 ... 3 ... PNP transistor, 20 ... 2nd diode, 21 ... 2nd NPN transistor, 22 ... 4th resistance, 23 ... 2nd connection terminal,
24 ... Sense resistor, 25 ... Fifth power supply, 50 ... Damping resistor, 51 ... nMOS, 52 ... Inductance, 53
... first connection terminal, 54 ... driver circuit of the present invention, 55
... control circuit, 56 ... detection circuit, 57 ... primary side filter circuit, 58 ... first DC power supply, 59 ... secondary side rectification and filter circuit, 60 ... DC-DC converter load, 61 ...
2nd DC power supply, 81 ... Isolator, 82 ... 2nd inverter, 83 ... 3rd connection terminal, 84 ... Auxiliary power supply.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H02M 3/28

Claims (6)

(57) [Claims] 1. A logic circuit to which a first voltage pulse signal is input and a second voltage pulse signal is output, and a current pulse signal which is connected to the logic circuit and which is based on the second voltage pulse signal. A switching current source for outputting, a voltage buffer connected to the switching current source for inputting the current pulse signal, an input of the voltage buffer and the first voltage pulse signal
A driver circuit having an impedance connected to a potential lower than a low level. 2. The voltage buffer according to claim 1, wherein the voltage buffer is a complementary emitter follower circuit having an NPN transistor and a PNP transistor, and a diode is connected between the base of the NPN transistor and the base of the PNP transistor. Driver circuit. 3. A logic circuit to which a first voltage pulse signal is input and a second voltage pulse signal is output, and a current pulse signal which is connected to the logic circuit and is based on the second voltage pulse signal. A switching current source for outputting, a voltage buffer connected to the switching current source for inputting the current pulse signal, an input of the voltage buffer and the first voltage pulse signal
An impedance connected between a potential lower than a low level, a MOS transistor whose gate is connected to the output of the voltage buffer, an overcurrent for detecting the overcurrent of the MOS transistor, and extracting the current of the switching current source. A driver circuit having a protection circuit. 4. A first PNP transistor having an emitter connected to a first power supply, a first resistor connected between a base and an emitter of the first transistor, and a first voltage pulse input. A second resistor connected between the logic circuit for outputting a second voltage pulse and the collector of the first transistor, and the base of which is the collector of the first PNP transistor,
A switching current whose emitter has a second PNP transistor connected to the base of the first PNP transistor, and which outputs a current pulse from the second PNP transistor based on the voltage pulse output from the logic circuit. Source circuit. 5. The base of the first PNP transistor and the second P of claim 3.
A current source circuit in which a diode is connected between the emitter of the NP transistor. 6. A transformer, a detection circuit which detects a secondary side output of the transformer and outputs a detection signal, a control circuit which receives the detection signal and outputs a first voltage pulse, and the first circuit. A logic circuit to which the voltage pulse signal is input, a switching current source connected to the logic circuit to output a current pulse signal, a voltage buffer connected to the switching current source to input the current pulse signal, and the voltage buffer A driver circuit that has an impedance connected between the input of the first voltage pulse signal and a potential lower than the low level of the first voltage pulse signal, and that inputs the first voltage pulse signal and outputs a voltage pulse, And a switching circuit for inputting a voltage pulse output from a driver circuit and switching the primary side of the transformer.