JPH0223062A - Switching power supply controlling circuit - Google Patents

Switching power supply controlling circuit

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Publication number
JPH0223062A
JPH0223062A JP17061588A JP17061588A JPH0223062A JP H0223062 A JPH0223062 A JP H0223062A JP 17061588 A JP17061588 A JP 17061588A JP 17061588 A JP17061588 A JP 17061588A JP H0223062 A JPH0223062 A JP H0223062A
Authority
JP
Japan
Prior art keywords
circuit
switching
power supply
control circuit
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17061588A
Other languages
Japanese (ja)
Inventor
Tatsuji Yamawaki
山脇 達司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17061588A priority Critical patent/JPH0223062A/en
Publication of JPH0223062A publication Critical patent/JPH0223062A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce electromagnetic noise by providing an impedance controlling circuit between the output terminal of a switching controlling circuit and the gate electrode of a power MOSFET. CONSTITUTION:A switching power supply controlling circuit has a voltage variation detection circuit 1 which outputs a pulse width control signal Vpc of a level responsive to the variation in the output power voltage Vcc of a rectifying and smoothing circuit 7, a pulse width modulator 2, a switching control circuit 3 which outputs a switching control signal Vsc, and switching circuit 6. In this case, an impedance control circuit 5 having a junction type FETQJ in which its ON resistance is controlled in response to the level of an overcurrent detection control signal VDC is provided between the output terminal of the control circuit 3 and the gate electrode of the power MOSFETQP of the circuit 6, and an overcurrent detection controlling circuit 4 is provided. Thus, if an overcurrent flows to the FETQP, the circuit 4 immediately increases the ON resistance of the FETQJ.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はスイッチング電源制御回路に関し、特にパワー
M OS F E Tによりスイッチング電源トランス
の一次側をオン・オフ制御し所定の電源電圧を得るスイ
ッチング電源制御回路に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a switching power supply control circuit, and particularly to a switching power supply control circuit that controls on/off the primary side of a switching power supply transformer using a power MOSFET to obtain a predetermined power supply voltage. Related to power supply control circuits.

〔従来の技術〕[Conventional technology]

従来、この種のスイッチング電源制御回路は、第3図に
示すように、演算増幅器A1と定電圧ダ、イオードD1
とを備え、整流平滑回路7の出力電源電圧VCCの変動
に応じたレベルのパルス幅制御信号VPcを出力する電
圧変動検出回路1と、コンパレータA2を備え三角波と
パルス幅制御信号VPCとを入力しこのパルス幅制御信
号VPCのレベルに対応したパルス幅のパルス列信号V
p7を出力するパルス幅変調回路2と、1次電源の基準
電位端子(接地端子)と電源電圧V cI端子との間に
直列接続された2つのトランジスタQ!、Q2を備えパ
ルス列信号Vp7により出力端と基準電位端子及び電源
電圧■。、端子との間を交互にオン・オフしスイッチン
グ制御信号Vscを出力するスイッチング制御回路3と
、スイッチング制御信号■scをゲート電極に入力して
オン・オフするパワーM OS F E T Q pと
2次側に整流平滑回路7を接続したスイッチング電源ト
ランスTlとを1次電源の基準電位端子及び電源電圧V
CI端子間に直列接続したスイッチング回路6とを有す
る構成となっていた。
Conventionally, this type of switching power supply control circuit, as shown in FIG.
A voltage fluctuation detection circuit 1 outputs a pulse width control signal VPc at a level corresponding to fluctuations in the output power supply voltage VCC of the rectifying and smoothing circuit 7, and a comparator A2 inputting the triangular wave and the pulse width control signal VPC. Pulse train signal V with a pulse width corresponding to the level of this pulse width control signal VPC
A pulse width modulation circuit 2 that outputs p7, and two transistors Q! connected in series between the reference potential terminal (ground terminal) of the primary power supply and the power supply voltage VcI terminal. , Q2, and an output terminal, a reference potential terminal, and a power supply voltage (■) according to the pulse train signal Vp7. , a switching control circuit 3 which outputs a switching control signal Vsc by alternately turning on and off between the terminals, and a power MOSFET Q p which inputs a switching control signal SC to a gate electrode and turns it on and off. A switching power supply transformer Tl with a rectifying and smoothing circuit 7 connected to the secondary side is connected to the reference potential terminal of the primary power supply and the power supply voltage V.
The configuration includes a switching circuit 6 connected in series between the CI terminals.

〔発明が解決しようとする課題〕 上述した従来のスイッチング電源制御回路は、整流平滑
回路7の出力電源電圧■ccの変動を電圧変動検出回路
1、パルス幅変調回路2及びスイッチング制御回路3を
介してスイッチング回路6へ伝達制御する組成となって
いるので、これらの複数の回路を介しているほか、出力
電源電圧VCC端と接地電位端子間には静電容量が存在
し、また回路配線等の影響で制御の応答速度が低下し、
瞬時の重負荷に対してパワーM OS F E T Q
 、−が破壊するという欠点がある。
[Problems to be Solved by the Invention] The conventional switching power supply control circuit described above detects fluctuations in the output power supply voltage ■cc of the rectifying and smoothing circuit 7 through the voltage fluctuation detection circuit 1, the pulse width modulation circuit 2, and the switching control circuit 3. Since the composition is such that the transmission is controlled via these multiple circuits, there is capacitance between the output power supply voltage VCC terminal and the ground potential terminal, and there is also capacitance between the output power supply voltage VCC terminal and the ground potential terminal, and As a result, the control response speed decreases,
Power MOSFET Q for instantaneous heavy loads
, - has the disadvantage of being destroyed.

本発明の目的は、制御の応答速度を早めパワーM OS
 I” E Tの破壊を防止することができるスイッチ
ング電源制御回路を提供することにある。
The purpose of the present invention is to speed up the control response speed and improve power MOSFETs.
An object of the present invention is to provide a switching power supply control circuit that can prevent destruction of an I''ET.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のスイッチング電源制御回路は、整流平滑回路の
出力電源電圧の変動に応じたレベルのパルス幅制御電圧
を出力する電圧変動検出回路と、前記パルス幅制御電圧
のレベルに対応したパルス幅のパルス列信号を出力する
パルス幅変調回路と、1次電源の第1及び第2の電源端
子間に直列接続された2つのトランジスタを備え前記パ
ルス列信号により出力端と前記第1及び第2の電源端子
との間を交互にオン・オフしたスイッチング制御信号を
出力するスイッチング制御回路と、前記スイッチング制
御信号をゲート電極に入力してオン・オフするパワーM
 OS F E Tと2次側に前記整流平滑回路を接続
しスイッチング電源トランスとを前記1次電源の第1及
び第2の電源端子間に直列接続したスイッチング回路と
を有するスイッチング電源制御回路において、前記スイ
ッチング制御回路の出力端と+iir記パワーMOSF
ETのゲート電極との間に過電流検出制御信号のレベル
に応じてオン抵抗が制御されるトランジスタを(iMえ
たインピーダンス制御回路を設け、前記スイッチング回
路と前記1次電源の第1の電源端子との間にこのスイッ
チング回路と直列に接続された過電流検出用の抵抗を備
えこの抵抗の端子間電圧に応じて所定のレベルの前記過
電流検出制御信号を出力する過電流検出制御回路を設け
て構成される。
A switching power supply control circuit of the present invention includes a voltage fluctuation detection circuit that outputs a pulse width control voltage at a level corresponding to fluctuations in the output power supply voltage of a rectifying and smoothing circuit, and a pulse train having a pulse width corresponding to the level of the pulse width control voltage. a pulse width modulation circuit that outputs a signal; and two transistors connected in series between the first and second power terminals of a primary power source; a switching control circuit that outputs a switching control signal that alternately turns on and off; and a power M that inputs the switching control signal to a gate electrode and turns it on and off.
A switching power supply control circuit comprising an OS FET and a switching circuit in which the rectifying and smoothing circuit is connected to the secondary side and a switching power supply transformer is connected in series between the first and second power terminals of the primary power supply, The output terminal of the switching control circuit and +iir power MOSF
An impedance control circuit including a transistor whose on-resistance is controlled according to the level of the overcurrent detection control signal is provided between the gate electrode of the ET and the switching circuit and the first power supply terminal of the primary power supply. an overcurrent detection control circuit that includes an overcurrent detection resistor connected in series with the switching circuit between the switching circuit and the overcurrent detection control circuit that outputs the overcurrent detection control signal at a predetermined level according to the voltage between the terminals of the resistor; configured.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

この実施例が第3図に示された従来のスイッチング電源
制御回路と相違する点は、スイッチング制御回1i’!
 3の出力端とスイッチング回路6のパワーM OS 
F E’l’ Q pのグー1〜電極との間に、過電流
検出制御信号V。Cのレベルに応じてオン抵抗が制御さ
れる接合型F ET Q 、を備えたインピーダンス制
御回路5を設け、スイッチング回路6と1次電源の基準
電位端子(接地端子)との間に、このスイッチング回路
6と直列に接続された過電流検出用の抵抗R7と、定電
圧ダイオードD2と演算増幅器Δ1とを備え、この抵抗
R7の端子間電圧に応じて所定のレベルの過電流検出制
御信号VOcを出力する過電流検出制御回路4を設けた
点にある。
This embodiment differs from the conventional switching power supply control circuit shown in FIG. 3 in that the switching control circuit 1i'!
The output terminal of 3 and the power MOS of the switching circuit 6
An overcurrent detection control signal V is provided between the goo 1 and the electrodes of F E'l' Q p. An impedance control circuit 5 including a junction FET Q whose on-resistance is controlled according to the level of C is provided, and this switching It includes an overcurrent detection resistor R7 connected in series with the circuit 6, a constant voltage diode D2, and an operational amplifier Δ1, and outputs an overcurrent detection control signal VOc at a predetermined level according to the voltage between the terminals of this resistor R7. The point is that an overcurrent detection control circuit 4 for outputting is provided.

過電流検出制御信号VDCは、スイッチング回路6に過
電流が流れるとインピーダンス制御回路5の接合型F 
E T Q 、+のオン抵抗を増大させ、スイッチング
制御回路3の出力端とパワーMO3FE ’T Q p
のゲートとの間のインピーダンスを高くするようにレベ
ル変化する。即ち、抵抗R7の端子間電圧が定電圧ダイ
オードD2で定まる所定のレベルを越えると演算増幅器
A3の出力端から出力される過電流検出制御信号VDC
のレベルは低下し、接合型F E T Q Jのオン抵
抗は増大する。
The overcurrent detection control signal VDC detects the junction type F of the impedance control circuit 5 when an overcurrent flows through the switching circuit 6.
By increasing the on-resistance of E T Q ,
The level changes to increase the impedance between the gate and the gate. That is, when the voltage across the terminals of resistor R7 exceeds a predetermined level determined by voltage regulator diode D2, overcurrent detection control signal VDC is output from the output terminal of operational amplifier A3.
level decreases, and the on-resistance of the junction type FETQJ increases.

ところで、パワーM OS F E T Q pの入力
容量は一般的に数千pF程度あるため、パワーMOSF
ETQPの高速スイッチングを行なう為には、ゲート電
極と基準電位端子及び電源電圧V C1端子との間のイ
ンピーダンスを下げることが重要な要素となる。
By the way, the input capacitance of the power MOSFET Qp is generally about several thousand pF, so the power MOSFET
In order to perform high-speed switching of ETQP, it is important to lower the impedance between the gate electrode and the reference potential terminal and power supply voltage V C1 terminal.

ところが、過度にインピーダンスを下げると、パワーM
 OS F E T Q pがターンオフした際過電力
破壊に至ることがある。なぜならば、急速にターンオフ
すると、トレイン・ソース間電圧が急上昇する一方、ス
イッチング電源トランスTlが誘導性負荷である為に電
流の下降が急激に始まらずこのパワーM OS F E
 T Q pに短時間に過大な電力が印加される為であ
り、上記過電力破壊保護に対する制御回路の設計がスイ
ッチング電源における重要な要素となっている。
However, if the impedance is lowered excessively, the power M
When the OS FET Qp is turned off, overpower damage may occur. This is because when it is turned off rapidly, the voltage between the train and the source rises rapidly, but since the switching power transformer Tl is an inductive load, the current does not start to fall suddenly, and this power MOS F E
This is because excessive power is applied to T Q p in a short period of time, and the design of the control circuit for the above-mentioned overpower breakdown protection is an important element in switching power supplies.

以上の事実より、パワーM OS F E T Q p
の有効な制御回路は、次の様に考えることが出来る。
From the above facts, the power M OS F E T Q p
An effective control circuit for can be considered as follows.

即ち、ターンオフ、ターンオン時には極力、インピーダ
ンス制御回路5を含むゲートドライブ回路のインピーダ
ンスを下げ、しかしターンオフ時にパワーM OS F
 E T Q pがターンオフ破壊に至らぬ程度にして
効率、破壊耐量とも最適値で動作させる事が理想的であ
る。
That is, at turn-off and turn-on, the impedance of the gate drive circuit including the impedance control circuit 5 is lowered as much as possible, but at turn-off, the power MOSF
Ideally, E T Q p should be set to a level that does not lead to turn-off destruction, and the efficiency and destruction resistance should both be operated at optimum values.

因みに本発明では、ゲートドライブ回路のインピーダン
スの制御を接合型F E T Q Jの順・逆側方向の
インピーダンス特性(オン抵抗)を利用して実行し、こ
の接合型F E T Q 、、+の制御をパワーM O
S F E T Q pのソース電流に基づいて動作す
る過電流検出制御回路4により行っている。
Incidentally, in the present invention, the impedance of the gate drive circuit is controlled by using the impedance characteristics (on resistance) in the forward and reverse directions of the junction type FETQ, and the impedance of the junction type FETQ, , + Control of power MO
This is performed by an overcurrent detection control circuit 4 that operates based on the source current of S F E T Q p.

従って、パワーM OS F E T Q pに過電流
が流れると過電流検出制御回路4によりただちに接合型
F E T Q 、+のオン抵抗を増大させるので、制
御経路が短縮され保護応答時間を短縮することができる
Therefore, when an overcurrent flows through the power MOSFET Qp, the overcurrent detection control circuit 4 immediately increases the on-resistance of the junction type FETQ, +, thereby shortening the control path and shortening the protection response time. can do.

第2図は本発明の第2の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

ターンオン、ターンオフ時のインピーダンスは低くする
ことが望ましく、一般にはターンオフ時の方を低くする
場合が多い。
It is desirable that the impedance be low during turn-on and turn-off, and generally it is often lower during turn-off.

二の実施例においては、インピーダンス制御回路SAを
接合型F E T Q Jと直列にダイオードD、と抵
抗R8との並列回路を接続した構成とし、ターンオフ時
には接合型F E T Q 、、+のオン抵抗、ターン
オン時には接合型F E T Q Jのオン抵抗と抵抗
R8との和の抵抗でゲートドライブ回路のインピーダン
スを制御している。
In the second embodiment, the impedance control circuit SA has a configuration in which a parallel circuit of a diode D and a resistor R8 is connected in series with the junction type FETQJ, and at turn-off, the junction type FETQ, . The impedance of the gate drive circuit is controlled by the on-resistance, which is the sum of the on-resistance of the junction type FETQJ and the resistor R8 during turn-on.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、スイッチング制御回路の
出力端とパワーMOS F ETのグー1−’+S極と
の間にオン抵抗制御されるトランジスタを備えたインピ
ーダンス制御回路を設け、パワーMOSFETのソース
電流を検出する抵抗を設けてこの抵抗の端子間電圧によ
りトランジスタのオン抵抗を制御する構成とすることに
より、パワーMOSFETのゲートドライブ回路のイン
ピーダンスの制御経路が短縮されるので保護応答時間を
短縮することができ、パワーM OS I” E Tの
破壊を防止することかできる効果がある。
As explained above, the present invention provides an impedance control circuit equipped with a transistor whose on-resistance is controlled between the output terminal of the switching control circuit and the G1-'+S pole of the power MOSFET, and By providing a resistor for detecting current and controlling the on-resistance of the transistor by the voltage between the terminals of this resistor, the impedance control path of the power MOSFET gate drive circuit is shortened, thereby shortening the protection response time. This has the effect of preventing damage to the power MOS I''ET.

また、大電流動作時には、ドレイン電流、電圧波形等の
急激な変化が緩和され鈍るので、電磁波雑音を低減する
ことかできる効果もある。
Furthermore, during large current operation, rapid changes in drain current, voltage waveforms, etc. are relaxed and blunted, so that electromagnetic noise can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれ本発明の第1及び第2の実
施例を示す回路図、第3図は従来のスイッチング電源制
−御回路の一例を示す回路図である。 1・・・電圧変動検出回路、2・・・パルス幅変調回路
、3・・・スイッチング制御回路、4・・・過電流検出
制御回路、5,5A・・・インピーダンス制御回路、6
・・・スイッチング回路、7・・・整流平滑回路、A1
・・・演算増幅器、A2・・・コンパレータ、A3・・
・演算増幅器、DI、D2・・・定電圧ダイオード、D
3・・・ダイオード、Ql、Q2・・・トランジスタ、
Q、・・・接合型FET、Qp・・・パワーMOSFE
T、R1〜R8・・・抵抗、T1・・・スイッチング電
源トランス
1 and 2 are circuit diagrams showing first and second embodiments of the present invention, respectively, and FIG. 3 is a circuit diagram showing an example of a conventional switching power supply control circuit. DESCRIPTION OF SYMBOLS 1... Voltage fluctuation detection circuit, 2... Pulse width modulation circuit, 3... Switching control circuit, 4... Overcurrent detection control circuit, 5, 5A... Impedance control circuit, 6
...Switching circuit, 7...Rectifier smoothing circuit, A1
...Operation amplifier, A2...Comparator, A3...
・Operation amplifier, DI, D2... Constant voltage diode, D
3...Diode, Ql, Q2...Transistor,
Q,... Junction FET, Qp... Power MOSFE
T, R1 to R8...Resistor, T1...Switching power supply transformer

Claims (1)

【特許請求の範囲】[Claims] 整流平滑回路の出力電源電圧の変動に応じたレベルのパ
ルス幅制御電圧を出力する電圧変動検出回路と、前記パ
ルス幅制御電圧のレベルに対応したパルス幅のパルス列
信号を出力するパルス幅変調回路と、1次電源の第1及
び第2の電源端子間に直列接続された2つのトランジス
タを備え前記パルス列信号により出力端と前記第1及び
第2の電源端子との間を交互にオン・オフしスイッチン
グ制御信号を出力するスイッチング制御回路と、前記ス
イッチング制御信号をゲート電極に入力してオン・オフ
するパワーMOSFETと2次側に前記整流平滑回路を
接続したスイッチング電源トランスとを前記1次電源の
第1及び第2の電源端子間に直列接続したスイッチング
回路とを有するスイッチング電源制御回路において、前
記スイッチング制御回路の出力端と前記パワーMOSF
ETのゲート電極との間に過電流検出制御信号のレベル
に応じてオン抵抗が制御されるトランジスタを備えたイ
ンピーダンス制御回路を設け、前記スイッチング回路と
前記1次電源の第1の電源端子との間にこのスイッチン
グ回路と直列に接続された過電流検出用の抵抗を備えこ
の抵抗の端子間電圧に応じて所定のレベルの前記過電流
検出制御信号を出力する過電流検出制御回路を設けたこ
とを特徴とするスイッチング電源制御回路。
a voltage fluctuation detection circuit that outputs a pulse width control voltage with a level corresponding to fluctuations in the output power supply voltage of the rectifying and smoothing circuit; and a pulse width modulation circuit that outputs a pulse train signal with a pulse width corresponding to the level of the pulse width control voltage. , comprising two transistors connected in series between the first and second power supply terminals of the primary power supply, and alternately turns on and off between the output terminal and the first and second power supply terminals according to the pulse train signal. A switching control circuit that outputs a switching control signal, a power MOSFET that inputs the switching control signal to a gate electrode to turn it on and off, and a switching power transformer that connects the rectifying and smoothing circuit to the secondary side of the primary power source. In a switching power supply control circuit having a switching circuit connected in series between first and second power supply terminals, an output terminal of the switching control circuit and the power MOSFET
An impedance control circuit including a transistor whose on-resistance is controlled according to the level of an overcurrent detection control signal is provided between the gate electrode of the ET, and a connection between the switching circuit and the first power supply terminal of the primary power supply is provided. An overcurrent detection control circuit is provided, which includes an overcurrent detection resistor connected in series with the switching circuit in between, and outputs the overcurrent detection control signal at a predetermined level according to the voltage between the terminals of the resistor. A switching power supply control circuit featuring:
JP17061588A 1988-07-08 1988-07-08 Switching power supply controlling circuit Pending JPH0223062A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17061588A JPH0223062A (en) 1988-07-08 1988-07-08 Switching power supply controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17061588A JPH0223062A (en) 1988-07-08 1988-07-08 Switching power supply controlling circuit

Publications (1)

Publication Number Publication Date
JPH0223062A true JPH0223062A (en) 1990-01-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP17061588A Pending JPH0223062A (en) 1988-07-08 1988-07-08 Switching power supply controlling circuit

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59221347A (en) * 1983-05-31 1984-12-12 Mitsui Petrochem Ind Ltd Thermoplastic elastomer composition having excellent injection weldability
US8839535B2 (en) 2006-03-30 2014-09-23 Esco Corporation Wear assembly
US9222353B2 (en) 2008-01-08 2015-12-29 Esco Corporation Tip for an earth working roll

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59221347A (en) * 1983-05-31 1984-12-12 Mitsui Petrochem Ind Ltd Thermoplastic elastomer composition having excellent injection weldability
JPH0410505B2 (en) * 1983-05-31 1992-02-25
US8839535B2 (en) 2006-03-30 2014-09-23 Esco Corporation Wear assembly
US9650764B2 (en) 2006-03-30 2017-05-16 Esco Corporation Wear assembly for use on earth working equipment
US9816254B2 (en) 2006-03-30 2017-11-14 Esco Corporation Wear assembly for use on earth working equipment
US10829912B2 (en) 2006-03-30 2020-11-10 Esco Group Llc Wear assembly for use on earth working equipment
US9222353B2 (en) 2008-01-08 2015-12-29 Esco Corporation Tip for an earth working roll

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