JPH08331023A - Identification system - Google Patents

Abstract

PURPOSE: To send a signal in plural bits for a reverberation stop period in the identification system where an intermitted signal is sent from a write/read control unit and the signal is sent while controlling reverberation with a data carrier for an oscillation stop period. CONSTITUTION: In the case of sending a signal from a data carrier 30, the signal of 2-bit each is coded by a coding circuit 63 for a reverberation stop period. Then a shunt timing control circuit 64 controls a generating timing of a shunt pulse. Thus, the reverberation is controlled via a shunt circuit 41. Thus, a write/read control unit demodulates a signal based on a timing for reverberation stop.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a physical distribution system for managing tools and products and an identification system used for identifying a human body.

[0002]

2. Description of the Related Art Conventionally, a system for identifying and managing various articles such as tools, parts and products in order to mechanize the management of tools of machine tools and the identification of parts and products in an assembly and conveyance line in a factory. Is required. Therefore, JP-A-1-151831
As shown in the item No., a memory unit (data carrier) having a memory is provided in the identification object, and necessary information is written in such a memory by data transmission from the outside, and the information is stored as necessary. An identification system for reading out is proposed.

As shown in FIG. 6, such a conventional identification system comprises a write / read control unit including an ID controller 1 and a read / write head (RWH) 2 and a data carrier 3. Then, the read / write head 2 intermittently oscillates at a constant frequency and the data carrier 3
A signal having a constant duty ratio is transmitted when data is received, and the reverberation is controlled by the resonance circuit in the data carrier. In the read / write head 2, the signal is received by determining the presence or absence of this reverberation by the resonance circuit.

In FIG. 6, the write / read control unit has first and second duty ratios corresponding to a transmission data signal when transmitting data from the read / write head 1 side to the data carrier 3, and when receiving data. It generates a transmission signal of a constant frequency, which is intermittent with a constant third duty ratio, for example, a duty ratio of 50%. First
The duty ratio is 30%, and the second duty ratio is 70%. This signal is transmitted to the transmission circuit 12, the oscillation is interrupted, and the transmission coil L1 is driven.
The coil L1 is provided on the surface facing the data carrier 2. Further, the receiving circuit 14 is provided with a resonance circuit 13 including a coil L2 and a capacitor C1. The output obtained from the resonance circuit 13 is received by the reception circuit 14 and transmitted to the envelope detection circuit 16 via the amplification circuit 15. The envelope detection circuit 16 performs envelope detection of the input signal,
The output is given to the decision circuit 17. The determination circuit 17 discriminates the input signal into H or L level based on a predetermined threshold value and outputs it as a reception signal.

FIG. 7 is a block diagram showing the structure of a conventional data carrier 3. In the figure, the data carrier 3 has a resonance circuit 31. The resonance circuit 31 is the coil L3.
And a capacitor C2 connected in parallel with the coil L3. A full-wave rectification circuit 32 is connected to both ends of the resonance circuit 31. The full-wave rectification circuit 32 performs full-wave rectification on the obtained signal and supplies it as a power supply Vcc to each part of the data carrier via the power supply circuit 33.

A DEM extraction circuit 34 is connected to one end of the resonance circuit 31. The DEM extracting circuit 34 converts the carrier of the transmission signal into a square wave by half-wave rectifying and shaping the carrier of the transmission signal as a passing frequency, and its output is given to the demodulation circuit 35. Further, the integration comparator circuit 36 is connected to one end of the resonance circuit 31. The integration comparator circuit 36 performs envelope detection of the signal obtained in the resonance circuit 31, discriminates the power supply with a threshold value obtained by dividing the power supply, extracts the clock signal CKA, and outputs the output to the demodulation circuit 35. . When the data carrier receives a signal, the demodulation circuit 35 counts the number of carrier pulses extracted by the DEM extraction circuit 34 based on CKA, and determines either the H level or the L level depending on the duty ratio of intermittent transmission. To do. The signal thus demodulated is separated into a command and data by the memory control unit 37, necessary data is written in the memory 38, and data is read from the memory 38. The NRZ signal read from the memory control unit 37 is converted into the conversion circuit 4
It is converted into a serial bi-phase code by 0 and input to the shunt pulse generation circuit 39. The shunt pulse generation circuit 39 generates a shunt pulse by the logical product of these, and is input to the shunt circuit 41. The shunt circuit 41 has a pair of switching elements that ground both ends of the resonance circuit 31 based on a shunt pulse, and grounds both ends of the resonance circuit at the same time to stop reverberation in a short time.

Next, the waveforms of the write / read control unit and each part of the data carrier will be described. Figure 8 (a)
(G) shows the waveform of each part of a-g of FIG. 6, FIG. FIG. 8A shows a waveform of the transmission circuit 12 when the read / write head 2 receives a signal from the data carrier 3. Further, FIG. 8B shows transmission data transmitted from the data carrier to the write / read control unit.
It is assumed that one bit, that is, "1" or "0" is transmitted during the cycle as shown. A shunt pulse is not generated in the "1" level transmission, and a shunt pulse is generated in the "0" level transmission by the shunt pulse generation circuit 39 immediately after the transmission is stopped as shown in FIG. 8C. Due to the generation of this shunt pulse, the reverberation of the resonance waveform of the data carrier is stopped as shown in FIG. Therefore, "1"
Reverberation remains when transmitting level data, and reverberation is stopped when transmitting “0” level. This signal is received by the receiving coil L2 of the read / write head 2 as shown in FIG. 8 (e), and is received and amplified by the receiving circuit 14 to perform envelope detection. FIG. 8 (f) shows this envelope detection waveform, and by discriminating this signal with a predetermined threshold value, the transmission signal is demodulated as shown in FIG. 8 (g).

[0008]

However, in such a conventional communication system from the data carrier to the read / write head, since data is discriminated by the presence or absence of reverberation vibration, one bit is used in one cycle. Only the data of was able to be transmitted. Further, in the conventional data transmission method, since the envelope detection is performed on the read / write head side, there is a drawback that the signal is not easily demodulated normally because it is easily affected by constant noise such as white noise.

The present invention has been made in view of such conventional problems, and it is an object of the present invention to transmit a plurality of bits by one reverberation and improve noise resistance.

[0010]

SUMMARY OF THE INVENTION The present invention is an identification system comprising a data carrier and a write / read control unit for transmitting data to said data carrier and receiving the transmitted data. The read / write control unit includes a modulation circuit that generates a transmission signal having a constant duty ratio when receiving data, a transmission circuit that has a first coil, and intermittently oscillates oscillation based on the transmission signal provided from the modulation circuit. A receiving circuit including a second coil, for receiving reverberant vibration obtained when the oscillation of the transmitting circuit is stopped, a synchronous detecting means for synchronously detecting reverberant vibration obtained by the receiving circuit, and a synchronous detecting means. Demodulation means for demodulating the signal transmitted from the data carrier based on the pulse width of the detection signal, wherein the data carrier is a third coil. And a demodulation circuit for demodulating a signal based on an envelope signal of a signal received by the resonance circuit, and a code for encoding transmission data to be transmitted to the write / read control unit in units of a plurality of bits. By a shunt pulse from the shunt timing control circuit, and a shunt timing control circuit that generates a shunt pulse with different reverberation stop timing generated in the resonance circuit based on the encoded data of the encoding circuit. And a reverberation control circuit that controls reverberation of the resonance circuit.

[0011]

According to the present invention having such characteristics, when transmitting a signal from the data carrier to the write / read control unit, the oscillation of the write / read control unit is stopped in one cycle of the oscillation interruption. At times, a plurality of bits of data are coded by a coding circuit to control the timing of shunt pulses. The write / read control unit receives this signal and detects the pulse width during the reverberation by the synchronous detection means. Then, the original signal is demodulated based on the pulse width.

[0012]

1 is a block diagram showing the structure of a write / read control unit of an identification system according to an embodiment of the present invention. The same parts as those of the above-mentioned conventional example are designated by the same reference numerals for detailed description. Omit it. In this embodiment, the read / write head 2
The configuration of the modulation circuit 11, the transmission circuit 12 and the transmission coil L1 is the same as that of the conventional example, and the output of the resonance circuit 13 is transmitted through the reception circuit 14 to the bandpass filter (BPF) 51 of the ID controller 4 and the amplification circuit 52. Entered in. The amplifier circuit 52 amplifies the signal passed through the bandpass filter 51, and its output is input to the synchronous detection circuit 53. The synchronous detection circuit 53 performs synchronous detection based on the synchronous clock generated from the transmission clock, and its output is given to the pulse counter 54. The pulse counter 54 counts the counting clock signal based on this synchronous output, and the count value is the determination circuit 55.
Is input to The judgment circuit 55 discriminates the count value from a predetermined threshold value and demodulates the received data. The synchronous clock generation circuit 56 is for generating a synchronous clock from the transmission clock. Here, the pulse counter 54 and the determination circuit 55 constitute a demodulation means for demodulating the signal from the pulse width of the synchronous detection signal.

Next, the data carrier that constitutes the identification system together with the write / read control unit will be described with reference to FIG. In this figure, the same parts as those of the conventional example described above are designated by the same reference numerals, and detailed description thereof is omitted. In this embodiment, a variable resistor R whose resistance value changes according to a control signal from the outside is connected in series to the resonance circuit 31 of the data carrier 30. As in the conventional example, the data carrier 30 has a full-wave rectification circuit 32 connected to both ends of a resonance circuit 31, and power is supplied to each part via a power supply circuit 33. Further, the DEM extraction circuit 34, the demodulation circuit 35, the integration comparator circuit 36, and the memory 38 are the same as those of the conventional data carrier described above. The output of the demodulation circuit 35 is the control unit 6
1, the control unit 61 separates the data and the command, and writes the data in the memory based on the write command.
Or read the data. Further, when transmitting and receiving data, the control value of this control signal is switched by the Q control circuit 62 based on the signal from the control section 61.
That is, the resistance value is set to 0 or a small value when data is transmitted from the data carrier to the read / write head side, and when the data carrier receives data, the resistance value is increased to control the Q of the resonance circuit. The signal read from the control unit 61 is input to the encoding circuit 63. The encoding circuit 63 uses a plurality of bits of data to be transmitted,
Here, the data is encoded in units of 2 bits, and its output is input to the shunt timing control circuit 64. The shunt timing control circuit 64 controls the timing of generating a shunt pulse after the carrier transmitted from the read / write head is stopped according to the transmission data to be transmitted, and its output is input to the shunt circuit 41. . The shunt circuit 41 is similar to the above-mentioned conventional example,
The reverberation is controlled by grounding both ends of the resonance circuit 31.

Next, the data transmission method according to this embodiment will be described with reference to FIG. The transmission signal read from the memory 38 and transmitted to the read / write head side is an encoding circuit 63.
Are separated by 2 bits. This data is "0
It is one of "0", "01", "10", and "11", and the timing for generating the shunt pulse is controlled as shown in FIG. 3 according to the transmission data. That is, when transmitting the data “00” as shown in FIG. 3A, after a certain time T ₀₀ has elapsed from the rising edge of the transmitted signal shown in FIG. A shunt pulse of Ts shall be generated. Data "01"
When transmitting, the shunt pulse having the pulse width Ts is generated after the time T ₀₁ has elapsed after the rising of the transmission waveform as shown in FIG. 3B. Similarly, when transmitting the data “10”, as shown in FIG. 3C, after the rising of the transmission waveform from the read / write head, time T ₁₀ is reached.
It is assumed that a shunt pulse having a pulse width Ts is generated after the passage of. When transmitting the data "11", the shunt pulse is not generated as shown in FIG. Here, T ₀₀ + Ts = T ₀₁ T ₀₁ + Ts = T ₁₀ . T ₀₀ is set equal to 50% of one cycle of intermittent carrier transmission from the read / write head, and the maximum reverberation time is set to 3 Ts or more. That is, the reverberation time is divided and used for transmission of each data.

In this way, the signal received by the receiving coil L2 of the read / write head 2 has its level and pulse width changed according to the timing of the shunt pulse, as shown in FIGS. Therefore, the ID controller 4
Performs synchronous detection and converts it into a signal having a pulse width corresponding to the received data, whereby the 2-bit signal can be demodulated on the ID controller 4 side.

Next, the operation of this embodiment will be described with reference to FIG. FIGS. 4A to 4H are waveform charts showing the waveforms of the respective portions a to h in FIGS. FIG. 4A shows a transmission waveform transmitted from the read / write head 2. The read / write head 2 intermittently oscillates at a duty ratio of 50% when receiving a signal from the data carrier 30 as in the above-described conventional example. FIG. 4B shows transmission data transmitted from the data carrier to the read / write head 2 side. In this embodiment, since a 2-bit signal is transmitted to the read / write head 2 side in one cycle, the transmission data is read from the memory 38 at a speed corresponding to this. Then, the data carrier 30 encodes the data by the encoding circuit 63 based on the transmission data, and controls the timing of the shunt pulse. That is, as shown in FIG. 4 (c), at the time of transmission of "10", after the rise of the oscillation from the read / write head T
_A shunt pulse is generated after ₁₀ passes. In the next cycle, if the transmission data is "01", a shunt pulse is generated after T ₀₁ has elapsed after the rising of the transmission waveform. Also in transmission of "00" generates a shunt pulse after T _00, the transmission data is not generated a shunt pulse at "11". By doing so, the waveform of the resonance circuit 31 of the data carrier becomes as shown in FIG. 4 (d), and the width of the reverberation is controlled. Therefore, the signal received by the coil L2 of the read / write head 2 is as shown in FIG. This signal is amplified by the amplifier circuit 52 via the bandpass filter 51. Then, by the synchronous detection circuit 53, FIG.
Synchronous detection is performed as shown in.

FIG. 5 is a waveform diagram showing in detail the waveform of each part of the write / read control unit. When reverberant vibration is obtained in the receiving circuit 14 as shown in FIG. 5A, the output shown in FIG. 5B is obtained by amplifying it through the bandpass filter 51, and this is output by the synchronous detection circuit 53. When binarized, the signal shown in FIG. 5C is obtained. This signal is synchronously detected by the synchronous clock. This synchronous detection is the same signal as the transmission clock considering the group delay due to the filter of the read / write head, etc., and the rectangular wave signal is generated by the synchronous clock without noise as shown in FIGS. 4 (f) and 5 (e). Will be detected. The length of this signal is counted by the pulse counter 54. If a clock signal having a frequency higher than that of the synchronous clock is used as the counting clock, the pulse width can be measured more accurately. Therefore, the original data can be demodulated based on the pulse width. The determination circuit 55 counts the pulse width based on this count value, and demodulates the original 2-bit signal, that is, "00" to "11" based on the pulse width.
In this way, the original signal can be demodulated as shown in FIG.

In this embodiment, a 2-bit signal is coded for data transmission within a time period in which reverberation of one cycle occurs, but it is possible to code a larger number of bits for data transmission. .

[0019]

As described in detail above, according to the present invention, since data is transmitted by changing the timing of the shunt pulse, conventionally, only 1 bit of data is transmitted at the time when one cycle of reverberation occurs. Although not possible, transmission of 2 bits or more is possible. Therefore, the conventional transmission speed can be significantly increased. Further, since the length of the reverberation vibration is determined, it is possible to obtain the effect that the noise resistance can be improved as compared with the conventional envelope detection.

[Brief description of drawings]

FIG. 1 shows the writing / writing of an identification system according to an embodiment of the present invention.
It is a block diagram showing a configuration of a read control unit.

FIG. 2 is a block diagram showing a configuration of a data carrier of the present embodiment.

FIG. 3 is a schematic diagram showing data transmission when transmitting from the data carrier to the read / write head side according to the present embodiment.

FIG. 4 is a time chart showing the operation of this embodiment.

FIG. 5 is a time chart showing a synchronous detection and an operation of demodulating a signal based on the synchronous detection according to the present embodiment.

FIG. 6 is a block diagram showing a configuration of a write / read control unit of a conventional identification system.

FIG. 7 is a block diagram showing a configuration of a conventional data carrier.

FIG. 8 is a time chart showing the operation of the conventional identification system.

[Explanation of symbols]

 1,4 ID controller 2 Read / write head 3,30 Data carrier 11 Modulation circuit 12 Transmission circuit 13,31 Resonance circuit 14 Reception circuit 15,52 Amplification circuit 51 Bandpass filter 53 Synchronous detection circuit 54 Pulse counter 55 Judgment circuit 56 Synchronous clock Generation circuit 61 Control unit 62 Q control circuit 63 Encoding circuit 6 Shunt timing control circuit

Claims (1)

[Claims] 1. An identification system comprising: a data carrier; and a write / read control unit for transmitting data to the data carrier and receiving the transmitted data, wherein the write / read control unit comprises: A modulation circuit that generates a transmission signal with a constant duty ratio when receiving data, a transmission circuit that has a first coil, and intermittently oscillates oscillation based on the transmission signal given from the modulation circuit, and a second coil A receiving circuit for receiving reverberant vibration obtained when oscillation of the transmitting circuit is stopped; a synchronous detecting means for synchronously detecting reverberant vibration obtained by the receiving circuit; and a pulse width of a detection signal obtained by the synchronous detecting means. And a demodulation means for demodulating a signal transmitted from the data carrier, wherein the data carrier includes a resonance circuit including a third coil. A demodulation circuit for demodulating a signal based on an envelope signal of a signal received by the resonance circuit; an encoding circuit for encoding transmission data to be transmitted to the write / read control unit in units of a plurality of bits; A shunt timing control circuit that generates shunt pulses with different reverberation stop timings that occur in the resonance circuit based on encoded data of the rectification circuit; and control the reverberation of the resonance circuit by the shunt pulse from the shunt timing control circuit. Reverberation control circuit
An identification system characterized by having.