JP2730186B2 - Data communication system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication system used for a tool of a machine tool, a part or product management in a factory, a distribution system, or the like.

[Conventional technology]

2. Description of the Related Art Conventionally, a system for identifying and managing various articles such as tools, parts, products, and the like is required to mechanize the management of tools of machine tools and the identification of parts and products on an assembly and transfer line in a factory. Therefore, a data carrier having a memory is provided in the object to be identified as disclosed in Japanese Patent Application Laid-Open No. 63-221950, and necessary information is written in the memory of the data carrier by external data transmission, and the information is read as necessary. There has been proposed a data communication system for transmitting data.

[Problems to be solved by the invention]

In such a conventional identification system, however, a plurality of write / read control units and the like are connected to a host computer, and a data carrier 3 is provided on a pallet 101 passing through a transport path 100 as shown in FIG. If the head units of the write / read control unit are arranged on the sides of the head unit, there is a possibility that they will interfere with each other depending on the distance between the head units. Therefore, it is specified in advance that the interval between the head units is separated by a predetermined position or more so as not to cause interference, but they may be arranged close to each other regardless of this installation standard,
There is a disadvantage that mutual interference may occur during data transmission.

The present invention has been made in view of such a problem of the conventional data communication system, and can easily recognize mutual interference when the head units of the write / read control unit are arranged close to each other. It is a technical task to do so.

[Means for solving the problem]

The present invention relates to a data communication system for performing half-duplex data transmission of serial data between a write / read control unit and a data carrier, wherein the write / read control unit is provided on a surface facing the data carrier. An oscillator having a first coil, and first and second duty ratios corresponding to the transmission data signal during data transmission, and constant third and fourth duty ratios during data reception and mutual interference confirmation, respectively. A transmission pulse generating means for generating a fixed-period transmission pulse signal having the following, and intermittently oscillating the oscillation by applying the fixed-period transmission pulse signal to the oscillator, and having a resonance frequency substantially equal to the oscillation frequency of the oscillator. A first coil including a second coil provided on a surface facing the data carrier.
A signal corresponding to the transmission pulse of the transmission pulse generation means is given, and the reception gate signal which has a timing when the oscillation of the oscillator is stopped at the time of data reception and continuously opens the gate at the time of mutual interference check is generated. A receiving gate signal generating means for generating a signal having a fourth duty ratio by the transmission pulse generating means and a receiving gate signal for continuously opening the gate by the receiving gate signal generating means at the time of mutual interference confirmation. Switch means for selecting whether or not, a detection circuit for detecting an electromagnetic induction signal obtained in the first resonance circuit while the reception gate signal of the reception gate signal generation means is given, and a detection circuit for detecting the electromagnetic induction signal at a predetermined timing of the reception gate signal. A sample and hold circuit for sampling the output, and a second for discriminating a hold signal of the sample and hold circuit at a predetermined level. And an operation display means for displaying the output of the detection circuit when mutual interference is confirmed, wherein the data carrier has a resonance frequency substantially equal to the oscillation frequency of the oscillator of the write / read control unit. A second resonance circuit including a third coil provided on a surface facing the write / read control unit; a detection circuit for detecting a signal obtained by the second resonance circuit; A second comparator for obtaining a transmission pulse signal by discriminating at a threshold level, and a second comparator based on a comparison signal of the second comparator.
A clock discriminating circuit for discriminating and shaping an oscillation signal obtained in the resonance circuit of the first embodiment, and a first and a second discriminating circuits based on the output of the second comparator and the clock signal of the clock discriminating circuit when receiving data from the write / read control unit. A data demodulating means for demodulating a transmission data signal from a transmission pulse signal having a duty ratio of 2; and a switching element connected between the second resonance circuit and the ground. The reverberation generated in the second resonance circuit is controlled by intermittently switching the switching element corresponding to the transmission data at the timing of stopping the oscillation of the oscillator based on the transmission pulse signal having the third duty ratio obtained from the second comparator. And reverberation control means.

[Action]

According to the present invention having such features, the write / read control unit interrupts the oscillation of the oscillator at a constant cycle,
At the time of transmission, the binary signal is transmitted to the data carrier side by changing the duty ratio. The data carrier side demodulates the transmission pulse signal by detecting this signal and discriminating it at a predetermined threshold level, and at the same time, shapes the oscillation signal of the oscillator obtained from the writing / reading control unit into a clock, and converts the clock signal into a clock signal. The original transmission data signal is demodulated by discriminating the duty ratio based on the duty ratio. When transmitting data from the data carrier to the write / read control unit, the oscillation of the oscillator is interrupted by the write / read control unit at a constant third duty ratio. By switching a switch provided in the resonance circuit in accordance with a transmission data signal, reverberation obtained in the resonance circuit of the write / read control unit is controlled. The writing / reading control unit generates a reception gate signal within the oscillation stop period based on the transmission pulse signal given to the oscillator, and extracts only the reverberation by the reception gate signal and detects the reverberation. The reception gate signal is sampled at a predetermined timing, applied to a first comparator, and discriminated at a predetermined threshold level to demodulate a transmission signal obtained from a data carrier.

In order to recognize the mutual interference of a plurality of write / read control units arranged close to each other, one write / read control unit drives an oscillator with a transmission pulse signal having a constant duty ratio, and drives the other oscillator. The writing / reading control unit continuously opens the reception gate signal, detects the signal obtained at that time, and displays the level by the operation display means for mutual interference.

〔The invention's effect〕

As described above, according to the present invention, half-duplex data transmission of serial data is performed between two units by using electromagnetic coupling, and when mutual interference is identified, one of the write / read control is performed. Intermittently oscillate the oscillator with the unit,
The other write / read control unit opens the reception gate and indicates whether there is mutual interference based on the reception level. Therefore, if the level of the detection output is low, it is determined that there is no mutual interference, and if this level is high, it is determined that mutual interference is likely to occur. Therefore, it is possible to easily recognize the mutual interference between the write / read control units. The effect that it can be obtained is obtained.

[Explanation of Example]

FIG. 2 is a block diagram showing the overall configuration of the data communication system according to one embodiment of the present invention. In this figure, the data communication system includes a write / read control unit 1 and an article 2
And the like. The write / read control unit 1 has first and second coils L1 and L2 at a position facing the data carrier 3, and the data carrier 3 has a third coil at a position facing these coils.
Has L3. The write / read control unit 1 is connected to, for example, a higher-order control device 4. The host control device 4 sends a transmission control signal (CT) to the write / read control unit 1.
Is transmitted, the transmission data SD is transmitted, and the reception data RD obtained from the write / read control unit 1 is read.

As shown in a detailed block diagram in FIG. 1, the write / read control unit 1 includes a clock generator 11 for generating a fixed clock signal, a time controller 12 for generating a timing signal based on the clock signal, and a transmission unit. A pulse generation circuit 13 is provided. The time controller 12 is a transmission control signal (CT) obtained from the upper control device 4
Is given, a transmission / reception switching signal is sent to the transmission pulse generation circuit 13 and the reception gate generation circuit 14. The upper control device 4 sends the transmission data SD to the transmission pulse generation circuit 13 after giving this transmission control signal. . The transmission pulse generation circuit 13 counts the clock of the clock generator 11 at a predetermined cycle at the timing when the reception switching signal is in the transmission state from the time controller 12, and performs the first and second duty ratios according to the transmission data SD at a fixed cycle. The output is given to the oscillator 15.
The oscillator 15 oscillates at a constant frequency only when a transmission pulse signal is given from the transmission pulse generation circuit 13, and its oscillation output is transmitted through the amplifier 16 to the first
To the coil L1. The write / read control unit 1 is provided with a second coil L2 for reception.
A capacitor C1 is connected in parallel to the coil L2 to form a first resonance circuit 17 that resonates with the oscillation frequency of the oscillator 15, and an induced voltage obtained at both ends thereof is supplied to the amplifier 18. The amplifier 18 amplifies the induced voltage, and supplies its output to the detection circuit 20 via the analog switch 19.
The reception gate generation circuit 14 generates a reception gate signal delayed by a predetermined time, for example, one clock from the fall of the transmission pulse when the transmission / reception switching signal provided by the time controller 12 is in a reception state during normal data transmission. When a mutual interference is determined, a reception gate signal for continuously opening the gate is generated. The reception gate signal is provided to the analog switch 19 as a gate signal. Clock generator 11 and reception gate generation circuit
The 14 reception gate signals are also supplied to the sampling signal generation circuit 21. The sampling signal generation circuit 21 supplies a predetermined timing of the reception gate signal, for example, a signal for one clock immediately before the end to the sample and hold circuit 22 as a sampling signal. The detection circuit 20 detects a signal obtained through the analog switch 19 to obtain an integrated signal or its envelope signal. The detection signal is supplied to the sample-and-hold circuit 22. Sample hold circuit 22
Holds an input signal based on a sampling signal, and its output is supplied to a first comparator 23.
The comparator 23 obtains a binary signal by discriminating a signal held at a predetermined threshold level, and its output is given to the higher-level control device 4 as a reception signal RD. The output of the detection circuit 20 is also provided to a comparator 24. The comparator 24 is a comparator that compares the output obtained from the detection circuit 20 at the time of self-diagnosis with a predetermined threshold level, and the output is given to the display driving device 25. The display driving device 25 turns on a display means for confirming mutual interference, for example, a light emitting diode 26 or a level meter when a predetermined threshold level is exceeded. Switch 27 is a transmission pulse generation circuit
13 and a reception gate signal generation circuit 14. The switch 27 is provided with a switch signal to check the interference between the write / read control units.
The control signal for discontinuing the gate or for continuously opening the gate is supplied to the reception gate signal generation circuit.

As shown in FIG. 3, the data carrier 3 has a second resonance circuit 30 including a coil L3 and a capacitor C2 provided on a surface facing the write / read control unit 1, and an induced voltage at both ends thereof. Is the detection circuit 31 and the diode bridge
Given to 32. The detection circuit 31 detects this signal, and its output is given to the second comparator 33. The diode bridge 32 performs full-wave rectification of the induced voltage obtained in the resonance circuit and supplies the voltage to the constant voltage circuit 34. The constant voltage circuit 34 smoothes the rectified voltage and supplies it to each block of the data carrier 3 as a constant voltage. A predetermined threshold level is set in the comparator 33, and the detection output is discriminated by the threshold. The output of the comparator 33 is supplied to a clock discriminating circuit 35, a counter 36, and a digital comparator 37. The input end of the clock discriminating circuit 35 is connected to one end of the resonance circuit 30 as shown in the drawing, and detects a clock having an oscillation frequency obtained in the resonance circuit 30 when a transmission pulse is given. Clock signal to counter 36
Give to. The counter 36 counts this clock signal, and the count value is given to the digital comparator 37. The digital comparator 37 compares the count value of the counter 36 with a fixed count value when a comparison signal is given from the comparator 33, and outputs an "L" or "H" output depending on whether or not the count value is exceeded. The output is given to the memory control unit 38. The memory control unit 38 is connected to a memory 39 serving as a storage unit of the data carrier 3.
Since the signals obtained from the write / read control unit 1 are data and commands, the memory control unit 38 writes the data into the data memory 39 given based on the commands,
It controls to read the data in the memory 39. The output of the memory controller 38 is a reverberation control pulse generator 40.
Given to. The reverberation control pulse generator 40 outputs the transmission data based on the transmission data transmitted from the memory control unit 38 and transmitted to the write / read control unit 1 at a predetermined timing when the output of the comparator 33 becomes the “L” level. A reverberation control pulse having a predetermined width is generated when the signal is at the "H" level. Now, FETs 41 and 42 as switching elements are connected to both ends of the resonance circuit 30 via resistors between the respective ends of the resonance circuit 30 and the ground. The FETs 41 and 42 control the both ends of the resonance circuit 30 to be grounded based on the reverberation control pulse of the reverberation control pulse generator 40.

Here, the counter 36 and the digital comparator 37 transmit based on the discriminated clock signal and the output of the comparator 33 having the first and second duty ratios, that is, the transmission pulse signal given from the write / read control unit 1. The data demodulation means 43 for determining the data SD is configured. Further, FETs 41 and 42, which are switching elements for grounding both ends of the residual control pulse generator 40 and the resonance circuit 30, constitute reverberation control means 44 for controlling the reverberation of the resonance circuit 30.

(Operation of Embodiment) Next, the operation of the embodiment will be described with reference to a time chart. First, when a signal is transmitted from the writing / reading control unit 1 to the data carrier 3, the transmission control signal CT is transmitted from the higher-level control device 4 to the time controller 12.
Is sent. Then, the time controller 12 supplies a transmission switching signal to the transmission pulse generation circuit 13. Then the fourth
As shown in FIG.
A signal of SD (for example, “HLLH” as shown) is applied to the transmission pulse generation circuit 13. Transmission pulse generating circuit 13 That way the first corresponding to the logical level of the transmitted data in Figure 4 time t ₁ as shown in _{(b), t 3, t} 5 and constant period T than t ₆
1. Generate a transmission pulse signal having a second duty ratio. By this signal, the oscillation of the oscillator 15 is interrupted as shown in FIG. When the data carrier 3 are close Therefore, the driving time of the oscillator 15 as shown in FIG. 4 (d) across the resonant circuit 30, i.e., the time _{t 1 ~t 2, t 3 ~t} 4 ......
, A signal having a constant amplitude is obtained, and then a signal attenuating is obtained. Since this signal is detected by the detection circuit 31 and compared at a predetermined threshold level, the same signal as the transmission pulse signal as shown in FIG. 4 (e) is obtained by the comparator 33. Time t _{1 when} this signal is at “H” level
The ~t ₂ the clock signal as shown in FIG. 4 (f) are extracted. This signal is given to the counter 36 and counted. At time t ₄ when the counter 36 output when the count is started from the time t ₁ is greater than count the predetermined value at time t ₂ which falls is obtained, which starts counting from the time t ₃ In, a count value lower than a predetermined value is obtained. Accordingly, the digital comparator 37 discriminates the count value at times t ₂ and t ₄ , and transmits the transmission data as shown in FIG.
A signal is output to the memory control unit 38 at a timing one cycle behind SD. In this way, data can be transmitted from the write / read control unit 1 to the data carrier 3. In addition, unlike the FSK signal, since a signal of a constant frequency is only intermittent, the data transmission can be performed with high efficiency by keeping the resonance frequency of the resonance circuit 30 equal to the oscillation frequency of the oscillator 15. Further, as the output of the oscillator 15 of the write / read control unit 1 is increased, the voltage level induced in the data carrier 3 is increased accordingly, so that the communication distance can be increased by the oscillation output.

Next, write / read control unit 1 from data carrier 3
When data is transmitted to the transmission / reception control unit 1, first, the transmission / reception switching signal of the time controller 12 of the write / read control unit 1 is switched to the reception state, and the transmission pulse generation circuit 13 is turned on in FIG.
The transmission pulse signal of a constant period T with a constant third duty ratio, for example, a duty ratio of 50% as shown in FIG. In this case, since the oscillator 15 is periodically intermittent,
An oscillation signal as shown in FIG. 2B is transmitted from the coil L1 to the data carrier 3. Therefore, the comparator 33 outputs a clock signal having a duty of 50% as shown in FIG. 5 (c). A data signal is read from the memory control unit 38 based on the clock signal. FIG. 5D shows that the signal read from the memory control unit 38 is “HLHL”.
This shows an example of a signal which is given to a reverberation control pulse generator 40. The reverberation control pulse generator 40 outputs a reverberation control pulse having a predetermined width as shown in FIG. 5 (e) when the comparator 33 falls based on the logical level of this signal. This signal is applied to the FETs 41 and 42 and is interrupted. Thus, in FET41,42 off state, the attenuation signal to the resonant circuit 30 as shown at time t ₉ subsequent like of FIG. 5 (f) has occurred, at time t ₁₁ after turning on the FET41,42 Since both ends of the resonance circuit 30 are grounded, almost no reverberation occurs in the resonance circuit 30 of the data carrier 3. Meanwhile signal obtained in the resonant circuit 17 of the write / read control unit 1 is between the oscillator 15 time t ₈ ~t ₉ which is driven, t ₁₀ ~t ₁₁ ...... having constant high amplitude level, the Subsequent times t _{9 to} t
_{At 10} , t _{11 to} t ₁₂ , low-level reverberation remains according to the reverberation of the resonance circuit 30 of the data carrier 3. Then, as shown in FIGS. 5 (h) and 5 (i), the reception gate signal generation circuit 14 has a fixed period shorter than the period in which the transmission pulse is turned off.
A reception gate signal is generated, and the signal is transmitted to the detection circuit 20 via the analog switch 19 that is closed only during that time. Immediately before the fall, a sampling signal is supplied to the sample hold circuit 22 as shown in FIG. 5 (k). Therefore, the output of the sample and hold circuit 22 is relatively 23
Therefore, a signal as shown in FIG. 5A, that is, a memory read signal similar to that shown in FIG. 5D is sent from the comparator 23 to the write / read control unit 1 in the transmission cycle T.
Will be transmitted with a delay.

Now, an operation for identifying interference between the write / read control units of the data communication system will be described. In this case, as shown in FIG. 6, one of the plurality of write / read control units 1A, 1B... Is used for transmission. For example, the switch 27 of the write / read control unit 1A is set to the transmission state, and the switches 27 of the other write / read control units 1B and 1C are set for reception. Then write /
The transmission pulse generating circuit 13 of the read control unit 1A generates a fourth, for example, a transmission pulse having a duty ratio of 50%. Therefore, as shown in FIG. 7B, the oscillation circuit 15 oscillates intermittently. On the other hand, in the receiving units of the other write / read control units 1B and 1C close to this, the reception gate signal generated by the reception gate signal generation circuit 14 is continuously released as shown in FIG. 7 (c). . Then, an electromagnetic induction signal as shown in FIG. 7D is detected from the analog switch 19 according to the degree of mutual interference. This signal is detected by the detection circuit 20 and supplied to the comparator 24.
Accordingly, by appropriately setting the threshold level of the comparator 24, a signal discriminated from the predetermined threshold level by the comparator 24 is obtained as shown in FIG. 7 (f). When signals exceeding the threshold level are obtained in this way, it is considered that mutual interference occurs. Therefore, the light emitting diode 26 is turned on by increasing the distance between the write / read control units 1A and 1B or 1C. Set not to. This makes it very easy to recognize the interference between the write / read control units and set the position so that no interference occurs.

In the present embodiment, the light emitting diode is turned on when the threshold value exceeds the threshold level set by the comparator 24.However, it is also possible to check to what level the interference is occurring using a level meter or the like. Good.

In this embodiment, the write / read control unit is provided with switches for transmission and reception in order to confirm mutual interference. However, the operation mode may be set by a higher-level control device. Needless to say.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a write / read control unit of an embodiment of a data communication system according to the present invention, FIG. 2 is a block diagram showing an overall configuration thereof, and FIG. 3 shows a configuration of a data carrier. FIG. 4 is a block diagram, FIG. 4 is a time chart showing waveforms of respective parts when data is transmitted from the write / read control unit to the data carrier, and FIG. 5 is a time chart when a signal is transmitted from the data carrier to the write / read control unit. FIG. 6 is a schematic diagram showing settings for identifying the presence or absence of mutual interference according to the present embodiment, and FIG. 7 is a time chart showing the operation when the mutual interference is confirmed. 1, 1A, 1B, 1C ... write / read control unit, 3 ... data carrier, 4 ... control device, L1, L2, L3 ... coil, 11 ...
… Clock generator, 12 …… Time controller, 13 ……
Transmission pulse generation circuit, 14 ... Reception gate signal generation circuit,
15 ... Oscillator, 17,30 ... Resonant circuit, 19 ... Analog switch, 20,31 ... Detector circuit, 22 ... Sample hold circuit, 23,33 ... Comparator, 24 ... Comparator, 25 ... ... Display drive device, 26 ... Light emitting diode, 27 ... Switch, 34 ...
... Rectifying / smoothing circuit, 35 ... Clock discriminating circuit, 36 ... Counter, 37 ... Digital comparator, 38 ... Memory control unit, 39 ... Memory, 40 ... Residual control pulse generator, 4
1,42 …… FET, 43 …… Data demodulation means, 44 …… Reverberation control means

Claims (1)

(57) [Claims] 1. A data communication system for performing half-duplex data transmission of serial data between a write / read control unit and a data carrier, wherein the write / read control unit has a surface facing the data carrier. And an oscillator having a first coil provided in the first and second coils corresponding to a transmission data signal during data transmission.
Generating a transmission pulse signal of a constant cycle having a constant third and fourth duty ratios at the time of data reception and mutual interference confirmation, and applying the transmission pulse signal of the constant cycle to the oscillator. A first pulse circuit having a resonance frequency substantially equal to the oscillation frequency of the oscillator, and a second coil provided on a surface facing the data carrier; And a signal corresponding to a transmission pulse of the transmission pulse generation means is provided. The data has a timing at the time of oscillation stop of the oscillator at the time of data reception, and generates a reception gate signal for continuously opening the gate at the time of mutual interference confirmation. A reception gate signal generation unit, a generation of a signal having a fourth duty ratio by the transmission pulse generation unit, and Switch means for selecting any one of generation of a reception gate signal for continuously opening a gate by the gate signal generation means; and obtaining the first resonance circuit while the reception gate signal of the reception gate signal generation means is supplied. A detection circuit for detecting an electromagnetic induction signal to be obtained, a sample and hold circuit for sampling an output of the detection circuit at a predetermined timing of the reception gate signal, and a first comparator for discriminating a hold signal of the sample and hold circuit at a predetermined level. And an operation display means for displaying an output of the detection circuit at the time of confirming the mutual interference, wherein the data carrier has a resonance frequency substantially equal to an oscillation frequency of an oscillator of the write / read control unit. Including a third coil provided on a surface facing the write / read control unit.
A detection circuit that detects a signal obtained by the second resonance circuit; a second comparator that obtains a transmission pulse signal by discriminating the detection output at a predetermined threshold level; A clock discrimination circuit for discriminating and shaping an oscillation signal obtained in the second resonance circuit based on a comparison signal of the comparator, and an output of the second comparator when receiving data from the write / read control unit Data demodulating means for demodulating a transmission data signal from transmission pulse signals having first and second duty ratios based on a clock signal of the clock discrimination circuit; and a switching element connected between the second resonance circuit and ground. And stopping oscillation of the oscillator based on a transmission pulse signal of a third duty ratio obtained from the second comparator at the time of data transmission to the write / read control unit. Reverberation control means for controlling reverberation generated in the second resonance circuit by interrupting the switching element in response to transmission data at a stop timing.