JP2724363B2 - Data communication device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device for performing data communication between first and second units which are close to each other in a non-contact manner by using an induction electromagnetic field.

(Prior art)

Conventionally, as shown in, for example, JP-A-62-63050, a data storage device for holding respective tool data is provided in a tool shank of a machine tool or the like, and data is serially transferred from the data input / output device to the data storage device. 2. Description of the Related Art There has been proposed a data transmission device that transmits and writes data or reads written content. In such a data transmission device, communication between the data input / output device and the data storage device is performed by using a fixed high-frequency signal and performing frequency shift keying (FSK) modulation on the signal.

[Problems to be solved by the invention]

However, according to such a conventional data transmission device, a PLL circuit and the like for demodulating an FSK signal are required in the data storage device and the data input / output device, so that much power consumption is required. In some cases, a data storage device rectifies an AC voltage induced from a data input / output device and uses it as a power source. At this time, if the power consumption is large, data communication cannot be performed unless the induced voltage is high. It has the disadvantage of being shorter. Further, when a battery is provided on the data storage device side, there is a disadvantage that the battery life is shortened. On the other hand, the applicant transmits a binary logical level signal from the input / output device by matching the resonance frequency of the data storage device and the input / output device, intermittently intermittently transmitting a signal of a fixed frequency at a fixed period, and changing the duty ratio. A data communication device that transmits a signal having an intermediate duty ratio during reception and transmits a signal from a data storage device to a data input / output device has been proposed (not disclosed). In this case, the duty ratio of the intermittent transmission pulse is changed from the data input / output device to transmit the logic signal. However, even when the data input / output device is in the reception state, the data storage device has any of the logic levels. There is a disadvantage that data may be received erroneously as a signal, and the received data becomes uncertain.

The present invention has been made in view of such a problem of the data communication apparatus, and transmits a transmission signal to each other by changing the duty ratio using a carrier of a constant frequency, and simultaneously transmits data without error during reception. It is a technical task to enable transmission.

[Structure and effect of the invention]

(Means for Solving the Problems) The present invention is a data communication device for performing half-duplex data transmission of serial data between a first unit and a second unit, wherein the first unit is a second unit. An oscillator that oscillates a signal of a constant frequency, having a first coil provided on a surface facing the data, and has first and second duty ratios corresponding to a transmission data signal during data transmission, Occasionally, a transmission pulse signal of a constant cycle having a third duty ratio between the first and second duty ratios is generated, and the oscillation is intermittently generated by applying the transmission pulse signal of the constant cycle to an oscillator. A first coil having a resonance frequency substantially equal to the oscillation frequency of the oscillator and having a second coil provided on a surface facing the second unit;
A receiving gate signal generating means for receiving a signal corresponding to the transmission pulse of the transmission pulse generating means and generating a reception gate signal having a timing when the oscillation of the oscillator is stopped, and a reception gate signal of the reception gate signal generating means , A detection circuit for detecting an electromagnetic induction signal obtained in the first resonance circuit while receiving the signal, a sample and hold circuit for sampling the output of the detection circuit at a predetermined timing of the reception gate signal, and discriminating the hold signal of the sample and hold circuit. The second unit is provided on a surface facing the first unit and having a resonance frequency substantially equal to the oscillation frequency of the oscillator of the first unit. A second resonance circuit including a third coil, a detection circuit for detecting a signal obtained by the second resonance circuit, and a detection output that is a predetermined threshold level. A second comparator that obtains a transmission pulse signal by discriminating between the first and second duty ratios based on an output of the second comparator when receiving data from the first unit. A data demodulating means for demodulating the transmission data signal; and a clock signal obtained from the second resonance circuit while the comparison output obtained from the second comparator is provided, and a count value near the third duty ratio. And a switching element connected between the second resonance circuit and the ground, and a reception inhibition circuit for invalidating the reception data obtained by the data demodulation means when the data is obtained. The switching element is turned on and off in accordance with the transmission data at the timing when the oscillation of the oscillator is stopped based on the transmission pulse signal of the third duty ratio obtained from the second comparator. Reverberation control means for controlling reverberation vibration generated in the second resonance circuit.

(Operation) According to the present invention having such characteristics, the first unit intermittently oscillates the oscillation of the oscillator of a constant frequency at a constant period, and changes the duty ratio at the time of transmission to convert the binary signal into the second signal. To the unit side. The second unit demodulates the transmission pulse signal by detecting this signal and discriminating it at a predetermined threshold level, and further demodulates the original transmission data signal based on the duty ratio of the signal. When the first unit enters the receiving state, the first unit interrupts the oscillation of the oscillator by the third duty ratio between the first and second duty ratios. In the second unit, a signal having a third duty ratio is detected by counting a clock signal obtained from the resonance circuit based on the output of the comparator, and at that time, reception is prohibited. And when transmitting data from the second unit to the first unit,
When the oscillation of the oscillator is stopped by the third duty ratio which is more constant than the first unit, the switching element provided in the resonance circuit of the second unit is turned on and off in accordance with the transmission data signal, so that the resonance circuit of the first unit is turned off. The reverberation obtained is controlled. The first unit generates a reception gate signal within the oscillation stop period based on the transmission pulse signal supplied to the oscillator, and extracts only the reverberation by the reception gate signal to detect the reverberation. Then, the transmission signal obtained from the second unit is sampled at a predetermined timing of the reception gate signal, supplied to the first comparator, and discriminated by comparison with a predetermined threshold level or the signal level. I have to.

(Effects of the Invention) As described above, according to the present invention, the first and second electromagnetic couplings are utilized.
Half-duplex data transmission of serial data is performed between the second units. Since the data demodulation means of the second unit demodulates the signal based on the pulse width, there is no need to use a PLL circuit or the like, which is relatively simple and consumes less power. Therefore, when the power of the second unit is obtained from the first unit, the power consumption is small, so that the transmission distance can be lengthened. Even if the second unit is erroneously set to the receiving state, the third unit detects the third duty ratio of the oscillator transmitted from the first unit and inhibits the second unit from receiving. It is not performed and the possibility of malfunction can be eliminated. When data is transmitted from the second unit to the first unit, the reverberation of the signal obtained from the first unit is controlled based on the transmission data. When the oscillation output given to the unit is increased, the reverberation level can be increased accordingly. Therefore, the reverberation resonance signal obtained in the first unit also increases, so that the data transmission distance can be increased. Also, since the resonance circuits provided in the first and second units are made to substantially match the oscillation frequency of the oscillator, data transmission can be performed with high efficiency, and the SN ratio can be improved. The effect is also obtained.

[Explanation of Example]

(Configuration of Embodiment) FIG. 2 is a block diagram showing an overall configuration in which a data communication device according to an embodiment of the present invention is applied to an article identification system. In this figure, the data communication device has a write / read control unit 1 as a first unit and an ID unit 3 as a second unit attached to an article 2 or the like.
The write / read control unit 1 has first and second coils L1 and L2 at positions facing the ID unit 3, and the ID unit 3 also has third coils L3 at positions facing these coils. Have. The write / read control unit 1 is connected to, for example, a higher-order control device 4. The upper control device 4 performs writing /
After transmitting the transmission control signal (CT) to the read control unit 1, the transmission data SD is transmitted, and the reception data RD obtained from the write / read control unit 1 is read.

As shown in a detailed block diagram in FIG. 1, the write / read control unit 1 includes a clock generator 11 for generating a fixed clock signal, a time controller 12 for generating a timing signal based on the clock signal, and a transmission unit. A pulse generation circuit 13 is provided. The time controller 12 is a transmission control signal (CT) obtained from the upper control device 4
Is transmitted to the transmission pulse generation circuit 13 and the reception gate signal generation circuit 14, the host control device 4 sends the transmission data SD to the transmission pulse generation circuit 13 after giving the transmission control signal. send. The transmission pulse generation circuit 13 counts the clock of the clock generator 11 at a predetermined cycle at the timing when the reception switching signal is in the transmission state from the time controller 12, and performs the first and second duty ratios according to the transmission data SD at a fixed cycle. The output is given to the oscillator 15. The oscillator 15 oscillates at a constant frequency only when a transmission pulse signal is given from the transmission pulse generation circuit 13, and its oscillation output is supplied to a first coil L1 for transmission via an amplifier 16. Things. In this embodiment, the first duty ratio is 15 when the number of clocks of the clock generator 11 is 15.
As described above, the second duty ratio is 11 or less.

The write / read control unit 1 is provided with a second coil L2 for reception. A capacitor C1 is connected in parallel to the coil L2 to form a first resonance circuit 17 that resonates with the oscillation frequency of the oscillator 15, and an induced voltage obtained at both ends thereof is supplied to the amplifier 18. The amplifier 18 amplifies the induced voltage, and supplies its output to the detection circuit 20 via the analog switch 19. The reception gate signal generation circuit 14 generates a reception gate signal delayed by a predetermined time, for example, one clock from the fall of the transmission pulse when the transmission / reception switching signal provided by the time controller 12 is in the reception state. The reception gate signal is provided to the analog switch 19 as a gate signal. Clock generator 11
The reception gate signal of the reception gate signal generation circuit 14 is also given to the sampling signal generation circuit 21. The sampling signal generation circuit 21 supplies a predetermined timing of the reception gate signal, for example, a signal for one clock immediately before the end to the sample and hold circuit 22 as a sampling signal. The detection circuit 20 detects a signal obtained through the analog switch 19 to obtain an integrated signal or its envelope signal. The detection signal is supplied to the sample-and-hold circuit 22. The sample and hold circuit 22 holds an input signal based on a sampling signal, and its output is provided to a first comparator 23. The comparator 23 obtains a binary signal by discriminating a signal held by comparison with a predetermined threshold level or a previous signal level,
The output is given to the upper control device 4 as a reception signal RD.

As shown in FIG. 3, the ID unit 3 has a second resonance circuit 30 including a coil L3 and a capacitor C2 provided on a surface facing the write / read control unit 1, and induced voltages at both ends thereof. Is supplied to the detection circuit 31 and the diode bridge 32. The detection circuit 31 detects this signal, and its output is given to the second comparator 33. Further, the diode bridge 32 performs full-wave rectification of the induced voltage obtained in the resonance circuit 30 and supplies the voltage to the constant voltage circuit 34. The constant voltage circuit 34 smoothes the rectified voltage and supplies it to each block of the ID unit 3 as a constant voltage. A predetermined threshold level is set in the comparator 33, and the detection output is discriminated by the threshold. The output of the comparator 33 is supplied to a clock discriminating circuit 35, a counter 36, and a digital comparator 37. The input end of the clock discriminating circuit 35 is connected to one end of the resonance circuit 30. The input terminal of the clock discrimination circuit 35 detects a clock having an oscillation frequency obtained by the resonance circuit 30 when a transmission pulse is given. Give to 36. counter
A counter 36 counts this clock signal while being reset by the output of the comparator 33 and supplying a transmission pulse. The count value is supplied to a digital comparator 37. The digital comparator 37 compares the count value of the counter 36 with a fixed count value when the comparison signal is given from the comparator 33, and determines whether the count value has exceeded the count value by determining whether the count value has exceeded the count value.
Alternatively, an output of "H" is obtained, and the output is given to the memory control unit 38. The memory control unit 38 is connected to a memory 39 serving as a storage unit of the ID unit 3. Comparator 33
The output of the clock discrimination circuit 35 is provided to the reception inhibition circuit 40. The reception prohibition circuit 40 counts the clock signal based on the comparison output as described later, and supplies the reception prohibition signal to the memory control unit 38 when a count value in a certain range corresponding to the third duty ratio is obtained. is there.

Since the signals obtained from the write / read control unit 1 are data and commands, the memory control unit 38 writes the given data to the memory 39 based on the commands and reads the data in the memory 39. Is controlled. The memory controller 38 has a comparator as a reference clock.
The output of 33 is given, and the output of the read data is given to a reverberation control pulse generator 41. The reverberation control pulse generator 41 outputs a write / read signal from the memory control unit 38 at a predetermined timing when the output of the comparator 33 becomes “L” level.
A reverberation control pulse having a predetermined width is generated based on transmission data transmitted to the read control unit 1 when the transmission data is at the “L” level. By the way, FETs 42 and 43 as switching elements are connected to both ends of the resonance circuit 30 via respective resistors between the resonance circuit 30 and the ground. The FETs 42 and 43 control the both ends of the resonance circuit 30 to be grounded based on the reverberation control pulse of the reverberation control pulse generator 41.

Here, the counter 36 and the digital comparator 37 output the output of the comparator 33 having the first and second duty ratios, that is, write / read.
The data demodulation means 44 for determining the transmission data SD based on the transmission pulse signal given from the read control unit 1 is configured. The FETs 42 and 43 which are switching elements for grounding both ends of the resonance control pulse generator 41 and the resonance circuit 30 constitute reverberation control means 45 for controlling reverberation vibration of the resonance circuit 30.

Next, a detailed configuration of the memory control unit 38 and the reception inhibition circuit 40 of the present embodiment will be described with reference to FIG. The reception prohibition circuit 40 has a counter 51 for counting a clock signal based on an output of the comparator 33 and detectors 52 and 53 for detecting rising and falling of the comparator 33. The counter 51 counts the clock signal and is reset at the falling edge of the comparator to give a constant count value, for example, an output when counting 11 and 15, respectively.The count value output of `` 11 '' is output from the flip-flop 54. The count value output of “15” is supplied to the reset input terminal of the flip-flop 54 via the OR circuit 55 at the set input terminal. The flip-flop 54 has counters 11 to 15
The rising and falling detection outputs are supplied to the shift register 58 via the gate circuit 56 or 57 as a shift pulse and a reset pulse. The shift register 58 detects that the shift pulse has been repeated four times, and its four outputs are AND circuits that take a logical product.
59, and is provided as a reset signal of the memory control unit 38 as a reception inhibition signal.

On the other hand, the memory control unit 38 has an S / P conversion circuit 61 that converts a serial signal of the digital comparator 37 into a parallel signal, and a data decode circuit 62 that interprets data of the parallel signal. The output of the data decode circuit 62 is provided to a memory control circuit 63, and data is written to and read from the memory 39 via the memory control circuit 63. The read data is applied to the transmission control circuit 64,
The transmission signal is provided to the reverberation control pulse generator 41 after being converted into a serial signal. Further, a transmission signal which becomes “H” level during reception and “L” level during transmission and a reception inhibition signal from the AND circuit 59 are given to the AND circuit 65 of the memory control unit 38. The AND circuit 65 calculates the S / P conversion circuit 6
1 and the data decode circuit 62 are reset.

(Operation of Embodiment) Next, the operation of the embodiment will be described with reference to a time chart. First, when a signal is transmitted from the writing / reading control unit 1 to the ID unit 3, a transmission control signal CT is transmitted from the host control device 4 to the time controller 12. Then, the time controller 12 supplies a transmission switching signal to the transmission pulse generation circuit 13. After that, as shown in FIG.
(For example, “HLLH” as shown) is applied to the transmission pulse generation circuit 13. Then the transmission pulse generation circuit
13 first corresponding to a logical level of the transmitted data in Figure 5 time t ₁ as shown in _{(b), t 3, t} 5 and constant period T than t _6,
A transmission pulse signal having a second duty ratio is generated. In the present embodiment, the first duty ratio is set to 70%, and the second duty ratio is set to 30%. With this signal, the oscillation of the oscillator 15 is interrupted as shown in FIG. Therefore, when the ID unit 3 is close, the driving time of the oscillator 15, that is, the time, is set at both ends of the resonance circuit 30 as shown in FIG.
A signal having a constant amplitude is obtained at t _{1 to} t ₂ , t _{3 to} t ₄ ..., and a signal that attenuates thereafter is obtained. Since this signal is detected by the detection circuit 31 and compared at a predetermined threshold level, the same signal as the transmission pulse signal shown in FIG. 5 (e) is obtained by the comparator 33. This signal is provided to the counter 36 and the digital comparator 37. The fifth
The clock signal is discriminated by the clock discrimination circuit 35 as shown in FIG. Thus the predetermined value at the time t ₂ when the output falls when the counting from the time t ₁ is started the counter 36, for example greater than 13 count is obtained, the time when you start counting from time t ₃ at the time of t ₄ lower count than the predetermined value (13) is obtained. Accordingly, the digital comparator 37 discriminates the count value at times t ₂ and t ₄ ,
As shown in FIG. 5 (g), a signal is output to the memory controller 38 at a timing one cycle later than the transmission data SD. At this time, the reception prohibition circuit 40 changes its operation as shown in FIG.
As shown in (b) and (c), the rising of the comparator 33 resets the flip-flop 54. Then, as shown in FIGS. 6 (b) to 6 (e), the flip-flop 54 is set when 11 clocks are counted thereafter, and reset when the clock is counted further 15. Therefore the sixth
As shown in FIG.
1, When the transmission pulse signal of the second duty ratio is transmitted, the count value is almost “15” or more or “1”, respectively.
1 ”or less, the flip-flop 54 is always in the reset state at the time of the fall of the comparator 33, and the gate circuit 57
The reset signal is supplied to the shift register 58 via the control signal. Therefore, the logical product by the AND circuit 59 is not established, and the reception is not prohibited. Therefore, the write / read control unit 1
More data can be transmitted to the ID unit 3. Unlike the FSK signal, a signal having a constant frequency is only intermittently transmitted. Therefore, by keeping the resonance frequency of the resonance circuit 30 equal to the oscillation frequency of the oscillator 15, data transmission can be performed with high efficiency. Write / read control unit 1
When the output of the oscillator 15 is increased, the voltage level induced in the ID unit 3 increases accordingly, so that the communication distance can be increased by the oscillation output.

Next, when data is transmitted from the ID unit 3 to the write / read control unit 1, first, the write / read control unit 1
The transmission / reception switching signal of the time controller 12 is switched to the reception state, and the transmission pulse generation circuit 13 outputs the third duty ratio between the first and second duty ratios as shown in FIG. A transmission pulse signal having a constant period T with a duty ratio of% is generated. In this case, the oscillator 15 is periodically intermittently transmitted, so that an oscillation signal as shown in FIG. 7B is transmitted to the ID unit 3 from the coil L1. Accordingly, the comparator 33 outputs a comparison signal having a duty of 50% as shown in FIGS. 6 (a) and 7 (c). The flip-flop 54 is reset at times t ₈ , t _10, ... At the rise, and the flip-flop 54 is set when the counter 51 counts 11 clocks. When the duty ratio is 50%, the number of clocks in one cycle is, for example, about 13, so that the time when the flip-flop 54 is set as shown in FIGS. The output of the comparator 33 falls at t ₉ , t _11, ..., and a timing signal is supplied to the shift register 58 via the gate circuit 56. If this state continues four times, the AND condition of the AND circuit 59 is satisfied, and the reception inhibition signal is output. Accordingly, in this state, a reception prohibition signal is given from the reception prohibition circuit 40 to the memory control unit 38, and the S / P conversion circuit 61 and the data decode circuit 62
Are always in the reset state. Therefore, when a transmission pulse signal having a duty ratio of 50%, which is the third duty ratio, is erroneously transmitted, the ID comparator 3 is set to the receiving state and the digital comparator 37 makes a logical determination as the first or second duty ratio. Even so, the signal becomes invalid. Then, a data signal is read from the memory control unit 38 based on the clock signal.

FIG. 7D shows an example of a signal in which the signal read from the memory control unit 38 is "HLHL", and this signal is given to the reverberation control pulse generator 41. The reverberation control pulse generator 41 outputs a reverberation control pulse having a predetermined width as shown in FIG. 7 (e) when the comparator 33 falls based on the logical level of this signal. This signal is applied to the FETs 42 and 43 and is interrupted. Thus, in FET42,43 off state, the attenuation signal to the resonant circuit 30 as shown at time t ₉ subsequent etc. FIG. 7 (f) has occurred, at time t ₁₁ after turning on the FET42,43 Since both ends of the resonance circuit 30 are grounded, the ID unit 3
Resonance hardly occurs in the resonance circuit 30 of FIG. Meanwhile signal obtained in the resonant circuit 17 of the write / read control unit 1 is between the oscillator 15 time t ₈ ~t ₉ which is driven, t ₁₀ ~t ₁₁ ...... having constant high amplitude level, it Later time
At t _{9 to} t ₁₀ , t _{11 to} t ₁₂ , low-level reverberation remains according to the reverberation of the resonance circuit 30 of the ID unit 3. Then, as shown in FIG. 7 (h), a reception gate signal is generated from the reception gate signal generation circuit 14 at a fixed period shorter than the period in which the transmission pulse is turned off, and the signal is detected via the analog switch 19 which is closed only during that period. The signal is transmitted to the circuit 20. Immediately before the fall, a sampling signal is applied to the sample and hold circuit 22 as shown in FIG. 7 (k). Therefore, since the output of the sample hold circuit 22 is discriminated from the threshold value by the comparator 23, the comparator 23 writes a signal as shown in FIG. 7 (1), that is, a memory read signal similar to FIG. 7 (d). This is transmitted to the read / write control unit 1 with a delay of the transmission frequency T.

In this embodiment, a counter for counting clocks and a digital comparator are used as data demodulation means of the ID unit 3, and the output of the digital comparator discriminates a binary signal corresponding to the pulse width of the oscillation signal. Various configurations for demodulating the width to a binary signal, such as an integration circuit for integrating a signal obtained by a comparator, and a comparator for discriminating the integration output at a predetermined threshold level, constitute data demodulation means. Is also good.

In this embodiment, a rectifier circuit and a constant voltage circuit are provided in the ID unit 3 to serve as a power supply for the ID unit 3.
The transmission data SD supplied from the control device 4 is further subjected to Manchester encoding so that the average period of the transmission pulse becomes constant, and the signal subjected to Manchester encoding, that is, logic "H"
"HL" for level, "LH" for logical "L"
It is preferable to transmit the transmission data by giving the signal of (1) to the transmission pulse generation circuit 13 as transmission data.
In this case, the data transmission rate is halved compared to the case without Manchester encoding.However, the average value of the driving time of the oscillator 15 does not fluctuate with time, and an oscillation signal having a constant average value is given. 3 can perform data transmission without changing the DC voltage.

Further, in this embodiment, the oscillation signal of the resonance circuit is rectified and smoothed and supplied to each block as power.However, a battery may be provided in the ID unit to supply power to each block from this battery. Needless to say.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an article identification system write / read control unit according to an embodiment of the data communication apparatus of the present invention, FIG. 2 is a block diagram showing the overall configuration thereof, and FIG.
FIG. 4 is a block diagram showing the configuration of the ID unit, FIG. 4 is a block diagram showing the configuration of the reception inhibition circuit and the memory control unit, and FIG. 5 is each unit when data is transmitted from the write / read control unit to the ID unit. The time chart showing the waveform of FIG.
FIG. 7 is a time chart showing the operation of the reception prohibition circuit, and FIG. 7 is a time chart showing the waveforms of various parts when transmitting a signal from the ID unit to the write / read control unit. 1 ... Write / read control unit, 3 ... ID unit, 4
…… Control equipment, L1, L2, L3 …… Coil, 11 …… Clock generator, 12 …… Time controller, 13 …… Transmit pulse generation circuit, 14 …… Reception gate signal generation circuit, 15 …… Oscillator, 17 , 30 …… Resonant circuit, 19 …… Analog switch, 20,
31 ... Detector circuit, 22 ... Sample hold circuit, 23,33
... Comparator, 35 ... Clock discriminating circuit, 36,51 ... Counter, 37 ... Digital comparator, 38 ... Memory control unit, 39 ... Memory, 40 ... Reception inhibition circuit, 41 ... Residual control pulse Generator, 44: Data demodulation means, 45: Reverberation control means, 54: Flip-flop, 58: Shift register

Claims (1)

(57) [Claims] 1. A data communication apparatus for transmitting half-duplex data of serial data between a first unit and a second unit, wherein the first unit is provided on a surface facing the second unit. An oscillator having a first coil provided and oscillating a signal of a constant frequency; and a first and a second corresponding to a transmission data signal during data transmission.
And at the time of data reception, the first and second
Transmission pulse generating means for generating a fixed-period transmission pulse signal having a third duty ratio between the above-mentioned duty ratios, and applying the fixed-period transmission pulse signal to the oscillator to interrupt the oscillation, and the oscillator A first resonance circuit having a resonance frequency substantially equal to the oscillation frequency of the first unit and including a second coil provided on a surface facing the second unit; Receiving gate signal generating means for receiving a received signal and generating a receiving gate signal having a timing when the oscillation of the oscillator is stopped; and providing the first resonance circuit while the receiving gate signal of the receiving gate signal generating means is supplied. A detection circuit for detecting the obtained electromagnetic induction signal; and a sampler for sampling the output of the detection circuit at a predetermined timing of the reception gate signal. And a first comparator for discriminating a hold signal of the sample and hold circuit, wherein the second unit has a resonance substantially equal to an oscillation frequency of an oscillator of the first unit. A second resonance circuit having a frequency and including a third coil provided on a surface facing the first unit, a detection circuit for detecting a signal obtained by the second resonance circuit, and a detection output A second comparator that obtains a transmission pulse signal by discriminating a signal at a predetermined threshold level, and a first and a second duty based on an output of the second comparator when data is received from the first unit. Data demodulation means for demodulating a transmission data signal from a transmission pulse signal having a ratio, and a clock signal obtained from the second resonance circuit while a comparison output obtained from the second comparator is provided. A reception prohibition circuit for invalidating reception data obtained from the data demodulation means when a count value near the third duty ratio is obtained; and a switching connected between the second resonance circuit and ground. A switching element for transmitting the switching element at the timing of stopping the oscillation of the oscillator based on a transmission pulse signal having a third duty ratio obtained from the second comparator at the time of data transmission to the first unit. And a reverberation control means for controlling reverberation vibration generated in the second resonance circuit by being intermittently connected to the data communication apparatus.