JPH08330852A - Mixer circuit - Google Patents

Abstract

PURPOSE: To provide a mixer circuit whose circuit scale is small, which can reduce the voltage of a power source and suppresses an unnecessary wave signal appearing in output resulting from a converted unnecessary wave of a local signal, etc. CONSTITUTION: An unnecessary wave suppression part 20 generating a signal similar to at least the main unnecessary wave signal included in the output 3a of a frequency conversion part 19 is provided in parallel to the frequency conversion part 19. An addition part 23 synthesizing the frequency conversion output 3a and the output 3b of the unnecessary wave suppression part so that the unnecessary wave signal has an amplitude equal to and a phase opposite to the output 3b is provided. Thus, the unnecessary wave signal can be suppressed with the small number of elements even if power voltage is low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mixer circuit, and more particularly to a mixer circuit which receives a local signal and an intermediate frequency signal and obtains a frequency converted signal by frequency conversion, and is particularly included in a frequency converted signal. The present invention relates to a mixer circuit that attenuates unnecessary waves.

[0002]

2. Description of the Related Art As a conventional mixer circuit, a simple mixer circuit composed of a single semiconductor element as shown in FIG. 1 is known. For example, when the single semiconductor element is the dual gate FET 1, the transconductance gm changes depending on the voltage applied to the upper gate 2. ) Property causes multiplication of the signals applied to the gates 2 and 3. Therefore, by inputting the local signal Lo and the intermediate frequency signal IF (hereinafter also abbreviated as IF signal) to the gates 2 and 3, respectively, a predetermined frequency-converted frequency-converted signal RF appears at the output end 4, so that a mixer circuit is formed. It is used. However, dual gate F
Since ET1 does not perform the ideal square operation, this mixer circuit does not perform the ideal multiplication operation, and the local signal L
The o and IF signal components appear at the output 4. The local signal Lo and the IF signal component appearing at the output end 4 are unnecessary waves and are desired to be as small as possible. In addition, in the actual configuration of the mixer circuit, it is unnecessary if the local signal Lo generally has high power in order to increase the conversion gain, and especially when the frequency of the local signal Lo and the frequency of the necessary frequency conversion signal are close. It is difficult to effectively remove waves with matching circuits, filters, etc. Therefore, a technique for effectively suppressing unnecessary waves is often required.

As a mixer circuit capable of effectively suppressing unnecessary waves, there is known a mixer circuit using a so-called Gilbert cell circuit in which a plurality of differential circuits are combined, as shown in FIG. Analysis and De
sign of Analog Integrated Circuits; PRGray and Rob
ert G. Meyer (1984), John Wiley & Sons Inc.). However, the mixer circuit shown in FIG.
11, the matching circuits 13 to 18, the constant current source 12 and the like) are large, and the circuit scale is large. Further, since the transistor has a multi-stage vertically stacked configuration, the power supply voltage cannot be lowered, and the portable communication device As described above, it is not suitable for a circuit device that requires miniaturization and low voltage.

[0004]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a mixer circuit having a small circuit scale, capable of lowering the power supply voltage, and suppressing unnecessary waves such as a local signal appearing on the output side. It is to be.

[0005]

To achieve the above object, a mixer circuit according to the present invention comprises a frequency conversion section for inputting a local signal and an intermediate frequency signal and outputting a frequency converted frequency conversion signal, and the above frequency conversion section. A suppression signal generation unit that generates a suppression signal having the same frequency as an unnecessary frequency component in the generated signal, and an addition unit that adds the frequency conversion signal and the suppression signal in opposite phase and equal amplitude at the output unit of the frequency conversion unit. And a part. As a preferred configuration, the circuits of the frequency conversion unit and the suppression signal generation unit are composed of the same type of elements and circuits, and the impedance of the input / output port of each circuit is made equal.

[0006]

In the mixer circuit of the present invention, the signal of the frequency component to be suppressed in the frequency conversion signal is formed by the circuit provided separately from the frequency conversion unit, and the unnecessary frequency component is canceled by addition to be attenuated. Any unnecessary frequency component can be effectively attenuated. Furthermore, the circuit configuration of the suppression signal generator can be configured by a single active element, or a simple circuit in which a differential amplifier and a single active element are connected in cascade, and a conventionally known Gilbert cell is used. The power supply voltage can be lower than that of the mixer circuit. In particular, among unnecessary signals of the converted frequency-converted signal, a signal component having a frequency equal to that of the local signal or the intermediate frequency signal has a high power level and needs to be removed. However, in the present invention, the suppression signal generator is replaced by the frequency converter. It is composed of the same kind of circuit as the above, and one of the local signal and the IF signal is added to generate a signal of the same frequency as the unnecessary signal included in the output signal of the frequency conversion unit. As a result, the main component of the unnecessary wave frequency signal of the output signal from the frequency conversion unit is effectively removed by adding the unnecessary signal in the opposite phase and equal amplitude state, and the converted frequency signal of the desired frequency is obtained. Obtainable. Further, the bandwidth of the mixer circuit can be widened by balancing the impedance of the input / output ports of each circuit.

[0007]

【Example】

<Embodiment 1> FIG. 3 is a block diagram showing the principle configuration of a first embodiment of the mixer circuit according to the present invention. In this embodiment, the local signal Lo and the intermediate frequency signal IF are input,
A suppression signal having a frequency converter having a mixer 21 for outputting the frequency-converted signal 3a and an amplifier 22 for producing a signal having the same frequency as the unnecessary signal included in the signal 3a and amplifying the signal to generate an unnecessary suppression signal 3b. The generating unit 20 and the adding unit 23 that adds the phases of the unnecessary signal and the unnecessary suppression signal 3b in opposite phases. The output of the adder 23, that is, the output RF of the mixer circuit is a signal obtained by subtracting the unnecessary suppression signal 3b from the frequency-converted signal 3a. Of the unnecessary signals in the frequency-converted signal 3a,
The signal of relatively large power is a leakage signal of the local signal Lo and the intermediate frequency signal IF. Therefore, in order to cancel the leakage of the unwanted wave signal, an amplifier 22 is provided to make the amplitude of the signal equal to the amplitude of the unwanted signal.

<Embodiment 2> FIG. 4 is a block diagram showing the principle configuration of a second embodiment of the mixer circuit according to the present invention. The present embodiment is an effective embodiment particularly when the unnecessary wave is the leaked output of the local signal Lo. The local signal Lo ₊ of the frequency conversion unit and the suppression signal Lo ₋ of the suppression signal generation unit having a phase opposite to that of the local signal Lo ₊ are supplied to the single differential amplifier 2
4 and add them to the mixer 21 and the amplifier 22, respectively, and then combine the respective outputs in the adder 23 to remove the local signal Lo _+, thereby removing the frequency converted signal RF.
Get. The differential amplifier 24 is particularly desirable in that it simplifies the circuit and easily obtains signals of opposite phases.

<Third Embodiment> FIG. 5 is a circuit diagram of a third embodiment of the mixer circuit according to the present invention. In this embodiment, the frequency conversion section and the suppression signal generation section are configured by the same kind of circuit using a dual gate FET as an active element. As shown in the figure, the frequency converter is a dual gate FET 25.
The local signal Lo ₊ and the intermediate frequency signal IF are respectively supplied to the first and second gates of the matching circuit 28 (which includes the inductance element L ₂ and the capacitance element C ₂ ) and (from the inductance elements L ₃ , L ₄ and the capacitance element C _2). ) 29. The source electrode of the dual gate FET 25 is grounded via a bias circuit composed of a resistance element R ₁ and a capacitance element C ₅ . The suppression signal generator is a dual gate F
Each ground potential to the first and second gates of ET26 and local signal Lo ₊ and opposite phase signals local signal Lo _-
Is added via a matching circuit (consisting of a resistance element R ₃ ) 31 and 27 (consisting of an inductance element L ₁ and a capacitance element C ₁ ). The source electrode of the dual gate FET 26 is grounded via a bias circuit including a resistance element R ₂ and a capacitance element C ₆ . The impedance of the port connected to each gate is balanced by a matching circuit. In this embodiment, the portion surrounded by the dotted line is composed of a semiconductor integrated circuit,
Since the matching circuit 29 is externally attached to the outside of the chip, it can be adjusted from the outside when the integrated circuit is mounted. Matching circuit 2
7 to 31 may be formed inside or outside the chip of the integrated circuit depending on its frequency and use. Further, in the embodiment of FIG. 5, the matching circuit 31 is separated from the sources of the two dual gate FETs 25 and 26, and the bias circuits R ₁ , C ₅ : R ₂ and C ₆ are connected to each of them, but the sources are common. You may comprise by one bias circuit. If the two bias circuits are provided independently, the operating points can be aligned even when the threshold voltages Vth of the FETs 25 and 26 vary.

This embodiment is an extremely simple circuit, and since the dual gate FET has one stage in the vertical direction, it can operate at a low voltage, and the local signal Lo on the output side over a wide band.
It has the advantage of being able to remove ₊ (unwanted signal components).

<Fourth Embodiment> FIG. 6 is a circuit diagram showing a mixer circuit according to a fourth embodiment of the present invention. In this embodiment, the frequency converter and the suppression signal generator are single-gate FETs.
It is composed of the same type of circuit using (abbreviated as SGFET). As shown in the figure, the frequency conversion unit includes differential amplifier circuits of SGFETs 32 and 33 whose sources are commonly connected,
SGFET 36 having a drain and a source connected to the common source and the ground of the differential amplifier circuit, and SG
FET32,33 and local signals to the gates of the 36 Lo _+, local signal Lo ₊ and opposite phase signals Lo _- is composed of a circuit applying via and intermediate frequency signal matching the IF circuit 38, 39 and 40.

The suppression signal generator is a differential amplifier circuit of SGFETs 34 and 35 whose sources are commonly connected, an SGFET 37 whose drain and source are respectively connected to the common source and ground, and SGFETs 35, 34 and 37.
Local signal Lo ₊ to the gates of the signal of the local signal Lo ₊ antiphase Lo _- and the ground potential is constituted by a circuit applying via the matching circuit 38, 39 and 42.

The adder is connected to the output terminal of the SGFET 33 and the SGF.
It is configured by connecting the output end of the ET35. SGFE
The local signal in the output signal of T33 and SGFET35
Since the local signals in the output signals of 1 have opposite phases, they cancel each other out.

This embodiment reduces the input power of the local signals Lo ₊ and Lo ₋ necessary for the mixer operation, as compared with the embodiment of FIG. When the impedance of each port is balanced,
The local signal suppression degree on the output side can be increased over a wide band. Since the SGFET has two stages in the vertical direction, low voltage operation is possible as compared with the circuit of the conventional example of FIG. 2 which has three stages including the low current source 12. Further, similar to the embodiment of FIG. 5, the matching circuit 42 of the suppression signal generator is simply matched, and the resistance element and the capacitance element are individually or in combination, or directly grounded to reduce the circuit elements with less characteristic deterioration. It is possible.

<Embodiment 5> FIG. 7 is a circuit diagram showing a fifth embodiment of the mixer circuit according to the present invention. This embodiment is shown in FIG.
This embodiment differs from the embodiment shown in FIG. 2 in that self-bias circuits 43 and 44 are connected between the sources of the SGFETs 36 and 37 and the ground, respectively. The same functions and components are given the same numbers as in FIG. As for the matching circuit 42 between the gate of the SGFET 37 and the ground, similar to the embodiment of FIG. 6, the number of elements can be reduced by simple matching. Further, the self-bias circuits 43 and 44 may be combined into one self-bias circuit.

<Sixth Embodiment> FIG. 8 is a circuit diagram showing a sixth embodiment of the mixer circuit according to the present invention. This embodiment is shown in FIG.
Except for the matching circuit 31 of the embodiment shown in FIG.
The second gate is directly grounded to simplify the circuit configuration. In order to compensate for the imbalance between the mixer and the unwanted wave suppressor caused by this, local matching circuits 27 'and 28' are provided.
Means for individually adjusting the two local signals Lo
₊ And Lo _-The phase difference and the amplitude difference are adjusted. As a result, the number of circuit elements can be reduced without deteriorating the performance. Further, in this embodiment, the DGFETs 26 and 2 are
Although the source of 7 is separated, the source may be shared.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in the above embodiment, the reduction of the leakage of the local signal was mainly described as the signal to be suppressed, but the signal to be suppressed is a neighboring frequency signal which is difficult to remove by a filter or a large amplitude signal which has a great influence on the circuit operation. Is selected and can be similarly applied to unnecessary wave signals such as IF signals and harmonics of local signals. Further, although FETs are used for the active elements of the circuit configuration of the frequency conversion section suppression signal generation section, bipolar transistors or the like may be used.

[0018]

As is apparent from the above description, the mixer circuit of the present invention is connected in parallel with a frequency conversion section such as a single mixer, and a simple circuit for reducing unnecessary waves is connected, and the power supply voltage is low. Unwanted signals can be greatly suppressed even with voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a conventional mixer circuit.

FIG. 2 is a circuit diagram of a conventional mixer circuit.

FIG. 3 is a block diagram showing a first embodiment of a mixer circuit according to the present invention.

FIG. 4 is a block diagram showing a second embodiment of the mixer circuit according to the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the mixer circuit according to the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of the mixer circuit according to the present invention.

FIG. 7 is a circuit diagram showing a fifth embodiment of the mixer circuit according to the present invention.

FIG. 8 is a circuit diagram showing a sixth embodiment of the mixer circuit according to the present invention.

[Explanation of symbols]

19: frequency converter, 20: suppression signal generator, 21: mixer, 22: amplifier, 23: adder, 24: differential amplifier circuit, 25, 26: dual gate FET, 27, 28,
29, 30, 31, 38, 39, 40, 41, 42: matching circuit, 43, 44: self-bias circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H04B 1/26 H04B 1/26 J

Claims (16)

[Claims] 1. Inputting a local signal and an intermediate frequency signal,
A frequency converter that outputs a frequency-converted frequency-converted signal, a suppression signal generator that generates a suppression signal having the same frequency as an unnecessary frequency component to be removed in the frequency-converted signal, the frequency-converted signal, and the suppression A mixer circuit comprising: an adder that adds signals in anti-phase and with equal amplitude. 2. The mixer circuit according to claim 1, wherein a bias circuit of a circuit forming the frequency conversion unit and the suppression signal generation unit is provided independently. 3. The circuit according to claim 1, wherein the circuit forming the suppression signal generating unit is composed of the same type of circuit as the circuit except the circuit for inputting the intermediate frequency signal of the frequency converting unit. Mixer circuit. 4. A circuit excluding a circuit constituting the suppression signal generating section, which receives an intermediate frequency signal having a phase opposite to that of the local signal of the frequency converting section and inputs the intermediate frequency signal of the frequency converting section. The mixer circuit according to claim 1, wherein the mixer circuit is configured by a circuit of the same type as. 5. The circuit constituting the suppression signal generating section is constituted by a circuit which is different only in a matching circuit connected to at least one input terminal of the local signal or the intermediate frequency signal of the frequency converting section. The mixer circuit according to claim 1. 6. The circuit forming the suppression signal generating section is formed of the same type of circuit as the circuit forming the frequency converting section,
2. The matching circuit connected to at least one of the intermediate frequency signal input terminal and the local signal input terminal of the frequency conversion section and the unwanted wave suppression section is provided with means for individually adjusting the matching circuit. Mixer circuit. 7. The first gate, the second gate and the source of the first dual gate FET are respectively a first matching circuit,
A frequency converter connected to the intermediate frequency signal input terminal, the local signal input terminal and the ground via the third matching circuit and the first self-bias circuit, and a second dual gate FET
The first gate, the second gate, and the source of are connected to the ground via the second matching circuit, the fourth matching circuit, and the second self-biasing circuit, respectively, and are connected to the signal input end having the opposite phase to the local signal and the ground. The wave suppressor is commonly connected to the drains of the first and second dual gate FETs, and a fifth
A mixer circuit having an adder connected to the output terminal via the matching circuit of. 8. The first and second dual gate FETs described above.
8. The mixer circuit according to claim 7, wherein at least one of the two is replaced by two single-gate FETs connected in series. 9. The first and second dual gate FETs described above.
9. The mixer circuit according to claim 7, wherein the source and the first and second self-bias circuits are common. 10. The mixer circuit according to claim 7, wherein the sources of the first and second dual gate FETs are grounded instead of the first and second self-bias circuits. 11. The second matching circuit instead of the second matching circuit.
10. The mixer circuit according to claim 7, wherein the gate of the dual-gate FET of 1. is grounded. 12. A first and a second FE whose sources are commonly connected and a third and a fourth FE whose sources are commonly connected.
T, a fifth FET whose drains are connected to the sources of the first and second FETs and whose sources are connected to the first self-bias circuit, and drains of the sources of the third and fourth FETs. And a source connected to the second self-bias circuit, and the first FET
And a first power supply connected to the drain of the third FET,
A fifth matching circuit connected between the drains of the second and third FETs and the output terminal of the frequency conversion signal; and the first matching circuit.
And a gate of the fourth FET are connected to each other, a third matching circuit for applying a local signal to the gates of the first and fourth FETs is connected to the gates of the second and third FETs, and the second matching circuit is connected to the second matching circuit. And a fourth matching circuit that applies a signal having an opposite phase and an equal amplitude to the local signal to the gate of the third FET, a first matching circuit that applies an intermediate frequency signal to the gate of the fifth FET, and the first matching circuit. 6. A mixer circuit having a second matching circuit for adding a second power source signal to the gate of the FET of 6. 13. The fifth and sixth FET sources are commonly connected, and the first and second self-bias circuits are constituted by a single self-bias circuit. The described mixer circuit. 14. The mixer circuit according to claim 12, wherein the sources of the fifth and sixth FETs are grounded instead of the self-bias circuit. 15. The sixth matching circuit instead of the second matching circuit.
14. The mixer circuit according to claim 12 or 13, wherein the gate of the FET of 1. is grounded. 16. A matching circuit according to claim 7, wherein at least one of the first, second, third and fourth matching circuits is constituted by a circuit different from other matching circuits. Mixer circuit.