JPH08330582A - Mosfet and its manufacture - Google Patents

Abstract

PURPOSE: To provide an MOSFET which can suppress short channel effect without increasing overlap capacitance. CONSTITUTION: A gate 14 is formed on a P-type silicon substrate 10 via a gate insulating film 12. Both sides of the gate 14 are provided with a source layer 22 and a drain layer, respectively, via a side wall 20 composed of SiO2 . The side wall 20 consists of a first side wall 16b and a second side wall 18a, where the first side wall 16b is in contact with the gate insulating film 12 and the silicon substrate 10, and in contact with the source layer 18a just above the silicon substrate 10. A second side wall 18a is in contact with the first side wall 16b and overhangs the source layer 22 part which is in contact with the first side wall 16b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET and its manufacturing method, and more particularly to a MOSFET manufacturing method using an elevated source / drain method.

[0002]

2. Description of the Related Art As an example of a conventional MOSFET manufacturing method, a method using an elevated source / drain method is described in a document: "Extended abstract of the 1994 Inte
rnational conference on solid state devices and ma
terials (Yokohama, 1994) pp.482-484 ". In the elevated source / drain method, a side wall is interposed between the gate and the source / drain layer grown on both sides of the gate to form a part of the source / drain region. Therefore, by thickening the source / drain layer, the source / drain resistance can be reduced. Further, according to this method, the short channel effect can be suppressed by diffusing the impurities from the source / drain layers to form the source / drain regions having a shallow junction.

[0003]

By the way, the diffusion length of impurities in the substrate in the horizontal direction is approximately the same as the diffusion length in the vertical direction. Therefore, if the diffusion diffusion layer is made shallow in order to make the source / drain junction depth shallow, the lateral diffusion distance also becomes short. On the other hand, in order for the device to operate, the source / drain region and the channel formed under the gate must be connected. Therefore, in order to reduce the junction depth of the source / drain and realize this connection, it is necessary to reduce the thickness of the sidewall interposed between the gate and the source / drain layer.

For example, when the junction depth is about 40 nm, the lateral diffusion distance is generally 60 to 7 which is the vertical diffusion distance.
Since it is 0%, it is necessary to reduce the thickness of the sidewall to about 20 nm in order to realize the junction with the channel.

However, when the side wall is thinned, the capacitance (overlap capacitance) between the gate and the source / drain increases. As a result, there is a problem that it hinders the high speed operation of the MOSFET.

[0006]

[Means for Solving the Problems]

(First invention) MOSFE of the first invention according to this application
According to T, a gate is provided on a substrate of the first conductivity type via a gate insulating film, and a source layer and a drain layer are provided on both sides of the gate via sidewalls. In the MOSFET in which the region in which the impurities of the second conductivity type are diffused into the substrate is the source region, and the region in which the impurities of the second conductivity type is diffused from this drain layer to the substrate is the drain region, the sidewall is The first side wall and the second side wall are in contact with at least the gate insulating film and the substrate,
Moreover, the second sidewall is in contact with the source layer or the drain layer directly above the substrate, and the second sidewall is in contact with the first sidewall and extends over the source layer portion and the drain layer portion which are in contact with the first sidewall. It is characterized by being provided.

In this MOSFET, the first and second source / drain layers and the diffusion layer are included in the source / drain regions.

In the source / drain layer, one of the two sides of the gate portion serves as the source and the other serves as the drain.

(Second invention) Further, the second invention according to the present application
According to the method of manufacturing a MOSFET of the invention of claim 1, a step of forming a gate portion on a substrate of the first conductivity type via a gate insulating film, and a first step of covering the gate portion and the exposed substrate surface.
A step of forming an insulating film, a step of forming a first sidewall on the side wall of the gate portion by performing a first anisotropic etching on the first insulating film, and a first anisotropic etching Selectively growing a first source / drain layer on the substrate exposed by the step of forming a second insulating film covering the first source / drain layer and the upper side of the gate portion; A step of forming a second sidewall on the sidewall of the first sidewall by performing a second anisotropic etching on the insulating film;
A step of selectively growing the second source / drain layer on the first source / drain layer exposed by the second anisotropic etching and a heat treatment are performed to remove the first source / drain layer from the first source / drain layer to the substrate. And a step of forming a diffusion layer by solid-phase diffusing two conductivity type impurities.

In this MOSFET, the first and second source / drain layers and the diffusion layer are included in the source / drain regions.

In the source / drain layer, one of both sides of the gate portion serves as a source and the other serves as a drain.

(Third Invention) The third invention according to the present application
According to the method of manufacturing a MOSFET of the invention of claim 1, a step of forming a gate portion on a substrate of the first conductivity type via a gate insulating film, and a first step of covering the gate portion and the exposed substrate surface.
An insulating film and a second material made of a material different from that of the first insulating film
The step of sequentially forming the insulating film and the first anisotropic etching of the second insulating film form the second sidewall on the side wall of the gate portion with the first insulating film interposed therebetween. By using the process and the second sidewall as an etching mask, a second anisotropic etching is performed on the first insulating film to form a portion sandwiched between the gate portion and the second sidewall and A step of forming a preliminary first sidewall below the second sidewall, and at least the gate insulating film, the substrate, and the second sidewall are formed by selectively performing isotropic etching on the preliminary first sidewall. The step of forming the first sidewall in contact with the wall and the selective source / drain etching on the substrate exposed by the second anisotropic etching and isotropic etching are performed. Growing an emission layer, by heat treatment, the impurity of this from the source-drain layer to the substrate a second conductivity type; and a step of forming a diffusion layer by solid-phase diffusion.

In this MOSFET, the source / drain layer and the diffusion layer are included in the source / drain region.

In the source / drain layer, one of both sides of the gate portion serves as a source and the other serves as a drain.

[0015]

[Action]

(First invention) MOSFE of the first invention according to this application
According to the structure of T, by providing the elevated source / drain, the source / drain resistance can be reduced as in the conventional case, and further, the short channel effect can be reduced by making the source / drain junction shallow. it can. Further, in the present invention, the sidewall is the first
And the second sidewall, and by reducing the film thickness of the first sidewall, the distance between the gate portion and the source / drain layer immediately above the substrate is shortened, while the second sidewall is used. The distance between the gate portion and the source / drain layer other than the portion directly above the substrate is increased. As a result, the diffusion layer and the channel can be connected without increasing the overlap capacitance. Therefore, M
High-speed operation of the OSFET becomes possible.

(Second and Third Inventions) According to the MOSFET manufacturing method of the second and third inventions of this application, the overlap capacitance is controlled by controlling the thickness of the first sidewall. can do. In addition, by controlling the thickness of the second sidewall, the horizontal distance between the gate portion and the source / drain region on the substrate can be controlled. Then, in these inventions, the thicknesses of the first and second sidewalls can be individually controlled. Therefore, a MOSFET having a very shallow source / drain junction can be realized without increasing the overlap capacitance.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A MOSFET and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.
It should be noted that the drawings to be referred to merely schematically show the sizes, shapes, and positional relationships of the respective constituent components to the extent that these inventions can be understood. Therefore, it is obvious that these inventions are not limited to the illustrated examples. Also,
In each drawing, hatching showing a cross section is partially omitted.

(First Embodiment) In the first embodiment, an example of the structure of the MOSFET of the first invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of an essential part for explaining the MOSFET of the first embodiment, showing a vertical cross section taken along a gate length direction.

According to the MOSFET of the first invention, the gate insulating film 1 having a thickness of 10 nm is formed on the p-type silicon substrate 10.
A gate 14 is provided through 2. This gate 14
Is made of polysilicon and has a gate length of 0.2 μm.

A source layer 22 and a drain layer are provided on both sides of the gate 14 with a sidewall 20 made of SiO ₂ interposed therebetween. The source layer 22 and the drain layer are made of epitaxially grown silicon.

The source layer 22 and the diffusion layer 24 in which n-type impurities are diffused from the source layer to the silicon substrate 10 are used as the source region 26, while the drain layer and the drain layer are n-type to the silicon substrate. The region in which the impurities are diffused is the drain region. In this embodiment, phosphorus (P) is used as the n-type impurity.

Since the source region and the drain region are symmetrical in cross-section with the gate in between, the drain region is not shown in FIG.

In this MOSFET, the side wall 20 is composed of the first side wall 16b and the second side wall 18a.

The first sidewall 16b is in contact with at least the gate insulating film 12 and the silicon substrate 10, and is in contact with the source layer 18a immediately above the silicon substrate 10. The configuration of the drain side is the same as that of the source side.

The second side wall 18a is
It is provided so as to overhang each of the source layers 22 that are in contact with the first sidewalls 20 and are in contact with the first sidewalls 16a.

In this embodiment, the width W ₁ of the first side wall in the lateral direction is set to 20 nm, and the first side wall and the source layer 22 are formed below the projecting portion of the second side wall.
The height H ₁ of a portion (hereinafter, also referred to as an adjacent portion) 22a that contacts with is 30 nm. When the height H ₁ is 30 nm, the resistance value of the adjacent portion 22a becomes smaller than the channel resistance. For example, when the gate length is 0.2 μm, the channel resistance is about 10 kΩ, while the resistance of the adjacent portion 22a is as small as about 1 kΩ. When the height H ₁ is 30 nm, the capacitance (C1) through the first sidewall between the gate portion and the source layer is equal to the capacitance through the gate insulating film between the gate portion and the silicon substrate. Compared with (C0), it is less than 1/10. For example, the gate length is 0.2 μm and the gate insulating film thickness is 10 μm.
In the case of nm, if the thickness of the first sidewall is 40 nm or less, the capacitance of C1 becomes 1/10 or less of the capacitance of C0.

(Second Embodiment) In the second embodiment, an example of a method for manufacturing the MOSFET of the second invention will be described with reference to FIGS. 2A to 2C show the second
FIG. 6 is a sectional process diagram for explaining the embodiment. (A) of FIG.
2C is a cross-sectional process diagram following FIG. 2C. FIGS. 4A and 4B are sectional process drawings following FIG. 3C. Each drawing shows a vertical cross section taken along the gate length direction. Since the source region and the drain region are symmetrical in cross-section across the gate, the drain region is not shown in each drawing.

In the second embodiment, first, the gate 14 made of polysilicon is formed on the p-type silicon substrate 10 via the gate insulating film 12 having a thickness of 10 nm. The gate length of the gate 14 is 0.2 μm ((A) of FIG. 2).

Next, a first insulating film 30 is formed to cover the gate portion 14 and the exposed surface of the substrate 10. In this embodiment, as the first insulating film 30, S having a uniform thickness of 20 nm is used.
An iO ₂ film 30 is formed ((B) of FIG. 2).

Next, the first side wall 30a is formed on the side wall of the gate portion 14 by performing the first anisotropic dry etching on the first insulating film 30. The width (thickness) of this sidewall in the gate length direction is about 2
It becomes 0 nm ((C) of FIG. 2).

Next, the first source / drain layer (hereinafter also referred to as the first epi layer) 32 is selectively grown on the substrate 10 exposed by the first anisotropic etching by selective epitaxial growth. In carrying out the selective epitaxial growth, the substrate temperature is set to 750 in this embodiment.
C., chamber pressure 40 Torr, source gas H ₂ 10 L / min, dichlorosilane 100 cc /
In addition, PH ₂ (diluted to 1000 ppm H ₂ ) as an impurity was supplied to the chamber, and an epitaxial layer having a film thickness of 30 nm was grown under the condition of the film formation rate of 6 nm / min. This first
The impurity concentration of the epi layer is about 3 × 10 ²⁰ atoms / cm ³ . Incidentally, when the first epi layer is grown, the polysilicon layer 34 grows on the gate portion 14 ((A) of FIG. 3).

Next, a second insulating film 36 is formed to cover the first source / drain layer 32 and the upper side of the gate portion 14 (polysilicon layer 14a in this embodiment). In this embodiment, a 200 nm-thick nitride film is formed as the second insulating film (FIG. 3B).

Then, the second side wall 36a is formed on the side wall of the first side wall 30a by performing the second anisotropic etching on the second insulating film 36. The first and second sidewalls 30a and 36a form the sidewall 38 ((C) of FIG. 3).

Next, the second source / drain layer (hereinafter referred to as the second source / drain layer) is selectively formed on the first epi layer 32 exposed by the second anisotropic etching by selective epitaxial growth.
40) is also grown. Second epi layer 34
In this embodiment, the substrate temperature is set to 8
Other than the temperature of 00 ° C., under the same conditions as the growth of the first epi layer
The film is grown to a film thickness of 200 nm at a film forming rate of 30 nm / min. When the thickness of the second epi layer is about 200 nm, the capacitance between the second epi layer and the gate is 1/10 or less of the capacitance via the gate insulating film between the gate portion 14 and the silicon substrate 10. become. The thickness of the second epi layer may be at least about 100 nm in order to make it equal to or less than 1/10.

When the second epi layer is grown, the polysilicon layer 42a is grown on the polysilicon layer 34. The polysilicon layers 42a and 34 and the gate portion 14 function as a gate. In addition, the first and second epi layers 32 and 40 are combined to form a source / drain layer 44 ((A) of FIG. 4).

Next, heat treatment is performed at a temperature of 850 ° C. for 30 minutes to solid-phase diffuse the n-type impurities from the first source / drain layers to the substrate to form a diffusion layer 46 having a thickness of about 40 nm. . The diffusion layer 46 and the first and second epi layers 32 and 40 become the source region 48 ((B) of FIG. 4).

(Third Embodiment) In the third embodiment, an example of a method for manufacturing the MOSFET of the third invention will be described with reference to FIGS. (A) to (C) of FIG.
FIG. 6 is a sectional process diagram for explaining the embodiment. FIG. 6A
5C is a cross-sectional process diagram following FIG. 5C. 7A and 7B are sectional process drawings following FIG. 6C. Each drawing shows a vertical cross section taken along the gate length direction.

In the third embodiment, first, the gate 14 made of polysilicon is formed on the p-type silicon substrate 10 via the gate insulating film 12 having a thickness of 10 nm. The gate length of the gate 14 is 0.2 μm ((A) of FIG. 5).

Next, a first insulating film covering the gate portion 14 and the exposed surface of the silicon substrate 10 and a second insulating film made of a material different from the first insulating film are sequentially formed.
Here, first, the silicon oxide film 1 having a film thickness of about 30 nm is formed.
6 is formed ((B) of FIG. 5).

Next, a film thickness of 20 is formed on the silicon oxide film 16.
A silicon nitride film 18 of about 0 nm is formed ((C) of FIG. 5).

Next, the second insulating film 18 is subjected to the first anisotropic dry etching to form the second side wall 18a on the side wall of the gate portion 14 with the first insulating film 16 interposed therebetween. ((A) of FIG. 6).

Next, the second side wall 18a is used as an etching mask to perform the second anisotropic etching on the first insulating film 16 to form the gate portion 14 and the second side wall 18a. The preliminary first sidewall 16a is formed on the portion sandwiched between the two and the lower side of the second sidewall 18 ((B) of FIG. 6).

Next, this spare first sidewall 16a
By performing isotropic etching selectively with respect to
At least the gate insulating film 12, the silicon substrate 10, and the first sidewall 16b in contact with the second sidewall 18a are formed ((C) of FIG. 6).

Next, on the silicon substrate 10 exposed by the second anisotropic etching and isotropic etching,
A source / drain layer (hereinafter, also referred to as an epi layer) 22 is selectively epitaxially grown using a low pressure CVD method. (In FIG. 7, only the source layer 22 is shown.)
In carrying out the selective epitaxial growth, in this embodiment, the substrate temperature is 750 ° C. and the chamber pressure is 40 Torr.
As a source gas, H ₂ 10 L / min, dichlorosilane 100 cc / min, and impurities PH ₂ (1000 p / min)
pmH ₂ dilution) into the chamber. Then, the film was epitaxially grown to a film thickness of 200 nm under the condition of the film forming rate of 6 nm / min. The impurity concentration of this first epi layer is about 3 ×
It becomes 10 ²⁰ atoms / cm ³ .

When the epi layer is grown, the gate portion 1
A polysilicon layer 14a grows on the surface 4 (FIG. 7A).

Then, a heat treatment is performed at a temperature of 850 ° C. for 30 minutes to diffuse the n-type impurities from the source / drain layer 22 to the silicon substrate 10 in a solid phase to a thickness of 40 n.
A diffusion layer 24 of about m is formed. The diffusion layer 24 and the epi layer 22 become the source region 46 ((B) of FIG. 7).

In this way, the MOSFET having the structure described in the first embodiment is obtained.

By the way, when selectively growing an epitaxial layer on a substrate, so-called facets may occur depending on the growth conditions. For example, as shown in FIG. 11, when a facet is generated in the portion near the gate portion, the overlap capacitance can be reduced without forming the second sidewall. Further, even if facets occur, there is no particular problem in terms of device characteristics. Therefore, it is conceivable to intentionally generate facets to reduce the overlap capacitance and obtain a MOSFET in which a diffusion region having a shallow junction depth is formed. However, when growing an epitaxial layer, it is not always easy to set the conditions for generating facets with good reproducibility.

In this respect, the MOSFE of the invention according to this application
According to the manufacturing method of T, epitaxial growth can be easily performed without considering the occurrence of facets, that is, without being bound by the facet generation conditions.

(Fourth Embodiment) In the fourth embodiment, an example of a method for manufacturing the MOSFET of the third invention will be described with reference to FIGS. FIGS. 8A to 8C are sectional process drawings for explaining the fourth embodiment. 9A to 9C are cross-sectional process diagrams following FIG. 8C. FIGS. 10A and 10B are sectional process drawings following FIG. 9C. Each drawing shows a vertical cross section taken along the gate length direction.

In the fourth embodiment, first, the gate 14 made of polysilicon is formed on the p-type silicon substrate 10 via the gate insulating film 12 having a thickness of 10 nm. The gate length of the gate 14 is 0.2 μm ((A) of FIG. 8).

Next, the first insulating film 50 that covers the gate portion 14 and the exposed surface of the silicon substrate 10 and the first insulating film 50.
A second insulating film 52 made of a material different from that of the insulating film 50 is sequentially formed. Here, first, a silicon nitride film 50 having a film thickness of about 30 nm is formed ((B) of FIG. 8).

Next, a film thickness of 20 is formed on the silicon oxide film 52.
A silicon oxide film 52 of about 0 nm is formed ((C) of FIG. 8).

Next, the second insulating film 52 is subjected to the first anisotropic dry etching to form the second sidewall 52a on the side wall of the gate portion 14 with the first insulating film 50 interposed therebetween. ((A) of FIG. 9).

Next, by using this second side wall 52a as an etching mask, the first insulating film 50 is anisotropically etched a second time to form the gate portion 14 and the second side wall 52a. The preliminary first sidewall 50a is formed on the portion sandwiched between the two and the lower side of the second sidewall 18 ((B) of FIG. 9).

Next, this spare first sidewall 50a
By performing isotropic etching selectively with respect to
At least the gate insulating film 12, the silicon substrate 10, and the first sidewall 16b in contact with the second sidewall 18a are formed ((C) of FIG. 9).

Next, on the silicon substrate 10 exposed by the second anisotropic etching and isotropic etching,
A source / drain layer (hereinafter, also referred to as an epi layer) 22 is selectively epitaxially grown using the UHV-CVD method. (In FIG. 10, only the source layer 22 is illustrated.) In performing selective epitaxial growth, the substrate temperature is 600 ° C. and the pressure in the chamber is 1 × in this embodiment.
10 ^-4 Torr, SiH ₄ 10c as source gas
c / min, PH ₃ as an impurity 1 cc / min (H ₂ dilution, 1
%) Was supplied to the chamber and the film was epitaxially grown to a film thickness of 200 nm under the condition of the film formation rate of 10 nm / min. The impurity concentration of this first epi layer is about 3 × 10 ²⁰ atoms / cm 3.
It becomes ³ .

When the epi layer is grown, the gate portion 1
A polysilicon layer 14a grows on the surface 4 (FIG. 10A).

Next, heat treatment is performed at a temperature of 850 ° C. for 30 minutes to solid-phase diffuse the n-type impurities from the source / drain layer 22 to the silicon substrate 10 to a thickness of 40 n.
A diffusion layer 24 of about m is formed. The diffusion layer 24 and the epi layer 22 become the source region 46 ((B) of FIG. 10).

In each of the above-described embodiments, these inventions have been described only with respect to examples in which a particular material is used and are formed under particular conditions, but these inventions can be subjected to many modifications and variations. For example, in each of the above-described embodiments, the first
Although the conductivity type is p-type and the second conductivity type is n-type, in these inventions, the first conductivity type may be n-type and the second conductivity type may be p-type.

Although the silicon substrate is used as the substrate in each of the above-described embodiments, a silicon substrate may be used in these inventions. For example, a substrate obtained by epitaxially growing SiGe or SiC on the silicon substrate may be used. .

Further, in each of the above-mentioned embodiments, the epitaxial layer of silicon is selectively grown as the source / drain layers, but in these inventions, for example, a polysilicon layer may be selectively grown. Further, as these layers, for example, SiGe may be selectively grown instead of silicon.

Further, in the above-described second to fourth embodiments, anisotropic dry etching is performed as anisotropic etching, but in these inventions, anisotropic wet etching may be performed as anisotropic etching.

Further, in the above-mentioned second to fourth embodiments, impurities are doped when the source / drain layers are selectively epitaxially grown, but in these inventions, the impurities may be ion-implanted after the epitaxial growth. .

Further, in the above-mentioned second to fourth embodiments, the polysilicon layer is grown on the gate portion 14 when the source / drain layers are selectively epitaxially grown, but in these inventions, the polysilicon layer is grown on the gate portion 14. However, it is not always necessary to grow the polysilicon layer.

[0066]

【The invention's effect】

(First invention) MOSFE of the first invention according to this application
According to the structure of T, by providing the elevated source / drain, the source / drain resistance can be reduced as in the conventional case, and further, the short channel effect can be reduced by making the source / drain junction shallow. it can. Further, in the present invention, the sidewall is the first
And the second sidewall, and by reducing the film thickness of the first sidewall, the distance between the gate portion and the source / drain layer immediately above the substrate is shortened, while the second sidewall is used. The distance between the gate portion and the source / drain layer other than the portion directly above the substrate is increased. As a result, the diffusion layer and the channel can be connected without increasing the overlap capacitance. Therefore, M
High-speed operation of the OSFET becomes possible.

(Second and Third Inventions) According to the MOSFET manufacturing methods of the second and third inventions of this application, the overlap capacitance is controlled by controlling the thickness of the first sidewall. can do. In addition, by controlling the thickness of the second sidewall, the horizontal distance between the gate portion and the source / drain region on the substrate can be controlled. Then, in these inventions, the thicknesses of the first and second sidewalls can be individually controlled. Therefore, a MOSFET having a very shallow source / drain junction can be realized without increasing the overlap capacitance.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts for explaining a MOSFET according to a first embodiment.

2A to 2C are MOSFETs of a second embodiment.
FIG. 6 is a cross-sectional process diagram that is used to describe the manufacturing method of FIG.

3A to 3C are sectional process drawings following FIG. 2C.

4A and 4B are cross-sectional process diagrams following FIG. 3C.

5A to 5C are MOSFETs of a third embodiment.
FIG. 6 is a cross-sectional process diagram that is used to describe the manufacturing method of FIG.

6A to 6C are sectional process drawings following FIG. 5C.

7A and 7B are sectional process drawings following FIG. 6C.

FIG. 8A to FIG. 8C are MOSFETs of a fourth embodiment.
FIG. 6 is a cross-sectional process diagram that is used to describe the manufacturing method of FIG.

9A to 9C are sectional process drawings following FIG. 8C.

10A and 10B are sectional process drawings following FIG. 9C.

FIG. 11 is a diagram for explaining facets.

[Explanation of symbols]

 10: Silicon Substrate 12: Gate Insulating Film 14: Gate Part 14a: Polysilicon Layer 16: First Insulating Film 16a: Preliminary First Sidewall 16b: First Sidewall 18: Second Insulating Film 18a: Second Sidewall 20 : Sidewall 22: Source layer 22a: Adjacent part 24: Diffusion layer 26: Source region 30: First insulating film 30a: First sidewall 32: First source / drain layer (first epi layer) 34: Polysilicon layer 36: Second Insulating Film 36a: Second Sidewall 38: Sidewall 40: Second Source / Drain Layer (Second Epi Layer) 42: Polysilicon Layer 44: Source / Drain Layer 46: Diffusion Layer 48: Source Region 50 : First Insulating Film 50a: Preliminary First Sidewall 52: Second Insulating Film 52a: Second Sidewall 54: Sidewall Le 60: insulating layer 62: silicon epitaxial layer

Claims (3)

[Claims] 1. A gate is provided on a substrate of the first conductivity type via a gate insulating film, and a source layer and a drain layer are provided on both sides of the gate via sidewalls. A region in which impurities of the second conductivity type are diffused into the substrate is used as a source region, and the drain layer and the second layer from the drain layer to the substrate.
In a MOSFET in which a region in which a conductivity type impurity is diffused is used as a drain region, the sidewall includes a first sidewall and a second sidewall.
The first sidewall is in contact with at least the gate insulating film and the substrate, and is in contact with the source layer or the drain layer immediately above the substrate, and the second sidewall is A MOSFET provided so as to project from the source layer portion and the drain layer portion which are in contact with the first sidewall and are in contact with the first sidewall. 2. A step of forming a gate portion on a first conductivity type substrate with a gate insulating film interposed therebetween, a step of forming a first insulating film covering the gate portion and the exposed substrate surface, Forming a first side wall on the side wall of the gate portion by performing a first anisotropic etching on one insulating film; and selecting a substrate exposed by the first anisotropic etching. The step of growing the first source / drain layer intentionally, the step of forming a second insulating film covering the first source / drain layer and the upper side of the gate portion, and the second time with respect to the second insulating film. Anisotropic etching is performed to form second sidewalls on the sidewalls of the first sidewalls, and selective etching is performed on the first source / drain layers exposed by the second anisotropic etching. First 2 a step of growing a source / drain layer, and a step of forming a diffusion layer by solid-phase diffusing second conductivity type impurities from the first source / drain layer to the substrate by performing heat treatment. MOSF characterized by
ET manufacturing method. 3. A step of forming a gate portion on a first conductivity type substrate via a gate insulating film, and a first insulating film covering the gate portion and the exposed substrate surface and the first insulating film. A step of sequentially forming a second insulating film made of a material, and a first anisotropic etching of the second insulating film to form a second insulating film on the sidewall of the gate portion through the first insulating film. A step of forming a second sidewall, and a second anisotropic etching is performed on the first insulating film using the second sidewall as an etching mask to thereby form the gate portion and the second sidewall. A step of forming a preliminary first sidewall on a portion sandwiched between and and a lower side of the second sidewall; and by performing isotropic etching selectively on the preliminary first sidewall, Forming a first sidewall in contact with the gate insulating film, the substrate, and the second sidewall; and selectively exposing the substrate exposed by the second anisotropic etching and the isotropic etching. A step of growing a source / drain layer on the substrate, and a step of forming a diffusion layer by solid-phase diffusing the impurities of the second conductivity type from the source / drain layer to the substrate by performing heat treatment. And a method for manufacturing a MOSFET.