JPH08330319A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: To suppress the lateral extension of the region of N type diffusion layer by introducing N type impurities along the side wall of a trench in the following stage and forming an N type diffusion layer, i.e., a collector lead-out region, using the N type impurities introduced to the side wall as a diffusion source. CONSTITUTION: N type impurities are introduced to the side wall of a first trench 4a by thermal diffusion or ion implantation of N type impurities, e.g. phosphorus or arsenic, using first, second and third protective films 21, 22, 23 as a mask and then heat-treatment is performed. An N type diffusion layer 8 is formed over the entire side wall of trench 4a by diffusing impurities from the side wall of the trench. Since the impurities are distributed uniformly in the direction of depth of N type diffusion layer 8, electrical resistance of the N type diffusion layer 8, i.e., the collector lead-out region, can be substantially halved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a bipolar transistor having semiconductor trench element isolation.

[0002]

2. Description of the Related Art Miniaturization and high densification of semiconductor elements are still being vigorously pursued, and a semiconductor device using a CMOS transistor which is an insulated gate field effect transistor is designed to have a size of about 0.2 μm. Highly integrated semiconductor devices have been developed and prototyped. Furthermore, in recent years, ultra-high speed operation of semiconductor devices has also been required at the same time. In response to this demand, along with the miniaturization of the above-mentioned CMOS semiconductor element, bipolar transistor and CM
The development of a BiCMOS semiconductor device whose circuit is composed of an OS transistor has become important.

As a structure of a bipolar transistor which constitutes such a BiCMOS semiconductor device, there is a promising method of forming a trench structure in an element isolation region for electrically insulating and isolating semiconductor elements for miniaturization as described above. To be seen. A conventional method of manufacturing a bipolar transistor using such trench isolation will be described with reference to FIG. FIG. 6 is a sectional view of such a bipolar transistor in the order of manufacturing steps.

As shown in FIG. 6A, an N ⁺ buried layer 102 is formed on the surface of a silicon semiconductor substrate 101 having a P conductivity type. Next, an N ⁻ type epitaxial layer 103 is formed on this N ⁺ buried layer 102. A trench 104 is formed on a predetermined region of the semiconductor substrate by dry etching.
Is formed. Then, P is formed on the bottom of the trench 104.
A mold channel stopper region 105 is provided.

Next, the first sidewall is formed on the sidewall of the trench 104.
And the second insulating film 107 is formed.
Is filled. In this way, the trench element isolation region 104 'in which the insulating film is buried in the trench is formed in a predetermined region. Then, the first interlayer insulating film 108 covering the N ⁻ type epitaxial layer 103 and the trench element isolation region 104 ′ is deposited.

Next, as shown in FIG. 6B, a contact hole is formed in a predetermined region of the first interlayer insulating film 108 near the trench element isolation region 104 ', and the first N-type polysilicon 109 is formed. Is provided. Here, phosphorus impurities are introduced into the N-type polysilicon 109. Then, heat treatment is applied to form the N-type diffusion layer 110 reaching the aforementioned N ⁺ buried layer 102 region. Thus, N
The type diffusion layer 110 is formed of the first N-type polysilicon 10 described above.
9 is formed by thermal diffusion using 9 as a diffusion source of phosphorus impurities.

Next, as shown in FIG. 6C, the base, emitter, and collector regions of the bipolar transistor are formed in the island-shaped regions separated by the trench element isolation regions 104 '. That is, the P-type base diffusion layer 111 is formed, and the N ⁺ -type emitter diffusion layer 112 is provided in the P-type base diffusion layer 111. Here, the N ⁺ type emitter diffusion layer 112 is formed by thermal diffusion of arsenic impurities contained in the second N type polysilicon 113. Then, the second interlayer insulating film 114 is formed between the first N-type polysilicon 109 and the second N-type polysilicon 113 described above.

Next, a third interlayer insulating film 115 is formed, contact holes are formed in the first interlayer insulating film 108, the second interlayer insulating film 114 and the third interlayer insulating film 115, and P is formed. Type base electrode 1 connected to the base diffusion layer
16 are provided. Then, the emitter electrode 117 connected to the second polysilicon 113 is formed through the contact hole formed in the third interlayer insulating film 115 on the second polysilicon 113. Similarly, the second interlayer insulating film 10 on the first N-type polysilicon 109 is formed.
8 and the contact hole formed in the second interlayer insulating film 114, the collector electrode 118 connected to the first polysilicon 109 is formed.

As described above, the silicon semiconductor substrate 1
01 has an N ⁺ buried layer 102, an N ⁻ type epitaxial layer 103 formed on top of it has a trench element isolation region 104 ′, and a trench existing in the N ⁻ type epitaxial layer 103 described above. N-type diffusion layer 110 reaching the N ⁺ buried layer 102 along the sidewall of the element isolation region 104 '.
Is formed. Then, this N-type diffusion layer 110 becomes a collector extraction region, and the first N-type polysilicon 109 is formed.
Is connected to the collector electrode 118 via. Then, as described above, the base region or the emitter region is formed to form the bipolar transistor having the trench element isolation region.

[0010]

As described above, in the conventional method for forming the bipolar transistor having the trench element isolation region, the N ⁺ buried layer 102 and the collector electrode 118 are electrically connected with low resistance as described above. N-type diffusion layer 1
10 or the collector extraction region is generally formed by thermal diffusion of N-type impurities from the surface of the N ⁻ -type epitaxial layer 103. In the above-mentioned conventional technique, the case where the first N-type polysilicon 109 containing phosphorus impurities serves as a diffusion source and the N-type diffusion layer 110 is formed has been described.

However, in such a method of forming the N-type diffusion layer 110, since the impurity diffusion is isotropic, the region of the N-type diffusion layer extends laterally. Therefore, it becomes difficult to reduce the lateral dimension of the semiconductor element.

[0012] In addition, the impurity diffusion source as previously described is N ^-
Since it is formed on the surface of the type epitaxial layer 103, the impurity concentration has a distribution in the depth direction. Then, the amount of impurities decreases as it approaches the N ⁺ buried layer 102. Therefore, it is difficult to reduce the electric resistance of the N-type diffusion layer 110, that is, the collector extraction region.

Here, in order to reduce the electric resistance of the N-type diffusion layer 110, if the diffusion temperature of phosphorus impurities or the like is raised to 1000 ° C. or higher or the diffusion time is lengthened, the region of the N-type diffusion layer 110 will be formed. Crystal defects such as dislocations will occur. Further, the impurities in the N ⁺ buried layer 102 are re-diffused, the withstand voltage between the collector and the base deteriorates, and the characteristics of the bipolar transistor also deteriorate.

The above problems become more remarkable as the thickness of the N ^-- type epitaxial layer 103 increases. In the BiCMOS semiconductor device described above, the film thickness of the N ⁻ type epitaxial layer 103 is set to be thicker than in the case of a high-speed semiconductor device including only bipolar transistors. Therefore, in such a BiCMOS semiconductor device, the above-mentioned problem is an important problem to be solved.

An object of the present invention is to solve the above problems and facilitate miniaturization, high density, and high speed of a semiconductor device such as BiCMOS.

[0016]

To this end, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a buried layer of opposite conductivity type in a region of a predetermined depth of a semiconductor substrate of one conductivity type, A step of forming an element active region of opposite conductivity type in a region reaching from the main surface of the semiconductor substrate to the buried layer; and a step of forming a first groove in a predetermined region of the element active region. A semiconductor region containing a high concentration impurity of opposite conductivity type, which reaches the buried layer from the main surface of the element active region by introducing an impurity of opposite conductivity type along the sidewall of the first groove. Including the process.

Further, after the formation of the first groove and the introduction of the impurity of the opposite conductivity type are performed using the same protective film as a mask, the protective film is again used as a mask to form the first groove. Dry etching is added to form a second groove penetrating the buried layer; and an impurity of one conductivity type is ion-implanted into the bottom of the second groove using the protective film as a mask. And a step of embedding an embedding material containing an insulator in the second groove.

Here, the buried layer is formed by high-energy ion implantation from the surface of the semiconductor substrate and heat treatment of the ion-implanted layer formed by the ion implantation.

Then, a bipolar transistor or an insulated gate field effect transistor is formed in the device active region.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the drawings. FIG. 1 is a plan view and a sectional view of a bipolar transistor formed by the method of the present invention. Here, FIG.
FIG. 1 shows a section taken along the line AB in the plan view of FIG.
It is a sectional view of (b). In order to avoid complication of the drawing, the emitter electrode, the base electrode, and the collector electrode are not shown in the plan view of FIG.

As shown in FIGS. 1A and 1B, an N ⁺ buried layer 2 is formed on the P type silicon substrate 1, and an N type buried layer 2 is formed on the N ⁺ buried layer 2. The silicon layer 3 is formed. Then, the trench 4 is the N-type silicon layer 3,
It is formed so as to extend to N ⁺ buried layer 2 and P type silicon substrate 1. Then, at the bottom of the trench 4, P
A mold channel stopper region 5 is provided.

Next, as described in the prior art,
A first insulating film 6 is formed on the side wall of the trench 4 and further filled with a second insulating film 7. In this way, the trench element isolation region 4'with the insulating film buried in the trench 4 is formed in a predetermined region. Here, as shown in FIG. 1A, the trench element isolation region 4'is formed so as to completely surround the semiconductor element. Further, as shown in FIG. 1B, the N type diffusion layer 8 is formed along both sides of the sidewall of the trench 4 described above. Then, the first N-type polysilicon 9 is formed on the N-type diffusion layer 8.

Next, as shown in FIG. 1A or FIG. 1B, the base, emitter and collector regions of the bipolar transistor are formed in the region surrounded by the trench element isolation region 4 '. That is, the P-type base diffusion layer 10 is formed, and the N ⁺ -type emitter diffusion layer 11 is provided in the P-type base diffusion layer 10. Here, the N ⁺ type emitter diffusion layer 11 is formed by thermal diffusion of arsenic impurities contained in the second N type polysilicon 12. Here, the first N-type polysilicon 9 and the second N-type polysilicon 12 described above are formed by patterning the same polysilicon film. The first N-type polysilicon 9 is electrically connected to the N-type diffusion layer 8 through the collector contact 14 formed in the first interlayer insulating film 13. The collector contact 14 can be formed in a U shape as shown in FIG.

Next, a second interlayer insulating film 15 is formed,
A base contact 16 is formed on the first interlayer insulating film 13 and the second interlayer insulating film 15, and a base electrode 17 connected to the P-type base diffusion layer is provided. Then, the emitter electrode 18 is formed through the contact hole provided in the second interlayer insulating film 15 on the second type polysilicon 12 described above. Similarly, collector electrode 19 is formed through a contact hole formed in second interlayer insulating film 15 on first N-type polysilicon 9.

Next, a method of manufacturing a bipolar transistor having such an N-type diffusion layer 8, that is, a collector extraction region, will be described as a first embodiment in the order of steps thereof with reference to FIGS. Here, the same components as those shown in FIG. 1 are designated by the same reference numerals.

First, phosphorus ions of monovalent or divalent ions are ion-implanted from the surface of the P-type silicon substrate 1 at an acceleration energy of about 1 to 2 Mev. Here, the dose amount of ions is set to 5 × 10 ¹³ to 1 × 10 ¹⁴ ions / cm ² . Subsequently, the acceleration energy is 100 keV
The phosphorus is ion-implanted again under the condition that the dose amount is about 10 ¹¹ ions / cm ² . After doing this,
Heat treatment is applied.

In this way, as shown in FIG.
The depth from the surface of the P-type silicon substrate 1 is 1 to 2.5 μm.
The N ⁺ buried layer 2 is formed in a certain region. Further, the N-type silicon layer 3 is formed on the surface of the P-type silicon substrate 1.

Next, the film thickness 2 is formed on the surface of the N-type silicon layer 3.
The first protective film 21 is formed of a silicon thermal oxide film having a thickness of about 0 nm. Then, a polysilicon film is formed on the first protective film 21 by a chemical vapor deposition (CVD) method, and a second protective film 22 having a film thickness of about 150 nm is formed. Furthermore, a film thickness of 300 n is formed on the second protective film 22.
A silicon oxide film of about m is deposited by the CVD method to form a third protective film.

Next, using a photoresist formed by a known photo-etching method as a mask, a predetermined region of the above-mentioned protective film is selectively etched, and as shown in FIG. 2 (b).
The first trench 4a is formed by dry etching.
Here, the depth of the first trench 4a is 1.5 to 2 μm.
It is about m and is formed so as not to penetrate the above-mentioned N ⁺ buried layer 2.

Next, the above-mentioned protective film and the first trench 4a.
The photoresist used as the dry etching mask is removed. After doing so, the above-mentioned first protective film 2 is formed.
Using the first, second protective film 22 and the third protective film 24 as a mask, N-type impurities are introduced into the sidewalls of the first trench 4a by thermal diffusion or ion implantation of N-type impurities such as phosphorus or arsenic. And further heat-treated. Thus, as shown in FIG. 2B, the N-type diffusion layer 8 is formed along the side wall of the first rotary wrench 4a. Here, the lateral width of such an N-type diffusion layer 8 is 0.5.
It is set to about μm.

Next, the first protective film 21 and the second protective film 2
2 and the third protective film 23 of the N ⁺ buried layer 2 through the addition of dry etching using a mask N ⁺ still about 1μm than buried layer 2 deep trench 4 is formed. Here, the etching ratio between the silicon substrate and the silicon oxide film is 2
The dry etching gas is selected so as to be about zero. Here, this dry etching gas is C
It is a mixed gas of l ₂ and HBr. Subsequently, the above-mentioned first
Protective film 21, second protective film 22 and third protective film 2
Using 3 as a mask for ion implantation, boron ion implantation is performed and heat treatment is performed. The ion implantation angle at this time is 0 °
And the implantation energy is set to about 20 keV. In this way, the P-type channel stopper region 5 is formed as shown in FIG.

Next, the structure shown in FIG. 3A is formed as follows. That is, a silicon oxide film having a film thickness of about 100 nm is formed by thermal oxidation. Alternatively, a silicon nitride film having a film thickness of about 150 nm is deposited on the silicon oxide film by a CVD method.
In this way, the first insulating film 6 is formed on the sidewall of the trench 4. Next, a BPSG film (a silicon oxide film containing boron glass and phosphorus glass) is deposited by the CVD method and buried in the trench 4 by reflow by heat treatment. Then, the BP remaining on the upper side by the chemical mechanical polishing (CMP) method.
The SG film and the third protective film 23 are removed and planarized. Here, the above-mentioned second protective film 22 is a polysilicon film and has a role as an etching stopper for CMP. In this way, the second insulating film 7 made of the BPSG film is filled in the trench together with the above-described first insulating film 6.

Next, the second protective film 22 and the first protective film 21 left on the surface are sequentially removed by wet etching. Here, the second protective film 22 is removed with a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid, and the first protective film 21 is removed with a dilute hydrofluoric acid solution in a short time. Under such wet etching conditions, the first insulating film 6 and the second insulating film 7 filling the trench 4 are hardly etched.

Next, the first interlayer insulating film 13 covering the N-type silicon layer 3 and the trench element isolation region 4'is CV.
It is formed of a silicon oxide film by the D method, and a structure as shown in FIG. 3A is completed. Here, the film thickness of the first interlayer insulating film 13 is set to about 20 nm.

Next, as shown in FIG. 3B, the first polysilicon 9 is formed so as to be electrically connected to the N type diffusion layer 8, and the P type base diffusion layer 10 is formed. An N ⁺ type emitter diffusion layer 11 is formed in the base diffusion layer 10. Here, the N ⁺ type emitter diffusion layer 11 is formed by thermal diffusion of arsenic impurities contained in the second polysilicon 12.

After this, the bipolar transistor suitable for miniaturization is completed which has the base element, the emitter electrode and the collector electrode shown in FIG. 1B and has the trench element isolation region.

In the method of the present invention, the N type diffusion layer 8 is formed by diffusing impurities from the side wall of the first trench 4a and is formed over the entire side wall of the trench. For this reason, the impurity distribution in the depth direction of the N-type diffusion layer 8 becomes uniform, and the electric resistance of the N-type diffusion layer 8, that is, the collector extraction region can be reduced to about half that of the conventional technique. become.

Next, the second embodiment of the present invention will be described with reference to FIGS. 4 and 5.
An example will be described. 4 and 5 are cross-sectional views in order of steps of another manufacturing method of the present invention. Here, the same components as those shown in FIG. 1 are designated by the same reference numerals.

First, the surface of the P-type silicon substrate 1 has an acceleration energy of 100 keV and a dose of 10 ¹¹ ions /
Phosphorus is ion-implanted under the condition of about cm ² . After this, heat treatment is performed to form the N-type silicon layer 3 on the surface of the P-type silicon substrate 1 as shown in FIG.

Next, similarly to the first embodiment, the first protective film 2 having a film thickness of about 20 nm is formed on the surface of the N-type silicon layer 3.
1 is formed. Then, a polysilicon film is formed by stacking on the first protective film 21, and a second protective film 22 having a film thickness of about 150 nm is formed. Further, a third protective film having a film thickness of about 300 nm is formed on the second protective film 22.

Next, as shown in FIG. 4A, a predetermined region of the above-mentioned protective film is selectively etched by a known photo-etching method, and the first trench 4a is formed by dry etching. . Here, the depth of the first trench 4a is 2
It is set to about μm.

Next, the photoresist used as the mask for these dry etchings is removed. After this, N-type impurities are removed by thermal diffusion or ion implantation of N-type impurities such as phosphorus or arsenic using the first protective film 21, the second protective film 22 and the third protective film 23 as a mask. It is introduced into the sidewall of the above-mentioned first trench 4a. Further heat treatment is performed, and as shown in FIG. 4B, the N-type diffusion layer 8 is formed.
Will be formed along the side wall of the first trench 4a. Here, the lateral width of the N-type diffusion layer 8 is set to about 0.5 μm.

Next, as shown in FIG. 4C, a depth of about 4 μm is obtained by additional dry etching using the first protective film 21, the second protective film 22 and the third protective film 23 as a mask. Trench 4 is formed. Subsequently, boron ion implantation is performed using the first protective film 21, the second protective film 22, and the third protective film 23 described above as masks for ion implantation. The ion implantation angle at this time is 0 °, and the implantation energy is set to about 20 keV. In this way, the P-type channel stopper region 5 is formed as shown in FIG.

Next, as shown in FIG. 5A, a silicon oxide film having a film thickness of about 200 nm is formed by thermal oxidation. In this way, the first insulating film 6 is formed on the sidewall of the trench 4. Then, in the same manner as described in the first embodiment, the BPSG film is embedded in the trench 4, and the second insulating film 7 made of the BPSG film is formed in the trench.
It will be filled together with the above-mentioned first insulating film 6.

Next, the second protective film 22 and the first protective film 21 left on the surface are sequentially removed by wet etching, and the N-type silicon layer 3 and the trench element isolation region 4 '.
To form a first interlayer insulating film 13. Here, the film thickness of the first interlayer insulating film 13 is set to about 20 nm.

Next, monovalent or divalent phosphorus ions are ion-implanted from the surface of the first interlayer insulating film 13 at an acceleration energy of about 1 to 2 Mev. Here, the dose amount of ions is set to 5 × 10 ¹³ to 1 × 10 ¹⁴ ions / cm ² . After this, heat treatment is performed, and as shown in FIG.
As shown in (b), the N ⁺ buried layer 2 is formed in a region having a depth of about 2 to 3 μm from the surface of the N-type silicon layer 3.

At the same time as this step, phosphorus impurities are introduced also into the first insulating film 6 and the second insulating film 7 filling the trench 4. However, the amount of phosphorus impurities introduced into the first insulating film 6 or the second insulating film 7 is about 10 ¹⁸ atoms / cm ³ , and the amount of phosphorus impurities contained in the second insulating film 7 is 10 ¹⁸ atoms / cm ^{3. The} amount is very small compared to ²¹ atoms / cm ³ . Therefore, the phosphorus impurities introduced in this way are
The insulating properties of the insulating film 6 and the second insulating film 7 are not deteriorated. Further, since the conductivity type of the region of the silicon substrate in contact with these insulating films is N type, even if the introduced phosphorus impurities are thermally diffused again, such impurities have no influence on the semiconductor element. Not.

In this way, the same structure as that of FIG. 3A described in the first embodiment is completed. After that, the bipolar transistor is formed through the same steps as described in the first embodiment.

In this second embodiment, the N ⁺ buried layer 2 is formed in a later step than that in the first embodiment. And
The number of heat treatment steps after the introduction of phosphorus impurities into the N ⁺ buried layer 2 is reduced. Therefore, it becomes easy to control the depth of the N ⁺ buried layer 2 to be shallow, and the depth of the trench 4 can be set to be shallow.

In the above embodiments, the case where the insulating film is buried in the trench has been described, but it should be noted that the same effect can be obtained when the polysilicon film is buried. Further, although the case where the N-type silicon layer is formed by ion implantation into the silicon substrate is described, it should be noted that this layer may be formed by the silicon epitaxial layer described in the conventional technique. .

In the case of forming a CMOS transistor constituting BiCMOS, the n-channel and p-channel MOS transistors are formed by a known method in the island-shaped N-type silicon layer region separated by the trench element isolation region described above. Is formed by.

[0052]

As described above, according to the present invention, in forming a bipolar transistor having a trench element isolation region, a trench is formed through a two-step process,
N-type impurities are introduced along the sidewall of the trench formed after one step. Then, the N-type impurity of the side wall thus introduced is used as a diffusion source to form an N-type diffusion layer, that is, a collector extraction region.

Due to such a method, the lateral expansion of the region of the N-type diffusion layer, which is seen in the above-mentioned conventional technique, is suppressed, and the lateral dimension of the semiconductor element can be easily miniaturized.

Further, arsenic impurities having a small diffusion coefficient can be used as the N-type impurities, and the amount of impurities can be increased more than in the case of phosphorus, so that the electric resistance of the N-type diffusion layer, that is, the collector extraction region is significantly reduced. In this case, the lateral expansion of the region of the N-type diffusion layer described above is further reduced.

Furthermore, since the P-type channel stopper region is formed after the N-type diffusion layer is formed, the expansion of the P-type channel stopper region in the thermal diffusion process of forming the N-type diffusion layer, which has been found in the conventional technique, is prevented. To be prevented. Therefore, the required trench depth can be set shallow. Alternatively, since the separation distance between the N ⁺ buried layer and the P-type channel stopper region becomes long, it is possible to improve the junction breakdown voltage between the collector region and the silicon substrate and reduce the parasitic capacitance.

As described above, according to the present invention, even in a BiCMOS semiconductor device in which an active region in which a semiconductor element is formed, that is, an N-type silicon layer is thick, it can be miniaturized with high precision and stably formed.

[Brief description of drawings]

FIG. 1 is a structural diagram of a semiconductor device formed by the method of the present invention.

2A to 2D are cross-sectional views in order of processes for explaining the first embodiment of the present invention.

FIG. 3 is a cross-sectional view in process order for explaining a first embodiment of the present invention.

FIG. 4 is a cross-sectional view in process order for explaining a second embodiment of the present invention.

5A to 5D are cross-sectional views in order of the steps, for explaining the second embodiment of the present invention.

6A to 6C are cross-sectional views in order of processes for explaining a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2,102 N ⁺ burying layer 3 N-type silicon layer 4,104 Trench 4a 1st trench 4 ', 104' Trench element isolation area 5,105 P-type channel stopper area 6,106 1st Insulating film 7,107 Second insulating film 8,110 N-type diffusion layer (collector extraction region) 9,109 First N-type polysilicon 10,111 P-type base diffusion layer 11,112 N ⁺ -type emitter diffusion layer 12 , 113 second N-type polysilicon 13, 108 first interlayer insulating film 14 collector contact 15, 114 second interlayer insulating film 16 base contact 17, 116 base electrode 18, 117 emitter electrode 19, 118 collector electrode 21 1 of the protective layer 22 and the second protective layer 23 third protective film 101 a silicon semiconductor substrate 103 N ^- -type epitaxial Layer 115 third interlayer insulating film

Claims (4)

[Claims] 1. A step of forming a buried layer of reverse conductivity type in a region of a predetermined depth of a semiconductor substrate of one conductivity type, and a reverse conductivity in a region from the main surface of the semiconductor substrate to the buried layer. Forming a first element active region, and forming a first groove in a predetermined region of the element active region and introducing an impurity of opposite conductivity type along a sidewall of the first groove to form a device active region of the element active region. Forming a semiconductor region containing a high-concentration impurity of opposite conductivity type from the main surface to the buried layer along the side wall of the first groove. 2. The formation of the first groove and the introduction of the impurity of the opposite conductivity type are performed using the same protective film as a mask, and then the protective film is used as a mask again to form the first groove. Dry etching is added to form a second groove penetrating the buried layer; and an impurity of one conductivity type is ion-implanted into the bottom of the second groove using the protective film as a mask. The method of manufacturing a semiconductor device according to claim 1, further comprising a step and a step of burying an embedding material containing an insulator in the second groove. 3. The semiconductor device according to claim 1, wherein the buried layer is formed by high-energy ion implantation from the surface of the semiconductor substrate and heat treatment of the ion-implanted layer. Manufacturing method. 4. The method of manufacturing a semiconductor device according to claim 1, wherein a bipolar transistor or an insulated gate field effect transistor is formed in the element active region.