JPH08330295A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH08330295A JPH08330295A JP11807795A JP11807795A JPH08330295A JP H08330295 A JPH08330295 A JP H08330295A JP 11807795 A JP11807795 A JP 11807795A JP 11807795 A JP11807795 A JP 11807795A JP H08330295 A JPH08330295 A JP H08330295A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- liquid resin
- electrode substrate
- film thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Formation Of Insulating Films (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、樹脂モールドされた
半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a resin-molded semiconductor device.
【０００２】[0002]
【従来の技術】図６は従来の半導体装置の樹脂封止（モ
ールド）前の平面図を示す。ＩＧＢＴのような制御電極
を有する半導体装置で説明する。コレクタ端子となる電
極基板３１に半導体チップ１を半田付けし、ゲート部を
リード線７１でゲート端子となる電極体３２に接続し、
エミッタ部をリード線７２でエミッタ端子となる電極体
３３に接続する。半導体チップ１の周縁部は酸化膜で被
覆されたパッシベーション部２となっている。半導体チ
ップ１上と電極基板３１上に、絶縁性を確保するために
樹脂膜４が被覆されている。図の点線内にある半導体チ
ップと電極基板３１、電極体３２、３３はモールド樹脂
５で封止される。同図において、説明し易いように半導
体チップ１上に被覆している樹脂膜４は省略されてい
る。実際は半導体チップ１上にも樹脂膜４は被覆されて
いる。2. Description of the Related Art FIG. 6 is a plan view of a conventional semiconductor device before resin sealing (molding). A semiconductor device having a control electrode such as an IGBT will be described. The semiconductor chip 1 is soldered to the electrode substrate 31 serving as the collector terminal, and the gate portion is connected to the electrode body 32 serving as the gate terminal with the lead wire 71.
The emitter portion is connected by a lead wire 72 to the electrode body 33 serving as an emitter terminal. The peripheral portion of the semiconductor chip 1 is a passivation portion 2 covered with an oxide film. A resin film 4 is coated on the semiconductor chip 1 and the electrode substrate 31 in order to ensure insulation. The semiconductor chip, the electrode substrate 31, and the electrode bodies 32 and 33 within the dotted line in the figure are sealed with the mold resin 5. In the figure, the resin film 4 covering the semiconductor chip 1 is omitted for ease of explanation. Actually, the resin film 4 is also coated on the semiconductor chip 1.
【０００３】図７は樹脂膜を形成する方法の図を示す。
半導体チップ１を電極基板３１に半田付けし、リード線
７１、７２を配線した後で、ディスペンサ８で液状樹脂
６を半導体チップ１上に滴下し、液状樹脂６で半導体チ
ップが覆われた状態を示す。FIG. 7 shows a diagram of a method for forming a resin film.
After the semiconductor chip 1 is soldered to the electrode substrate 31 and the lead wires 71 and 72 are wired, the liquid resin 6 is dropped on the semiconductor chip 1 by the dispenser 8 so that the semiconductor chip is covered with the liquid resin 6. Show.
【０００４】[0004]
【発明が解決しようとする課題】この方法では、半導体
チップ上で液状樹脂６は重力により拡がる。このとき、
半導体チップの周縁部にあるパッシベーション部は極端
に膜厚は薄く、半導体チップ中心部や半導体チップ端近
傍の金属基板上の膜厚は厚くなる。このように半導体チ
ップ１のパッシベーション部２で極端に薄くなると電気
的な絶縁性および外部からのストレスを受け易くなる。
またこのパッシベーション部２の膜厚を十分確保しよう
とすると、過量な液状樹脂６を半導体チップ１上に滴下
することになり、半導体チップ上の中心部や半導体チッ
プ端近傍の金属基板上で膜厚が極端に厚くなり、液状樹
脂６が熱硬化する時の硬化応力で半導体チップ１に熱ス
トレスが加わり、パッシベーション部２での耐圧の確保
が困難になったり、オン電圧やスイッチング時間などの
電気的特性が劣化する。また極端に熱ストレスが加えら
れると半導体チップ１が割れることもあり得る。In this method, the liquid resin 6 spreads on the semiconductor chip due to gravity. At this time,
The film thickness of the passivation portion in the peripheral portion of the semiconductor chip is extremely thin, and the film thickness on the metal substrate near the center of the semiconductor chip and the edge of the semiconductor chip is large. If the passivation portion 2 of the semiconductor chip 1 is extremely thin in this way, it becomes easier to receive electrical insulation and external stress.
Further, if an attempt is made to secure a sufficient film thickness of the passivation portion 2, an excessive amount of the liquid resin 6 is dropped on the semiconductor chip 1, and the film thickness is formed on the metal substrate near the center of the semiconductor chip and the edge of the semiconductor chip. Becomes extremely thick, and the semiconductor chip 1 is subjected to thermal stress due to the curing stress when the liquid resin 6 is thermally cured, which makes it difficult to secure the withstand voltage in the passivation part 2, and the electrical voltage such as on-voltage and switching time. The characteristics deteriorate. Further, the semiconductor chip 1 may be cracked when heat stress is extremely applied.
【０００５】この発明は、前記課題を解決するために、
液状樹脂の中に半導体チップを浸漬する方法で、液状樹
脂を均一に被着させ、その後の熱硬化でも異常な熱スト
レスが半導体チップに加わらないようにした半導体装置
の製造方法を提供することを目的とする。In order to solve the above problems, the present invention provides
To provide a method of manufacturing a semiconductor device in which a semiconductor chip is immersed in a liquid resin, the liquid resin is uniformly applied, and abnormal thermal stress is not applied to the semiconductor chip even after subsequent thermal curing. To aim.
【０００６】[0006]
【課題を解決するための手段】この発明は前記の目的を
達成するために、半導体チップと電極基板を固着し、半
導体チップの表面を絶縁膜で被覆し、さらに半導体チッ
プと電極基板とが樹脂封止される半導体装置の製造方法
において、液状の樹脂に半導体チップおよび電極基板を
浸漬する工程と、半導体チップおよび電極基板に被着し
た液状の樹脂を熱硬化させる工程により、半導体チップ
と電極基板との表面が前記絶縁膜で被覆されるようにす
る。この絶縁膜の材質がポリイミドの液状の樹脂で、こ
の液状の樹脂の粘度が１０ｃｐｓから５０ｃｐｓである
と効果的である。また封止樹脂の材質がエポキシ樹脂で
あるとよい。また半導体チップの表面が液状の樹脂面に
ほぼ垂直になるように浸漬すると効果的である。In order to achieve the above-mentioned object, the present invention secures a semiconductor chip and an electrode substrate, coats the surface of the semiconductor chip with an insulating film, and further, the semiconductor chip and the electrode substrate are made of resin. In a method for manufacturing a semiconductor device to be sealed, a semiconductor chip and an electrode substrate are formed by a step of immersing a semiconductor chip and an electrode substrate in a liquid resin and a step of thermally curing the liquid resin adhered to the semiconductor chip and the electrode substrate. The surfaces of and are covered with the insulating film. It is effective that the material of the insulating film is polyimide liquid resin and the viscosity of the liquid resin is 10 cps to 50 cps. The material of the sealing resin is preferably epoxy resin. It is also effective to immerse the semiconductor chip so that the surface of the semiconductor chip is substantially perpendicular to the liquid resin surface.
【０００７】[0007]
【作用】液状樹脂の溶液に半導体チップを浸漬すること
で、液状樹脂を半導体チップ表面に被覆すると、半導体
チップ表面の濡れ性で液状樹脂が被着するため、膜厚が
パッシベーション部でも適正な厚さとなり、また半導体
チップの中心部や半導体チップ端付近の金属基板上でも
膜厚が厚くなることもなく、ほぼ均一な膜厚で全面が覆
われる。[Function] When the semiconductor chip surface is covered with the liquid resin by dipping the semiconductor chip in the liquid resin solution, the wetness of the semiconductor chip surface causes the liquid resin to adhere. In addition, the film thickness does not increase even on the metal substrate near the center of the semiconductor chip or the edge of the semiconductor chip, and the entire surface is covered with a substantially uniform film thickness.
【０００８】[0008]
【実施例】図１は一実施例の浸漬方法を表した図を示
す。コレクタ端子となる電極基板３１に半導体チップ１
を半田付けし、ゲート部をリード線７１でゲート端子と
なる電極体３２に接続し、エミッタ部をリード線７２で
エミッタ端子となる電極体３３に接続する。半導体チッ
プ１の周縁部は酸化膜で被覆されたパッシベーション部
２となっている。半導体チップ１上と電極基板３１上
に、絶縁力耐圧確保用の絶縁膜である樹脂膜４を被覆す
るために、容器９に入った液状樹脂６の溶液に半導体チ
ップ１上と電極基板３１上を溶液面に垂直になるように
浸漬する。ここで液状樹脂６としてポリイミド樹脂を使
用した。EXAMPLE FIG. 1 shows a diagram showing an immersion method according to an example. The semiconductor chip 1 is mounted on the electrode substrate 31 that serves as a collector terminal.
Are soldered, the gate portion is connected to the electrode body 32 serving as a gate terminal with the lead wire 71, and the emitter portion is connected to the electrode body 33 serving as an emitter terminal with the lead wire 72. The peripheral portion of the semiconductor chip 1 is a passivation portion 2 covered with an oxide film. On the semiconductor chip 1 and the electrode substrate 31, the solution of the liquid resin 6 contained in the container 9 is coated on the semiconductor chip 1 and the electrode substrate 31 in order to cover the resin film 4 which is the insulating film for ensuring the dielectric strength and breakdown voltage. Is soaked as to be perpendicular to the solution surface. Here, a polyimide resin was used as the liquid resin 6.
【０００９】図２は浸漬後、溶液から取り出した状態の
図を示す。液状樹脂６は半導体チップの中心部上、パッ
シベーション部２上、電極基板３１上でほぼ均一な膜厚
となっている。図３は液状樹脂の膜厚の分布図を示す。
同図でＡ、Ｂ、Ｃ、Ｄ、Ｅ、Ｆは膜厚測定ポイントを示
す。５０ｃｐｓ（ｃｐｓは粘度の単位でセンチポアズ：
ｃｅｎｔｉ−ｐｏｉｓｅを示す）の粘度の液状樹脂６を
従来法２０（滴下法）と本発明の方法３０（浸漬法）で
半導体チップ１上と電極基板３１上に被着した場合の液
状樹脂６の膜厚の分布を示す。従来法２０は半導体チッ
プ１の中心部上と半導体チップ端付近の電極基板３１上
で厚く、パッシベーション部２で極めて薄くなってい
る。また本発明の方法３０では、従来法と違って電極基
板３１の裏面も含め全面に亘ってほぼ均一に液状樹脂６
が被覆している。FIG. 2 shows a diagram of the state of being taken out from the solution after the immersion. The liquid resin 6 has a substantially uniform film thickness on the central portion of the semiconductor chip, the passivation portion 2, and the electrode substrate 31. FIG. 3 shows a distribution diagram of the film thickness of the liquid resin.
In the figure, A, B, C, D, E, and F indicate film thickness measurement points. 50 cps (cps is a unit of viscosity in centipoise:
of the liquid resin 6 having a viscosity of (centi-poise) is applied on the semiconductor chip 1 and the electrode substrate 31 by the conventional method 20 (dropping method) and the method 30 (immersion method) of the present invention. The distribution of film thickness is shown. In the conventional method 20, the thickness is large on the central portion of the semiconductor chip 1 and on the electrode substrate 31 near the end of the semiconductor chip, and extremely thin on the passivation portion 2. Further, in the method 30 of the present invention, unlike the conventional method, the liquid resin 6 is almost uniformly over the entire surface including the back surface of the electrode substrate 31.
Is covered.
【００１０】図４は液状樹脂の膜厚の分布データを表し
た図を示す。５０ｃｐｓの粘度の液状樹脂６を従来法２
０と本発明の方法３０で半導体チップ１上と電極基板３
１上に被覆した場合の液状樹脂６の膜厚の分布を示す。
膜厚は０から８０μｍの範囲で測定した。測定ポイント
のＣ点はパッシベーション部２の個所で従来法が極端に
薄くなっている。またＦ点より外では従来法では液状樹
脂６が被着されていない。FIG. 4 is a diagram showing distribution data of the film thickness of the liquid resin. Liquid resin 6 having a viscosity of 50 cps was prepared by conventional method 2
0 and the method 30 of the present invention on the semiconductor chip 1 and the electrode substrate 3
1 shows a distribution of the film thickness of the liquid resin 6 when the liquid resin 6 is coated on the surface 1.
The film thickness was measured in the range of 0 to 80 μm. The point C of the measurement point is a portion of the passivation portion 2 and the conventional method is extremely thin. Further, outside the point F, the liquid resin 6 is not adhered by the conventional method.
【００１１】図５は液状樹脂６の粘度を５ｃｐｓから８
０ｃｐｓに変化させて、本発明の方法で被着させた場合
の膜厚の分布図を示す。５ｃｐｓから５０ｃｐｓの範囲
の粘度では、膜厚のバラツキは２μｍから５μｍの範囲
内にあり、極めて良好である。表１は本発明の方法で被
着させた液状樹脂６の信頼性データを示す。FIG. 5 shows the viscosity of the liquid resin 6 from 5 cps to 8
The distribution chart of the film thickness when changing to 0 cps and applying by the method of the present invention is shown. When the viscosity is in the range of 5 cps to 50 cps, the variation in the film thickness is in the range of 2 μm to 5 μm, which is extremely good. Table 1 shows the reliability data of the liquid resin 6 deposited by the method of the present invention.
【００１２】[0012]
【表１】 ×：特性劣化 液状樹脂６の粘度は図５と同一で５ｃｐｓから８０ｃｐ
ｓである。また、信頼性試験は１０００時間（ｈｒ）の
電圧印加試験と５００サイクル（ｃｙ）の温度サイクル
試験である。電圧印加試験では膜厚が薄くなる５ｃｐｓ
の条件の液状樹脂６が５００Ｈｒで絶縁劣化を起こし、
一方温度サイクル試験では膜厚が厚くなる８０ｃｐｓの
条件の液状樹脂６が１００ｃｙでクラックが入り実用に
耐えないことが判明した。従って、信頼性を確保する液
状樹脂６の粘度は１０ｃｐｓから５０ｃｐｓが最適であ
る。[Table 1] X: Characteristic deterioration The viscosity of the liquid resin 6 is the same as in FIG.
s. Further, the reliability test is a voltage application test for 1000 hours (hr) and a temperature cycle test for 500 cycles (cy). 5 cps where the film thickness becomes thin in the voltage application test
The liquid resin 6 under the condition of 500 Hr causes insulation deterioration,
On the other hand, in the temperature cycle test, it was found that the liquid resin 6 under the condition of 80 cps at which the film thickness becomes thicker had cracks at 100 cy and could not be put to practical use. Therefore, the viscosity of the liquid resin 6 that ensures reliability is optimally 10 cps to 50 cps.
【００１３】[0013]
【発明の効果】液状樹脂を浸漬法により半導体チップお
よび電極基板に被着することで、半導体チップ上、パッ
シベーション部上および電極基板上でほぼ均一な膜厚を
確保でき、その後の熱硬化処理で異常な熱ストレスが半
導体チップに加わることを防止でき、半導体チップの電
気的特性の劣化を防止し、半導体チップの割れを防ぐこ
とができる。またこの液状樹脂の粘度を１０ｃｐｓから
５０ｃｐｓの範囲にすることで、均一な膜厚を確保し、
電気的、機械的な信頼性も確保できる。By applying the liquid resin to the semiconductor chip and the electrode substrate by the dipping method, it is possible to secure a substantially uniform film thickness on the semiconductor chip, on the passivation portion and on the electrode substrate. It is possible to prevent abnormal heat stress from being applied to the semiconductor chip, prevent deterioration of electrical characteristics of the semiconductor chip, and prevent cracking of the semiconductor chip. Also, by setting the viscosity of this liquid resin in the range of 10 cps to 50 cps, a uniform film thickness is secured,
Electrical and mechanical reliability can also be secured.
【図１】一実施例の浸漬方法を表した図FIG. 1 is a diagram showing an immersion method according to an embodiment.
【図２】浸漬後、溶液から取り出した状態の図FIG. 2 is a diagram showing a state of being taken out of the solution after the immersion.
【図３】液状樹脂の膜厚の分布図[Fig. 3] Distribution chart of film thickness of liquid resin
【図４】液状樹脂の膜厚の分布図FIG. 4 is a distribution diagram of the film thickness of the liquid resin.
【図５】液状樹脂の膜厚の分布図FIG. 5 is a distribution diagram of the film thickness of the liquid resin.
【図６】従来の半導体装置の樹脂封止（モールド）前の
平面図FIG. 6 is a plan view of a conventional semiconductor device before resin sealing (molding).
【図７】樹脂膜を形成する方法を表した図FIG. 7 is a diagram showing a method for forming a resin film.
１ 半導体チップ ２ パッシベーション部 ３１ 電極基板 ３２ 電極体 ３３ 電極体 ４ 樹脂膜 ５ モールド樹脂 ６ 液状樹脂 ７１ リード線 ７２ リード線 ８ ディスペンサ ９ 容器 ２０ 従来法（滴下法） ３０ 本発明の方法（浸漬法） Ａ 膜厚測定ポイント Ｂ 膜厚測定ポイント Ｃ 膜厚測定ポイント Ｄ 膜厚測定ポイント Ｅ 膜厚測定ポイント Ｆ 膜厚測定ポイント DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Passivation part 31 Electrode substrate 32 Electrode body 33 Electrode body 4 Resin film 5 Mold resin 6 Liquid resin 71 Lead wire 72 Lead wire 8 Dispenser 9 Container 20 Conventional method (dripping method) 30 Method of the present invention (immersion method) A film thickness measurement point B film thickness measurement point C film thickness measurement point D film thickness measurement point E film thickness measurement point F film thickness measurement point
Claims (4)
チップの表面を絶縁膜で被覆し、さらに半導体チップと
電極基板とが樹脂封止される半導体装置の製造方法にお
いて、液状の樹脂に半導体チップおよび電極基板を浸漬
する工程と、半導体チップおよび電極基板に被着した液
状の樹脂を熱硬化させる工程により、半導体チップと電
極基板との表面が前記絶縁膜で被覆されることを特徴と
する半導体装置の製造方法。1. A method for manufacturing a semiconductor device in which a semiconductor chip and an electrode substrate are fixed to each other, a surface of the semiconductor chip is covered with an insulating film, and the semiconductor chip and the electrode substrate are resin-sealed. The surface of the semiconductor chip and the electrode substrate is covered with the insulating film by the step of immersing the chip and the electrode substrate, and the step of thermally curing the liquid resin adhered to the semiconductor chip and the electrode substrate. Manufacturing method of semiconductor device.
で、該液状の樹脂の粘度が１０ｃｐｓないし５０ｃｐｓ
であることを特徴とする請求項１記載の半導体装置の製
造方法。2. The material of the insulating film is a liquid resin such as polyimide, and the liquid resin has a viscosity of 10 cps to 50 cps.
The method for manufacturing a semiconductor device according to claim 1, wherein
を特徴とする請求項１記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the sealing resin is epoxy resin.
垂直になるように浸漬することを特徴とする請求項１記
載の半導体装置の製造方法。4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip is immersed so that the surface of the semiconductor chip is substantially perpendicular to the liquid resin surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11807795A JPH08330295A (en) | 1995-03-24 | 1995-05-17 | Manufacture of semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7-65400 | 1995-03-24 | ||
| JP6540095 | 1995-03-24 | ||
| JP11807795A JPH08330295A (en) | 1995-03-24 | 1995-05-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08330295A true JPH08330295A (en) | 1996-12-13 |
Family
ID=26406544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11807795A Pending JPH08330295A (en) | 1995-03-24 | 1995-05-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08330295A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016159318A1 (en) * | 2015-03-31 | 2016-10-06 | 浜松ホトニクス株式会社 | Semiconductor device manufacturing method |
| JP2019186561A (en) * | 2016-04-07 | 2019-10-24 | 株式会社半導体エネルギー研究所 | Manufacture method of semiconductor device and display device |
-
1995
- 1995-05-17 JP JP11807795A patent/JPH08330295A/en active Pending
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10403676B2 (en) | 2015-03-31 | 2019-09-03 | Hamamatsu Photonics K.K. | Semiconductor device manufacturing method |
| KR20170133322A (en) * | 2015-03-31 | 2017-12-05 | 하마마츠 포토닉스 가부시키가이샤 | Method for manufacturing semiconductor device |
| WO2016159318A1 (en) * | 2015-03-31 | 2016-10-06 | 浜松ホトニクス株式会社 | Semiconductor device manufacturing method |
| US10615220B2 (en) | 2015-03-31 | 2020-04-07 | Hamamatsu Photonics K.K. | Semiconductor device and manufacturing method thereof |
| JP2022027973A (en) * | 2015-03-31 | 2022-02-14 | 浜松ホトニクス株式会社 | Semiconductor device and manufacturing method for the same |
| KR20170133328A (en) * | 2015-03-31 | 2017-12-05 | 하마마츠 포토닉스 가부시키가이샤 | Semiconductor device and manufacturing method thereof |
| JPWO2016159320A1 (en) * | 2015-03-31 | 2018-02-01 | 浜松ホトニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JPWO2016159318A1 (en) * | 2015-03-31 | 2018-02-01 | 浜松ホトニクス株式会社 | Manufacturing method of semiconductor device |
| EP3279924A4 (en) * | 2015-03-31 | 2018-11-07 | Hamamatsu Photonics K.K. | Semiconductor device manufacturing method |
| US10141368B2 (en) | 2015-03-31 | 2018-11-27 | Hamamatsu Photonics K.K. | Semiconductor device |
| CN107360729A (en) * | 2015-03-31 | 2017-11-17 | 浜松光子学株式会社 | Semiconductor device and its manufacture method |
| WO2016159320A1 (en) * | 2015-03-31 | 2016-10-06 | 浜松ホトニクス株式会社 | Semiconductor device and manufacturing method thereof |
| CN107408508A (en) * | 2015-03-31 | 2017-11-28 | 浜松光子学株式会社 | The manufacture method of semiconductor device |
| US10622403B2 (en) | 2015-03-31 | 2020-04-14 | Hamamatsu Photonics K.K. | Semiconductor device manufacturing method |
| US10622402B2 (en) | 2015-03-31 | 2020-04-14 | Hamamatsu Photonics K.K. | Semiconductor device |
| CN107360729B (en) * | 2015-03-31 | 2020-08-14 | 浜松光子学株式会社 | Semiconductor device and method for manufacturing the same |
| JP2020191478A (en) * | 2015-03-31 | 2020-11-26 | 浜松ホトニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP2020202400A (en) * | 2015-03-31 | 2020-12-17 | 浜松ホトニクス株式会社 | Manufacturing method for semiconductor device |
| JP2019186561A (en) * | 2016-04-07 | 2019-10-24 | 株式会社半導体エネルギー研究所 | Manufacture method of semiconductor device and display device |
| US11296132B2 (en) | 2016-04-07 | 2022-04-05 | Semiconductor Energy Laboratory Co., Ltd. | Peeling method and manufacturing method of flexible device |
| US11791350B2 (en) | 2016-04-07 | 2023-10-17 | Semiconductor Energy Laboratory Co., Ltd. | Peeling method and manufacturing method of flexible device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4558510A (en) | Method of producing a semiconductor device | |
| US20030042615A1 (en) | Stacked microelectronic devices and methods of fabricating same | |
| EP1191587B1 (en) | Packaging structure and method for automotive components | |
| JPH0239865B2 (en) | ||
| JP2005322902A (en) | Internal electrical isolation method for substrate for power semiconductor module | |
| JPS6312157A (en) | Heat resisting plastic semiconductor device | |
| JPH09502833A (en) | Coated bonding wires in high lead count packages | |
| EP0645812A1 (en) | Resin-sealed semiconductor device | |
| JPH08330295A (en) | Manufacture of semiconductor device | |
| JPH07161503A (en) | Chip thermister | |
| JPH09237869A (en) | Resin-encapsulated power module device and manufacture thereof | |
| JPS60178651A (en) | Semiconductor device | |
| US4974052A (en) | Plastic packaged semiconductor device | |
| JPS59763Y2 (en) | hybrid integrated circuit | |
| JPS61230344A (en) | Resin-sealed semiconductor device | |
| JPS63143850A (en) | Semiconductor device | |
| JPS6144436Y2 (en) | ||
| JPS622778Y2 (en) | ||
| JPH01297848A (en) | Semiconductor device and manufacture thereof | |
| JP2710207B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS6292331A (en) | Sealing method for semiconductor chip | |
| JP2605157B2 (en) | Mold package type thick film hybrid IC | |
| JPH0251905A (en) | Manufacture of piezoelectric resonator | |
| JPS62108554A (en) | Hybrid integrated circuit device and manufacture thereof | |
| JPH0246025Y2 (en) |