JPH08329693A - Semiconductor storage device, data processing device - Google Patents

Abstract

PURPOSE: To increase the guaranteed number of times of rewriting. CONSTITUTION: The number of times of writing to a memory cell is counted by a counter 113, refresh bias is applied to a memory cell by a memory control circuit 12 based on the counted result. Therefore, by reducing the deterioration of characteristics extracting electrons trapped in a unmatched part of a tunnel oxide film, an undesirably prolonged writing time is shortened, and the guaranteed number of times of rewriting is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which a plurality of memory cells each having a tunnel oxide film are arranged.
Further, the present invention relates to a technique for increasing the guaranteed number of rewrites therein, for example, a technique effectively applied to a flash memory and a data processing device including the same.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. 2-289997 discloses a batch erasing type EEPROM (electrically erasable and programmable read only memory). This collective erasing type EEPROM can be understood in the same meaning as the flash memory in this specification. The flash memory can rewrite information by electrical erasing / writing, and like the EPROM (electrically programmable read only memory), its memory cell can be composed of one transistor. , A function of electrically erasing all of the memory cells or a block of memory cells collectively. Therefore, the flash memory can rewrite the stored information in the state where it is mounted in the system, and the batch erasing function can shorten the rewriting time and contribute to the reduction of the chip occupying area. To do.

A flash memory cell has a two-layer structure of a floating gate and a control gate, and has an EPR.
It is a one-transistor cell that is almost the same as the OM. Writing is performed by applying a high voltage to the control gate and drain and injecting hot electrons generated in the vicinity of the drain junction into the floating gate to set the threshold value to a high value, as in the EPROM. Also,
Erasure is achieved by applying a high voltage to the source, grounding the control gate to a negative potential or 0 V, and pulling out electrons in the floating gate to the source by the tunnel phenomenon to set the threshold value to a low state. To be done.

[0004]

By the way, in the flash memory, the writing time tends to increase as the number of times of rewriting increases. For example, with a 16M flash memory, the initial value of the write time is about 3 μs (microseconds).
However, it has been confirmed by the inventor of the present application that the writing time becomes about 9 μs after the rewriting is performed 10,000 times.

The reason why the writing time becomes longer as the number of times of rewriting increases is that the electrons are trapped in the mismatched portion of the tunnel oxide film by the rewriting and the electric field between the gate and the drain is relaxed. It is supposed to do. This is the main factor that hinders the increase in the guaranteed number of rewrites.

An object of the present invention is to provide a technique for increasing the guaranteed number of rewrites.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the control means (112) for applying the refresh bias for releasing the electrons trapped in the tunnel oxide film (44) to the memory cell (MC).
A semiconductor memory device is configured to include.

Further, a counting means (113) for counting the number of times of writing of the memory cell and a refresh bias for releasing electrons trapped in the tunnel oxide film are applied to the memory cell based on the counting result of the counting means. And a control means (112) for controlling the semiconductor memory device (3).
81).

A data processing apparatus including a semiconductor memory device having the above control means, or a semiconductor memory device having the above counting means and the above control means, and a central processing unit (31) capable of accessing such semiconductor memory device. Make up.

[0012]

According to the above-mentioned means, the control means applies the refresh bias for releasing the electrons trapped in the tunnel oxide film to the memory cell. This alleviates an undesirably long writing time with an increase in the number of rewrites, and achieves an increase in the guaranteed number of rewrites.

[0013]

FIG. 2 shows a data processing device including a flash memory according to an embodiment of the present invention.

The data processing device shown in FIG. 2 is not particularly limited, but is a portable personal computer or the like, and a CPU (central processing unit) 31, an SRAM (static random access memory) via a system bus BUS. ) 33, ROM (Read Only Memory)
34, the peripheral device control unit 35, the display system 36, and the like are connected to each other so that signals can be exchanged therebetween, and predetermined data processing can be performed according to a predetermined program. The CPU 31 is the logical core of this system, and mainly addresses, reads and writes information, operates data, sequences instructions, accepts interrupts, activates information exchange between storage devices and input / output devices, etc. It has the function of, and is composed of an arithmetic control unit, a bus control unit, a memory access control unit, and the like. The SRAM 33 and the ROM 34 are positioned as internal storage devices. The SRAM 33 has
Programs and data required for calculation and control in the CPU 31 are loaded. The peripheral device control unit 35 controls the operation of the storage device 38 and the information input control from the keyboard 39 and the like. As the storage device 38, an auxiliary storage device such as a hard disk device is generally applied, but in the present embodiment, one or a plurality of flash memories are included for downsizing the device and improving impact resistance. It is used as a memory card. The application program executed by the CPU 31 and various data are stored in the storage device 38.

FIG. 1 shows a configuration example of a flash memory applied as the storage device 38.

The flash memory 381 shown in FIG.
Is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The flash memory 381 is not particularly limited, but it is an 8-bit data input / output terminal PI / O0-PI.
/ O7, 19-bit address input terminals PA0 to PA1
8. Low enable chip select signal input terminal PCE
N, a low-enable output enable signal input terminal POEN, a high-potential-side power source Vdd terminal such as 5V, a low-potential-side power source Vss terminal such as 0V, and 12V
A high voltage Vpp terminal such as

Reference numeral 100 denotes a memory cell array in which a plurality of flash memory cells each composed of an insulated gate field effect transistor having a two-layer gate structure are arranged in a matrix. The control gates of the flash memory cells are connected to corresponding word lines (not shown), the drains of the flash memory cells are connected to corresponding data lines (not shown), and the sources of the flash memory cells are common sources (not shown) for each memory block. Connected to the wire.

Address input buffer (AIB) 101
Converts an address signal supplied from the address input terminals PA0 to PA18 into an internal complementary address signal. The converted address signal is latched by the address latch circuit 102. An X address decoder and word driver (XADEC) 103 decodes the X address signal latched in the address latch circuit 102, and drives the word line based on a selection signal obtained by decoding. In the data read operation, the word driver drives the word line with a voltage such as 5V, and in the data write operation, drives the word line with a high voltage such as 12V. In a data erase operation, all word driver outputs are brought to a low voltage level, such as 0V. 104 is an address latch circuit 1
This is a Y address decoder (YADEC) that decodes the Y address signal latched in 02. Reference numeral 105 denotes a Y selector that selects a data line according to the output selection signal of the Y address decoder 104. Reference numeral 106 denotes a sense amplifier that amplifies a read signal from the data line selected by the Y selector 105 in the data read operation. A data output latch 107 holds the output of the sense amplifier 106. Reference numeral 108 is a data output buffer for outputting the data held by the data output latch 107 to the outside. 1
Reference numeral 09 is a data input buffer for fetching write data or command data supplied from the outside.
The write data or command data fetched from the data input buffer 109 is held in the data input latch 110. Of the write data held in the data input latch 110, the write circuit 111 supplies the write high voltage to the data line selected by the Y selector 105 with respect to the bit data corresponding to the logical value “0”. The high voltage for writing is supplied to the drain of the flash memory cell to which the high voltage is applied to the control gate according to the X address signal, and thereby the memory cell is written.

The command data latched by the data input latch 110 is supplied to the memory control circuit 112. The memory control circuit 112 also receives a chip selection signal and an output enable signal supplied from the terminals PCEN and POEN, and controls various internal operations such as read, erase, write operation, and write verify of the flash memory. In the present embodiment, although not particularly limited, this memory control circuit 112 is composed of an MPU (micro processing unit).

The operation of the flash memory 381 is determined by command data. Memory control circuit 112
Includes a command latch (not shown) that latches command data supplied from the data input latch 110, and a command decoder (not shown) that decodes the command latched in the command latch and generates control signals according to various operation modes. . The operation voltage required for each operation such as reading, erasing, and writing is supplied to each section according to the operation mode under the control of the memory control circuit 112.

Further, in this embodiment, the memory cell array 1
A counter 113 for counting the number of write times of 00 is provided. The number of times of writing referred to here includes the number of times of performing a write operation and the number of times of performing a pre-write operation for temporarily adjusting the threshold value of a memory cell to be erased to a high state in an erase operation. In the memory control circuit 112, based on the counting result of the counter 113, the memory cell array 10
The refresh bias application to 0 is controlled. The refresh bias is applied to reduce the deterioration of the characteristics of the memory cell by releasing the electrons trapped in the tunnel oxide film of the memory cell and to increase the guaranteed rewrite count. After the refresh bias is applied, the counting state of the counter 113 is initialized and prepared for the next refresh bias application. The refresh bias will be described later in detail.

FIG. 3 shows a configuration example of one flash memory cell included in the memory array 100.

As shown in FIG. 3, the flash memory cell MC has a two-layer structure of a floating gate 43 and a control gate 41, and is almost the same as an EPROM.
It is a transistor cell. That is, the floating gate 43 is formed on the P-channel substrate 45 via the tunnel oxide film 44, and the control gate 41 is further formed via the interlayer oxide film 42. Control gate 41 is coupled to the word line. Drain 47 is coupled to the data line arranged to intersect the word line.

The operation of writing information to the flash memory cell MC is realized, for example, by applying a high voltage to the control gate 41 and the drain 47 and injecting electrons from the drain side to the floating gate by avalanche injection. By this write operation, the threshold voltage of the flash memory cell MC seen from the control gate 41 becomes higher than that of the erased flash memory cell in which the write operation is not performed.

On the other hand, the erase operation is performed as shown in FIG.
For example, a high voltage is applied to the source 46, and electrons are extracted from the floating gate 44 to the source 46 side by a tunnel phenomenon. By this erase operation, the threshold voltage seen from the control gate 41 is lowered. The threshold voltage of the memory cell is set to a positive voltage level in both the write and erase states. That is, the threshold voltage in the written state is raised and the threshold voltage in the erased state is lowered with respect to the word line selection level applied from the word line to control gate 41. By having such a relationship between both threshold voltages and the word line selection level, it is possible to configure a flash memory cell with one transistor without using a selection transistor.

In the read operation, the flash memory cell MC is applied to the drain 47 and the control gate 41 so that weak programming, that is, undesired carrier injection to the floating gate 44 is not performed. The voltage is limited to a relatively low value. For example, a low voltage of about 1 V is applied to the drain 47 and a low voltage of about 5 V is applied to the control gate 41. By detecting the magnitude of the channel current flowing in the memory cell by these applied voltages, the logical value “0” of the information stored in the memory cell MC,
"1" can be determined.

Next, the refresh bias of the memory cell will be described.

As described above, the flash memory cell tends to increase the write time as the number of times of rewriting increases. For example, as shown in FIG. 6, the initial value of the write time is about 3 μs (microseconds), while the initial value is 100 μs.
The writing time after rewriting 00 times is about 9 μs, which is about three times as long as the initial value. It is considered that this is because electrons are trapped in the mismatched portion of the tunnel oxide film 44 by rewriting and the electric field between the gate and the drain is relaxed. Therefore, as shown in FIG. 5, it is possible to reduce the characteristic deterioration by extracting the electrons trapped in the tunnel oxide film 44 to the drain 47 side. That is, the control gate 41 is set to a low voltage level such as 0 V, and a voltage of about 5 V is applied to the drain 47, whereby the electrons trapped in the tunnel oxide film 44 are drained.
It can be pulled out to the 7 side. The voltage application for such electron extraction is referred to as refresh bias application in this specification. This refresh bias application is performed when the predetermined number of times of rewriting is reached. Although not particularly limited, in the case of a memory cell having the characteristics shown in FIG. 6, it is preferable to apply the refresh bias when the number of rewrites reaches 1000 times. Then, when the number of times of rewriting reaches 1000 times, the writing time of about 5 μs is originally required, but as shown in FIG. 7, the writing time can be returned to almost the initial value (3 μs). . That is, the counter 11
When the count value of 3 reaches 1000, the refresh bias is applied under the control of the memory control circuit 112, so that the write time is returned to the initial value. Since the writing time is returned to the initial value in this way, rewriting is enabled again thereafter. In other words, the guaranteed number of rewrites can be increased.

FIG. 8 shows the flow of the erase operation.

When an erase command is given to the memory control circuit 112, pre-verify and pre-write are performed in order to temporarily set the threshold value of the memory cell to be erased to a high state (steps 81 and 82). . If it is determined that the pre-write state is appropriate, the erase (erase) operation is performed (step 83). Erase-verify is performed (step 84), and when it is determined that the erased state of the memory cell is appropriate, the counter 113 is incremented by the count-up instruction signal from the memory control circuit 112, and the count value is increased. T is incremented (step 85). The memory control circuit 112 determines whether or not the count value T of the counter 113 has reached 1000 (step 86). In this determination, if it is determined that the count value T has reached 1000, A refresh bias is applied to the memory cell under the control of the memory control circuit 112 (step 87). This refresh bias application is collectively performed on the memory cells to be erased. And
The counter 113 is initialized (step 88) and the series of erase operations is completed. Further, when it is determined in step 86 that the count value T of the counter 113 has not reached 1000, refresh bias application is not necessary, so that a series of erase operations is performed without performing the refresh bias application. Will be terminated.

According to the above embodiment, the following operational effects can be obtained. (1) The number of write times of the memory cell is counted by the counter 113, and the memory control circuit 11 is based on the count result.
Since the refresh bias is applied to the memory cell by means of 2, the writing time is undesirably lengthened by extracting the electrons trapped in the mismatched portion of the tunnel oxide film to reduce the characteristic deterioration. It is possible to mitigate the occurrence of the error and thereby increase the guaranteed number of times of rewriting.

(2) Since the flash memory 381 is provided with a counter for counting the number of times of writing of memory cells, there is no need for an external device such as the CPU 31 in the data processing device in which the flash memory 381 is mounted. It is possible to determine an appropriate refresh bias application timing.

(3) If the flash memory is used over the guaranteed number of times of rewriting, a data error is likely to occur. However, since the guaranteed number of times of rewriting can be increased as described above, the flash memory and it can be accessed. A data processing device including a CPU enables stable data processing for a long period of time.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above-mentioned embodiment, the flash memory 38 is provided with the counter 113 as a write number counting means.
However, the number of times of writing may be counted by a counting unit such as a counter arranged outside the flash memory, and the counting result may be taken into the flash memory. Since the erasing or writing of the flash memory is instructed by the CPU 31, the system BU
By monitoring S, the count of the number of writes is obtained as K. Further, in the case where the number of writes of the flash memory is counted outside the flash memory as described above, the refresh bias is applied by applying a predetermined command instructing the refresh bias to the flash memory. be able to.

In the above description, the case where the invention made by the present inventor is mainly applied to a flash memory as a memory LSI, which is a field of application which is the background of the invention, has been described, but the present invention is not limited thereto. For example, it can be applied to a program memory of a data processing device such as a single chip microcomputer.

The present invention can be applied on condition that it includes at least a memory cell.

[0039]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the refresh bias for releasing the electrons trapped in the tunnel oxide film is applied to the memory cell, the write time is alleviated to be undesirably long as the number of rewrites is increased, and the guaranteed number of rewrites is reduced. It is possible to increase. Further, in a microcomputer having a built-in flash memory as a program memory, the life of the flash memory greatly affects the life of the microcomputer. Therefore, extending the life of the flash memory by increasing the guaranteed number of rewrites of the flash memory is It is effective in extending the life of the computer.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration example of a flash memory that is an embodiment of the present invention.

FIG. 2 is a block diagram of a configuration example of a data processing device including the flash memory.

FIG. 3 is an explanatory diagram of a memory cell configuration in the flash memory.

FIG. 4 is an explanatory diagram of an erase operation of a memory cell in the flash memory.

FIG. 5 is an explanatory diagram for applying a refresh bias to a memory cell in the flash memory.

FIG. 6 is a writing time change characteristic diagram when a refresh bias is not applied.

FIG. 7 is a write time change characteristic diagram when a refresh bias is applied.

FIG. 8 is a flow chart of an erase operation of the flash memory.

[Explanation of symbols]

 31 CPU 33 SRAM 34 ROM 35 Peripheral Device Control Unit 36 Display System 38 Storage Device 39 Keyboard 41 Control Gate 42 Interlayer Oxide Film 43 Floating Gate 44 Tunnel Oxide Film 45 P-Channel Substrate 46 Source 47 Drain 100 Memory Cell Array 101 Address Input Buffer 102 Address Latch 103 Word driver 104 Y address decoder 105 Y selector 107 Data output latch 108 Data output buffer 109 Data input buffer 110 Data input latch 111 Writing circuit 112 Memory control circuit 113 Counter 381 Flash memory

Claims (3)

[Claims] 1. In a semiconductor memory device including a memory cell in which a tunnel oxide film is formed between a substrate and a floating gate, a refresh bias for releasing electrons trapped in the tunnel oxide film is applied to the memory cell. A semiconductor memory device comprising control means. 2. In a semiconductor memory device including a memory cell in which a tunnel oxide film is formed between a substrate and a floating gate, counting means for counting the number of times of writing of the memory cell, and trapped in the tunnel oxide film. A semiconductor memory device, comprising: a control means for applying a refresh bias for emitting electrons to the memory cell based on a counting result of the counting means. 3. A data processing device comprising the semiconductor memory device according to claim 1 and a central processing unit capable of accessing the semiconductor memory device.