JPH06223587A - Nonvolatile semiconductor storage - Google Patents

Abstract

PURPOSE:To adjust the threshold value of a dummy cell by avalanche hot carrier implanting an electron or a positive hole after the electron stored in the charge storage part of the dummy cell is discharged. CONSTITUTION:A threshold value adjustment mode is selected with a specific signal by a mode selection circuit 32 to output a signal S1. By an erasure operation control part 33, the signal S1 is outputted with the signal S1. A Fowler- Nordheim (F-N) tunnel erasure control circuit 34 is operated by the signal S1, and the signal or a voltage is impressed to the dummy cell in a dummy cell part 31 to perform F-N tunnel erasure. After the erasure is ended, the signal S3 is outputted by the control part 33. The avalanche hot carrier implantation control circuit 35 is operated by the signal S3, and various kinds of signals or voltages are impressed to the dummy cell where the erasure is performed, and the avalanche hot carrier implantation is performed to the floating gate of the dummy cell to adjust the threshold value after erased. When the threshold value is adjusted by the implantation at the time of writing data in a memory cell and erasing the data, the threshold value of the dummy cell is updated at every rewrite.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to an EEPROM capable of electrically writing data and erasing the data collectively or in block units.
Regarding

[0002]

An EEPROM capable of electrically writing data and erasing the data collectively or in block units.
FIG. 3 shows the configuration of a typical data read circuit in (hereinafter referred to as flash EEPROM).

A memory cell 11 composed of a non-volatile transistor having a floating gate and a control gate is connected to a bit line 12. A memory cell selecting transistor 13 and a load transistor 14 are connected in series between the bit line 12 and the application point of the power supply voltage Vcc. Reference numeral 15 is a differential type sense amplifier, and a potential separating transistor 17 is connected between one of the input nodes 16 and the series connection point of the transistors 13 and 14. A voltage lower than the power supply voltage Vcc generated by the bias circuit 18 is supplied to the gates of both the transistors 14 and 17, whereby the potential amplitude of the bit line 12 is limited to a certain width. Further, a load P-channel transistor 19 is connected between the input node 16 and the application point of the power supply voltage Vcc, and the bit line potential limited to a certain amplitude is again input at the input node 16 of the sense amplifier 15. Expanded.

Reference numeral 20 is a reference potential generation circuit for generating a reference potential supplied to the other input node 21 when detecting the read data from the memory cell 11 in the sense amplifier 15. This reference potential generation circuit 20 has a dummy cell 22 having the same configuration as the memory cell 11, a transistor 23 having the same configuration as the selection transistor 13, and a load transistor 14 in order to make the circuit conditions the same as those on the memory cell side. ,
It is composed of transistors 24 and 25 having the same structure as 19 and a transistor 26 having the same structure as the transistor 17 for node separation. The power source voltage Vcc is constantly supplied to the gates of the dummy cell 22 and the transistor 23 in the reference potential generating circuit 20, and the output of the bias circuit 18 is supplied to the gates of the transistors 24 and 25. Note that all transistors whose channel type is not specified are N-channel transistors.

The data read circuit using the dummy cell has a feature that the processing margin is wide because the memory cell on the main body side and the dummy cell use transistors having the same shape. Further, since the same voltage Vcc is applied to the gates of the memory cell and the dummy cell at the time of reading data, there is a feature that the margin between the power supply voltage and the write amount is widened. The sensitivity of the differential sense amplifier depends on the load transistors 14 and 24 on the memory cell side and the dummy cell side.
It is determined by the element size ratio and the threshold value of the dummy cell.

By the way, in the case of EPROM, the dummy cell is used in a state after UV erasing (erasing by irradiation of ultraviolet rays). On the other hand, in the case of the flash EEPROM, the dummy cell is used in a state after UV erasing or in a state after electrical erasing like the main body memory cell. The adjustment of the threshold value after the electrical erasing of the dummy cell is always performed before the product is shipped, and is not performed thereafter.

In the flash EEPROM, the threshold of the memory cell after electrical erasing can be set regardless of the threshold after UV erasing. Therefore, the amount of channel implantation for threshold control can be increased. When the channel implantation amount is increased, the threshold value after UV erasing is increased, but hot carriers at the time of writing are increased and the writing characteristics are improved.

However, by increasing the amount of channel implantation,
If the threshold value after UV erasing is increased and the dummy cell is used in the state after UV erasing, the margin of the power supply voltage at the time of reading data becomes small, so the dummy cell cannot be used in this state. Therefore, in this case, threshold adjustment is performed on the dummy cell by electrical erasing. In the threshold adjustment by the electrical erasing, first, if the threshold value of the dummy cell is lower than a desired value, writing is performed. After that, electrical erasing of the dummy cell and verification for checking whether a desired threshold value is obtained are repeated, and the threshold value adjustment is ended when the verification is passed.

[0009]

By the way, the threshold value of the dummy cell is important because it greatly affects the sensitivity of the sense amplifier and the margin of the power supply voltage. Therefore, if the threshold value of the dummy cell is adjusted by electrical erasing, if it is attempted to be performed with high accuracy, it is conceivable to shorten the erasing time per time or decrease the voltage for erasing to increase the number of verifications. This verification is generally performed by applying an arbitrary voltage to the gate and drain of the dummy cell by a test circuit and monitoring the current flowing through the drain. The measurement of the current value usually requires a time of about several ms in the test circuit.

On the other hand, what must be noted in the dummy cell is the problem of soft writing. The soft write means that writing is performed little by little in the read state. For this soft light, you usually have to guarantee 10 years. The most severe state for soft write is during program verify. In this program verify, a voltage higher than a normal read voltage, for example, 7V is applied to the gates of the memory cell and the dummy cell in order to guarantee the write amount. Flash EE
In the case of PROM, the number of data rewrites is 10 ⁴ Times to 10 ⁵ In many cases, the program verify state in which a high voltage is applied to the dummy cell is E
It is extremely long compared to the case of PROM. In addition, since the first gate oxide film (gate oxide film between the channel and the floating gate) of the flash EEPROM is considerably thinned, when the gate (control gate) receives a high voltage, the EPR
There is a problem that erroneous writing is more likely than OM.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a nonvolatile semiconductor memory device capable of adjusting the threshold value of a dummy cell in a short time. Still another object of the present invention is to provide a nonvolatile semiconductor memory device in which the threshold value of the dummy cell does not change even if the number of times of rewriting is increased.

[0012]

A nonvolatile semiconductor memory device of the present invention has a charge storage section, and a plurality of memory cells for storing data according to the amount of electrons stored in the charge storage section. An arrayed memory cell array, a differential amplifier that detects data stored in a selected memory cell in the memory cell array, and a charge storage unit similar to the memory cell are included. A dummy cell for generating a reference potential used when detecting stored data in a memory cell, and electrons emitted from the charge storage portion of the dummy cell are emitted, and electrons or holes are avalanche hot carrier injection after the emission of electrons. Therefore, a threshold value adjusting means for adjusting the threshold value of the dummy cell is provided.

[0013]

The threshold value of the dummy cell is adjusted by injecting electrons or holes into the avalanche hot carrier after the electrons stored in the charge storage portion of the dummy cell are released. This threshold adjustment is automatically performed before shipping the product and during actual use.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a part of the configuration of an embodiment of the non-volatile semiconductor memory device of the present invention. In the nonvolatile semiconductor memory device of this embodiment, a plurality of memory cells 11 shown in FIG. 3 are provided. The plurality of memory cells are arranged in a matrix to form a memory cell array. Further, a plurality of dummy cells 22 in FIG. 3 are also provided, and these are shown as a dummy cell section 31 in FIG.

Further, in FIG. 1, reference numeral 32 is a mode select circuit for selecting an operation mode when adjusting the threshold value for each dummy cell in the dummy cell section 31. The mode select circuit 32 selects an operation mode in which threshold adjustment is performed when a special test signal that is not disclosed to the user is given, and outputs the signal S1. Upon receiving this signal S1, the erase operation control unit 33 first outputs the signal S2. Upon receiving this signal S2, F-N (Farrer-Nordheim:
Fowler Nordheim) The tunnel erasure control circuit 34 operates,
Various signals or voltages are applied to the dummy cells in the dummy cell section 31, and the FN tunnel erase of the dummy cells is performed. After the erase operation by the F-N tunnel erase control circuit 34 is completed, the erase operation controller 33 outputs the signal S3. In response to this signal S3, the avalanche hot carrier injection control circuit 35 operates and various signals or voltages are applied to the erased dummy cells in the dummy cell section 31, and avalanche hot is applied to the floating gates of the dummy cells. Carrier injection is performed and threshold adjustment is performed after erasing.

If the threshold value is adjusted by avalanche hot carrier injection at the time of writing or erasing data in the memory cell, the threshold value of the dummy cell is updated every time the data is rewritten.

Further, the voltage internally generated at the time of writing or erasing can be used as a voltage when performing avalanche hot carrier injection of the dummy cell.

In the conventional adjustment of the threshold value of the dummy cell by electric erasing, a large number of verifications are required, a long time is spent, and a complicated sequence is required. But,
According to the above-described embodiment, the threshold value adjustment of the dummy cell can be performed without verifying, so that it can be performed in a short time and in a simple sequence. Further, according to the above-described embodiment, even if the threshold value of the dummy cell fluctuates to some extent due to various obstacles, the threshold value can be automatically adjusted during use, so that the fluctuation of the threshold value of the dummy cell can be almost eliminated. Here, when the erasing method in which the threshold value by avalanche hot hole injection is self-converging is adopted also on the main body memory cell side, the threshold value of the dummy cell becomes almost the same value as the threshold value after erasing of the memory cell, which is desirable for the sense amplifier. Next, a method of selecting an operation mode in the mode selection circuit 32 when performing threshold adjustment will be described.

Generally, a semiconductor memory device has various test modes, and normally, a test signal is externally applied by using a method called three-value control. This three-value control is
By giving a signal of HH level which is higher than H level in addition to H and L levels, one external pin has three values. And when testing, H
The test mode can be set by giving the H level.

Conventionally, the test mode is set by applying a high voltage to the input pin. However, as the number of test items increases, the number of pins used for ternary input begins to run short.
Therefore, address pins have come to be used for three-value input. However, when the address pin is used for the test, the address pin cannot be used for the address input. Also, since most test circuits use power supply units to generate high voltages such as 12V, test signals cannot be switched over time.

Therefore, in this embodiment, the test signal is applied to the mode select circuit 32 by utilizing the three-value control and all or some of the data input / output pins. Hereinafter, a specific example thereof will be described.

FIG. 2 is a block diagram showing the entire structure of the nonvolatile semiconductor memory device according to the above-mentioned embodiment. In order to select a memory cell array 41 composed of a plurality of memory cells, and a memory cell in the memory cell array 41. Column decoder 42, column gate circuit 43, and row decoder 44, for example, an address buffer 45 to which 20-bit addresses A0-A19 are supplied, for example, input / output control of 16-bit data D0-D15 and including the sense amplifier. I / O buffer 46, control circuit 4 to which output enable signal / OE, chip enable signal / CE, etc. are supplied
7, a test circuit 48 including the mode select circuit 32, the erase operation controller 33, the FN tunnel erase controller 34 and the avalanche hot carrier injection controller 35 in FIG. It is configured.

In such a configuration, when a high voltage higher than the H level is supplied to the output enable signal (/ OE) pin, for example, the control circuit 47
As a result, out of 16 pins used for inputting / outputting data D0-D15, eight D0-D7 are used as original I / O pins, and the remaining eight D8-D15 are input as test signals. Used as a pin for.

That is, in this case, by inputting a combination of normal H or L level signals to the eight pins D8 to D15, the test circuit 48 is operated to detect the dummy cell as described with reference to FIG. An operation mode for threshold adjustment is selected and executed. In this case, since the high voltage is not used for selecting the operation mode, the test signal can be switched over time.

[0026]

As described above, according to the present invention,
It is possible to provide a nonvolatile semiconductor memory device in which the threshold value of the dummy cell can be adjusted in a short time, and the threshold value of the dummy cell does not change even if the number of times of rewriting is increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a partial configuration of an embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a block diagram showing the overall configuration of the above embodiment.

FIG. 3 is a circuit diagram of an EEPROM data reading circuit.

[Explanation of symbols]

11 ... Memory cell, 22 ... Dummy cell, 31 ... Dummy cell section,
32 ... Mode select circuit, 33 ... Erase operation control section, 34 ... F
-N tunnel erase control circuit, 35 ... Avalanche hot carrier injection control circuit, 41 ... Memory cell array, 48 ... Test circuit.

Claims (4)

[Claims] 1. A memory cell array having a charge storage section, in which a plurality of memory cells storing data according to the amount of electrons stored in the charge storage section are arranged, and a memory cell array selected in the memory cell array. A differential amplifier for detecting the data stored in the memory cell, and a charge storage part similar to the memory cell, and a reference potential used when the stored data of the memory cell is detected by the differential amplifier. A dummy cell for generating, and threshold adjusting means for adjusting the threshold of the dummy cell by emitting electrons stored in the charge storage portion of the dummy cell and by injecting electrons or holes into avalanche hot carriers after the emission of the electrons. A nonvolatile semiconductor memory device characterized by the above. Item 2. The nonvolatile semiconductor memory device according to item 1. 2. The method according to claim 1, wherein the injection of electrons or holes into the charge storage portion of the dummy cell by the threshold value adjusting means is performed during a data erasing operation for the nonvolatile semiconductor memory device. Nonvolatile semiconductor memory device. 3. The method according to claim 1, wherein the injection of electrons or holes into the charge storage portion of the dummy cell by the threshold value adjusting means is performed during a data writing operation to the nonvolatile semiconductor memory device. Nonvolatile semiconductor memory device. 4. The non-volatile semiconductor memory device according to claim 1, wherein the threshold adjusting means is made operable by applying a test signal to all or some of the data input / output pins.