JPH08328540A - Picture data synthesizing display device - Google Patents

Abstract

PURPOSE: To obtain a picture data synthesizing display device capable of performing display positional designations for every pixel even in the case the parallel processing of plural pixels is performed in the inside by making a video frequency high speed to the highly accurate display of a display device. CONSTITUTION: An address generating part 14 generates readout addresses to a frame memory for window display 5 from respective values of an X counter 10, a Y counter 11, an X register 8 and a Y register 9. Moreover, a window output control part 15 outputs window display data 112 matched with the display positions desiginated in one pixel unit by receiving the values of picture data for window display 106 equivalent to plural pixels simultaneously outputted by the frame memory for window display 5 and the X register 8. Then, the display positional designations for every pixel are highly accurately performed even in the case the parallel processing of plural pixels is performed in the inside by superposing picture data stored in the memory 5 with the positional designations of one pixel unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data synthesizing display device, and more particularly to an image data synthesizing display device for displaying data of a frame memory together with other external video data.

[0002]

2. Description of the Related Art Conventionally, image data synthesizing display devices of this type have been disclosed, for example, in Japanese Patent Application No. 89-15116 and Japanese Patent Laid-Open No. 02-288.
As shown in No. 681, video data and sub-screen data input from the outside are superimposed and displayed on the data written in the frame memory.

FIG. 8 is a block diagram showing an example of the configuration of a conventional image data combination display device. In FIG. 8, the drawing processor 1 draws a graphic in the frame memory 2. At that time, if the window is displayed, the window is also drawn by superimposing it on the graphic drawing. On the other hand, the external video I / F 33 that received the external video 101
Draws the contents of the external video 101 in the frame memory 2 and the graphic drawing in accordance with the control timing of the drawing processor 1. The frame memory 2 reads out the drawing content to the display device 4 as the digital video 103 in synchronization with TV. Display device 4 is digital video 1
03 is displayed.

In addition, this kind of image data composition display device generally has a dedicated frame memory other than the frame memory in order to superimpose and display window display data and external input video display data. These window data and external input video data are drawn in this dedicated frame memory, and these data may be switched and displayed.

For example, in JP-A-59-222888 and JP-A-58-177635, frame memory image data and externally input video or window display image data are provided corresponding to X and Y addresses on the screen. There is a description example of the technology of switching and displaying. FIG. 9 shows Japanese Patent Laid-Open No. 59-2228.
FIG. 1 is a block diagram showing an example of an image data combination display device according to No. 88 and Japanese Patent Laid-Open No. 58-177635.

In FIG. 9, the drawing processor 1 which receives the drawing command 102 from the CPU 6 draws a graphic in the frame memory 2. On the other hand, the window drawing data or the external video 121 is input to the window or external video display frame memory 25 to perform drawing. Further, the CPU unit 6 includes an X register 8 and a Y register 9
XY coordinates on the screen are set as the display start point. The frame memory unit 2 uses the frame memory unit image data 107.
Is output to the read switching unit 37 in synchronization with TV.

When the value of the X register 8 and the value of the X counter 10 match, and the value of the Y register 9 and the value of the Y counter 11 match, the window or external video display frame memory 25 displays the window display image. The data or the external input video 120 is read out in synchronization with the TV, and the switching unit 3
Output to 7.

The switching section 37 normally outputs the frame memory section image data 107 as a digital video 103. When the value of the X register 8 and the value of the X counter 10 match and the value of the Y register 9 and the value of the Y counter 11 match, the window display image data or the external input video 120 is output as the digital video 103. To do.

On the frame memory 25 for displaying a window or an external video, a portion corresponding to one horizontal line
Image data for window display or external input video 12
When the output of 0 ends, the switching unit continues to output the frame memory unit image data 107 as the digital video 103 until the value of the display start position of the X register 8 and the value of the X counter 10 match next.

[0010]

However, in the conventional image data composition display device shown in FIG. 8 described above, the drawing is performed directly in the frame memory 2 under the control of the drawing processor 1. Therefore, a circuit for timing control with graphic drawing, control of external video drawing position, etc. is required.
In addition, a program for changing the window drawing that is usually performed by the basic OS and adding control due to addition of hardware is required. When the drawing method in the frame memory 2 is changed and the superimposed display is performed as described above, there is a problem that the standard hardware and the graphic interface installed in the software must be changed significantly.

When the displayed window display data is moved to another place on the display screen, graphic drawing is performed again at the position on the frame memory 2 where the window display data was drawn before the movement. There is a need. Especially when the window is moved frequently, there is a problem that the load of the drawing processor 1 increases.

On the other hand, in the image data synthesizing display device shown in FIG. 9, the X and Y coordinates on the screen are designated to simply switch the frame memory image data 107 and the window display image data or the external input video 120. To do. Generally, when performing high-definition display on a display device, it is necessary to increase the video frequency, which is the frequency of ON / OFF repetition for each pixel of the display. In this case, parallel processing of a plurality of pixels is required internally.

However, in the image data synthesizing display device shown in FIG. 9, since the X and Y coordinates on the screen are designated and switching is simply performed, when a plurality of pixels are processed in parallel, one pixel is processed. It is difficult to specify the display position for each. Therefore, there is a problem that the window cannot be moved smoothly. Further, for the same reason, when the window display frame memory is applied to the cursor display, there is a problem that the accurate position cannot be displayed.

The present invention makes it possible to specify the display position for each pixel even if the video frequency is increased for high definition display of the display device and parallel processing of a plurality of pixels is internally performed. It is an object of the present invention to provide a simple image data synthesizing display device.

[0015]

In order to achieve the above object, an image data synthesizing display device of the present invention has an X counter for counting pixel clocks, a Y counter for counting horizontal synchronizing signals, and a start position for window display. , An X register for setting on the X axis of the display screen, and a Y register for setting the start position of the window display on the Y axis of the display screen,
CP for setting the numerical values stored in the X and Y registers
U, a memory for storing the image data of the window display, and N pixel image data (N is a natural number of 2 or more) stored in the memory from the numerical values held by the X counter, the Y counter, the X register, and the Y register. Address generation means for generating an address for simultaneously reading out data, output control means for outputting image data of N pixels based on the X-axis position designated by a numerical value held by the X register, and 1
Image data in a frame is input for every N pixels, and image data of N pixels output by the output control means is input, and image synthesis means for synthesizing the respective image data is provided, and an X register and a Y register are provided. It is characterized in that the image data stored in the memory is superimposed on the image data of one frame at the coordinate position corresponding to the numerical value held by the register by specifying the position for each pixel.

Further, the above-mentioned image data synthesizing display device has a parallel / serial converting means for sequentially converting the image data for each N pixel synthesized by the image synthesizing means into image data for one pixel and outputting the image data. It is advisable to display the generated image data for each pixel in a window. Note that it is preferable to further have a frame memory for storing one frame of image data and read out the image data for each N pixels of one frame from the frame memory.

Further, the above memory is a bitmap memory for displaying a cursor, or image data of an input video input from the outside is stored in the memory, and the image data of the input video is superimposed on the image data of one frame. It is good to display it in a window.

[0018]

Therefore, according to the image data synthesizing display device of the present invention, the pixel clock is counted, the horizontal synchronizing signal is counted, and the start position of the window display is set to the X position of the display screen.
Set on the axis, and set the window display start position on the Y axis of the display screen. The CPU sets a numerical value to be the start position of the window display, the image data of the window display is stored in the memory, and the N pixel image data stored in the memory is converted from the numerical values held in the X and Y counters and the X and Y registers, respectively. At the same time, an address for reading is generated. Control and input the output of N pixel image data based on the position of the X axis specified by the numerical value held in the X register, and input the image data in one frame for each N pixel,
The respective image data are combined. Therefore, the image data stored in the memory can be superimposed on the image data of one frame at the coordinate position corresponding to the numerical values held by the X register and the Y register by specifying the position of each pixel.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of an image data composition / display apparatus according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 7, there is shown an embodiment of an image data composition / display device of the present invention.

In the following description, the writing of the original image data to the frame memory is simply called "drawing", and the drawing of the image data by the drawing processor other than the drawing of the window data and the drawing of the external video data is performed.
They are called "graphic drawing" and distinguish both.

The image data composition and display device of the embodiment is shown in FIG.
It can be roughly divided into the characteristic constituent parts of the present invention and other constituent parts as shown by the chain line. The latter of these two categories is
The CPU unit 6, the drawing processor 1, the frame memory unit 2, the X register 8, and the Y, which are the same as the conventionally used components,
It is composed of a register 9, an X counter 10, a Y counter 11, and a display device 4. In the former case, the window display frame memory 5, the image data synthesizing unit 12, P /
The S unit 13, the address generator 14, and the window output controller 15 are included.

In each of the above-mentioned components, the drawing processor 1 is an image processing unit for performing graphic drawing on the frame memory unit 2. The frame memory unit 2 is a storage unit that stores image data including a color palette, and the image data stored here is the frame memory unit image data 1
It is output to the image data synthesizing unit 12 as 07.

The CPU section 6 is a central processing section that outputs the drawing command 102 to the drawing processor 1 and sets the XY coordinates on the screen as the display start point in the X register 8 and the Y register 9.

The X register 8 and the Y register 9 are registers for counting and storing the display start point of the window image data 105 on the display screen of the display device 4 as an XY coordinate point. The value stored in these registers is C
It is set by PU6. The X counter 10 counts the pixel clock 109, and the Y counter 11 counts the horizontal synchronizing signal 110.

The window display frame memory 5 is a temporary storage memory for storing image data for window display. The image data stored in the window display frame memory 5 is the window image data 105. The reading of the image data at the predetermined position of the stored window image data 105 is based on the signal of the read address 111. The read image data is output as the window display image data 106.

The image data synthesizing unit 12 is an image processing unit for synthesizing the frame memory unit image data 107 and the window display data 112 output from the window output control unit 15. The combined image data is output as a parallel digital video signal 108. The image data synthesizing unit 12 reads out the frame memory unit image data 107 for four pixels at a time from the frame memory unit 2 in synchronization with TV.

The P / S section 13 is a parallel / serial conversion circuit section for converting the parallel digital video signal 108, which is a parallel signal, into a serial signal. The digital video signal converted here is the digital video signal 103.
Is output as

The address generator 14 generates an address signal in which image data for each frame displayed on the display device 4 is divided by XY coordinates, and the read address signal 11 is generated.
It is a circuit unit that outputs 1 as 1. The read address signal 111 output is the X register 8 and the Y register 1
It is a start position based on the output numerical value of 0 and is a signal synchronized with the output signals of the X counter and the Y counter.

The window output control unit 15 is an image data output control unit that outputs the window display data 112 by using the value of the window display image data 106 and the value of the X register 8 as input signals. The window output control unit 15 outputs the window display data 112 of four pixels that match the display position of the window image to the image data synthesizing unit 12 based on the display start position designated by the X register 8 on a pixel-by-pixel basis. When the window display position is specified in pixel units, it is necessary to adjust where each bit of the window display data 112 is allocated. The window output control unit 15 has a function of performing this adjustment.

FIG. 2 is a block diagram showing one embodiment of a more detailed circuit configuration of the window output control section 15. The window output control unit A150 that processes the pixel 0 to the window output control unit D153 that processes the pixel 3 have the same circuit configuration. Here, the window output control unit A
From 150 to the window output control unit D153, the value indicating which pixel position on the screen corresponds to P
It is defined as X (n) (n = 0 to 3). Where 4
After the pixel, a value obtained by sequentially adding 4 to PX (n), that is, P
X (n) +14 + ... The window display image data 106 is 4-bit (W0 to W3) data because it is processed in parallel with four pixels.

The window output control unit A150 will be described. The MUL control unit 21 determines the value of SX113 and PX.
The MUL control signal 118 is output from the value of (0) 114. The MUL control signal 118 is a signal that controls which input bit the multiplexer 20 should select and which should be output by the calculation in the MUL control unit 21. The multiplexer 20 receives the window display image data 106, selects 1-bit image data in the window display image data 106 under the control based on the MUL control signal 118, and selects the 1-bit selected by the D / FF 22 and the selector 23. The image data of is output. The D / FF 22 latches the input image data by the pixel clock 109 and outputs the latched image data.

The SEL control section 24 uses the one signal SX113.
And the value of the other signal PX (0) 114, the SEL control signal 119 is output. The SEL control signal 119 is SE
This is a signal for controlling which of the image data input to the input ports A and B should be selected and output by the selector 23 according to the processing result in the L control unit 24. The selector 23 receives the SEL control signal 119, selects the data of the port A or B, and outputs the 0th bit of the window display data 112.

Similarly, the window output control unit B15
1 is the first bit based on the signal PX (1) 115, the window output control unit C152 is the second bit based on the signal PX (2) 116, and the window output control unit D153 is the third bit based on the signal PX (3) 117. Each of the eye window display data 112 is output. The output data of each of the 0th bit to the 3rd bit constitutes image data in units of 4 bits.

Next, details of the operation of the window output controller 15 will be described. 3 to 5 are diagrams showing the relationship between the display screen and the internal processing bits when the 4-pixel parallel processing is performed. Normally, in a TV scanning type display device,
As shown in FIGS. 3 to 5, display is started in the X direction from the left side on the screen. FIG. 3 shows the frame memory unit image data 10
This is an example of the case where only 7 is displayed. Numbers 0 to 3 in the figure indicate bits of the frame memory image data 107. In the case of 4-pixel parallel processing, the frame memory unit 2 always reads out 4 pixels (the portion surrounded by the solid line in the figure) at once. Therefore, bits 0 to 3 of the same frame memory image data 107 are always assigned to pixel positions 0 to 3 (or a value obtained by sequentially adding 4 to each) in the figure.

A value indicating the X coordinate of the display start position set in the X register 8 is defined as SX, and a value indicating the Y coordinate of the display start position set in the Y register 9 is defined as ST. FIG. 4 shows a window display in FIG.
This is the case where the display start position SX is SX = 1. W0 to W3 indicate the bits of the window display data 112. in this case,
Bit W0 is assigned to the position of pixel 1 (or a value obtained by sequentially adding 4 to 1) on the display screen. Similarly, W1 and W2 are allocated thereafter. Also, the pixel position 0 on the display screen
The bit 0 of the frame memory image data 107 is displayed as is, but the bit of W3 is assigned to the pixel position of the value obtained by sequentially adding 4 to the pixel position 0.

FIG. 5 shows a case where the window display is performed and the pixel position SX is SX = 3 in FIG. In this case, the bit W0 is assigned to the pixel position of pixel position 3 (or a value obtained by sequentially adding 4 to 3) on the display screen. Further, the bits of the frame memory unit image data 107 are displayed at the pixel positions 0, 1, and 2 on the display screen as they are, but at the pixel positions of the value obtained by sequentially adding 4 to each of the pixel positions. Bits W1, W2 and W3 are allocated respectively.

As described above, when the window display position is designated in pixel units, the window display data 1
It is necessary to adjust where to allocate each of the 12 bits. It is the function of the window output control unit 15 to make this adjustment.

Next, a processing procedure of image data combination display will be described. In the case of 4-pixel parallel processing, the display pixel position is repeatedly operated by sequentially adding 4 to the values of 0 to 3 as already described in FIG.
This indicates that considering the binary number, only the lower 2 bits need be considered. The upper bits are used for repetition. Therefore, SX considers only the value of the lower 2 bits here.

The MUL control unit 21 calculates PX (n) (where n = 0 to 3) -SX + 4, ignores overflow of 3 bits or more, and outputs any one of 0 to 3 as the MUL control signal 118. Outputs the calculated value.
The multiplexer 20 inputs the MUL control signal 118 of any value from 0 to 3 and selects and outputs 1 bit of the window display image data 106 of W0 to W3. When this operation is applied to FIG. 5, it is understood that W1 is selected when the display position of the 0th pixel is 0-34 = 1.

Similarly, the first pixel, the second pixel, and the third pixel are selected. However, at the display position of the third pixel,
3-3 + 4 = 4, and the overflowed bit is set. This is ignored and W0 is consequently selected.
Similarly, when this operation is applied to FIG. 4, it is understood that W3 is selected at 0-1 + 4 = 3 at the display position of the 0th pixel. Similarly, the first pixel, the second pixel itself, and the third pixel are similarly selected.

In this way, the multiplexer 20
The bits of the window display image data 106 are selected and output to the select 23 and the D / FF 22. on the other hand,
The selector 23 inputs the multiplexer output data 122, which is the output of the multiplexer 20, to the port A, and inputs the output D / FF output data 123 of the D / FF 22 to the port B.

The SEL control section 24 determines that SX≤PX (n).
SEL that selects port A when (where n = 0 to 3)
The control signal 119 is output. Also, SX> PX (n)
SEL for selecting port B when (where n = 0 to 3)
The control signal 119 is output.

Therefore, when SX = 1 in FIG. 4, since 1> 0 in the window output control unit A150, D / FF2
The port B which is the output of 2 is selected and is output as the 0th bit (0th of the display pixel position) of the window display data 112. On the other hand, in the window output control unit B151,
Since 1 = 1, port A, which is the output of the multiplexer 20, is selected and output as the first bit (first display pixel position) of the window display data 112. Similarly, the window output control unit C152 and the window output control unit D153 also output.

The above procedure will be described with reference to the timing chart. 6 and 7 show the window output control unit 15
5 is a timing chart showing the operation of FIG. 4 and shows the operation when SX = 1 in FIG. FIG. 6 shows the 4-bit window display image data 106 and the multiplexers 20, 20, and 2 of the window output control units A, B, C, and D in FIG.
The timing relationship between the respective data of 0, 20 and D / FF 22 and the pixel clock 109 is shown. Further, the relationship between the timing at which the numerical value held by the X register 8 and the numerical value held by the X counter 10 match and the display position on the display screen is shown in the relationship between the bit number of the window display data 112 selectively output by the selector 23. ing.

Here, the window display image data 10
6-bit data in a batch, WV0,
WV1, ... Further, each bit of the 4-bit data is referred to as WV0-W0, WV0-W1, ... In order. Here, W0, W1 and W3 are the same as those already defined in FIGS. 4 and 5. These window display image data 106 are synchronized with the rising edge of the pixel clock 109, and the window display frame memory 5
Read more.

Inside the window output control unit A150,
The multiplexer 20 selects WV0-W3. The multiplexer output data 122 which is its output is received, and D /
The FF 22 outputs the D / FF output data 123 delayed by one cycle of the pixel clock 109 with respect to the multiplexer output data 122. The selector 23 selects this output and outputs it as the 0th bit (0th of the display pixel position) of the window display data 112. On the other hand, inside the window output control units B, C, and D 151 to 153, each selector 23 has a multiplexer output data 122.
Is selected and is output as the corresponding bit of the window display data 112.

Therefore, in the first output, the 0th display pixel position is not output, and the image data synthesizing unit 12 outputs the frame memory unit image data 107 as it is.
Window display data 11 after the first display pixel position
2 is output, and the image data composition unit 12 displays this. In this way, the values in the window display frame memory 5 are displayed. FIG. 7 is a rewriting of FIG. 4 with the contents of FIG. The same processing is performed in the case of FIG.

In the image data synthesizing display device constituted by the above-mentioned respective parts, the CPU part 6 outputs the drawing command 102 to the drawing processor 1. This drawing command 10
Upon receiving 2, the drawing processor 1 draws a graphic in the frame memory unit 2 corresponding to the screen. When the window is displayed, the window drawing data 105 is also drawn in the window display frame memory 2. The frame memory unit 2 reads the frame memory unit image data 107 for four pixels at a time in the X direction in synchronization with the TV, and outputs it to the image data composition unit 12.

On the other hand, the address generation unit 14 uses the X counter 1
When 0 and the value of the X register 8 match and the values of the Y counter 11 and the Y register 9 match, the read address 111 is output to the window display frame memory 5. The output of the read address 111 is performed until the display is completed for one line in the horizontal direction on the window display frame memory 5. For example, if the window size on the display screen is 64 × 64 pixels, then 64
The read address 111 is generated and output until the window display image data 106 for pixels is output.

The window display frame memory 5 receives the read address 111 and outputs the window display image data 106 for four pixels at a time in the X direction. The window output control unit 15 receives the window display image data 106 and the value of the X register 8 and displays the window display data 112 for four pixels, which corresponds to the display start position designated by the X register in pixel units, as an image. Data synthesizer 12
Output to.

The image data synthesizing unit 12 synthesizes the frame memory unit image data 107 and the window display data 112 and outputs a parallel digital video 108. The P / S unit 13 performs parallel / serial conversion on the parallel digital video 108 to obtain the digital video 103.
Is output and is displayed on the display device 4.

In addition, in FIG. 1, the drawing processor 1
Outputs the window drawing data 105, it is also possible to generate the window drawing data 105 by an external video and perform the same processing. In this case, the external video image is displayed in the window of the display screen. Further, by changing the window display frame memory 5 to a cursor display bitmap memory, it is possible to display the cursor in the same manner.

Although the above-described embodiment is a preferred embodiment of the present invention, the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention. For example, although the case of parallel processing of four pixels has been described in the present embodiment, it is obvious that the present invention can be applied to parallel processing of any number of pixels by the same method.

[0054]

As is apparent from the above description, the image data composition display device of the present invention counts pixel clocks, horizontal synchronization signals, and the start position of window display on the X axis of the display screen. Set and set the window display start position on the Y-axis of the display screen. Further, the CPU sets a numerical value to be the start position of the window display, the memory stores the image data of the window display, and the N-pixel image stored in the memory from the numerical values held by the X and Y counters and the X and Y registers, respectively. An address for simultaneously reading data is generated. The output of N pixel image data based on the position of the X axis specified by the numerical value held in the X register is controlled and input, and the image data in one frame is input for each N pixel, and each image data is input. Is synthesized. By superimposing the image data stored in the memory on the image data of one frame at the coordinate position corresponding to the numerical values held by the X register and the Y register by specifying the position of each pixel, the video frequency can be displayed with high definition. It is possible to specify the display position for each pixel even when the processing speed is increased and a plurality of pixels are internally processed in parallel.

Therefore, even if the parallel processing of a plurality of pixels is internally performed, the window display can be smoothly moved. Further, when the memory for window display is applied to the cursor display, accurate pixel-by-pixel It is possible to display the cursor at the position.

[Brief description of drawings]

FIG. 1 is a circuit configuration block diagram showing an embodiment of an image data combination display device of the present invention.

2 is a block diagram showing a more detailed circuit configuration example of a window output control unit 15 in FIG.

FIG. 3 is a relationship diagram between a display position of a display screen and an internal processing bit with respect to a scanning direction, showing a case where display is performed only with image data in a frame memory unit.

4 shows a case where the window display start position is SX = 1 in the relationship of FIG.

5 shows a case where the window display start position is SX = 3 in the relationship of FIG.

6 is a timing diagram of the window output control unit 15 shown in FIGS. 1 and 2. FIG.

FIG. 7 is a relationship diagram between a display screen and internal processing bits when the window display start position is SX = 1.

FIG. 8 is a circuit block diagram showing an example of a conventional image data combination display device.

FIG. 9 is a circuit block diagram showing another example of a conventional image data combination display device.

[Explanation of symbols]

 1 Drawing Processor 2 Frame Memory Section 4 Display Device 5 Window Display Frame Memory 6 CPU Section 8 X Register 9 Y Register 10 X Counter 11 Y Counter 12 Image Data Synthesis Section 13 P / S Section 14 Address Generation Section 20 Multiplexer 21 MUL Control Part 22 D / FF 23 Selector 24 SEL control part 103 Digital video 105 Window drawing data 106 Window display image data 107 Frame memory part image data 108 Parallel digital video 109 Pixel clock 110 Horizontal sync signal 111 Read address 112 Window display data 113 SX 114 PX (0) 115 PX (1) 116 PX (2) 117 PX (3) 118 MUL control signal 119 SEL control signal 122 Multiplexer Output data 123 D / FF output data 150 Window output control unit A 151 Window output control unit B 152 Window output control unit C 153 Window output control unit D

Claims (5)

[Claims] 1. An X counter for counting a pixel clock, a Y counter for counting a horizontal synchronizing signal, an X register for setting a start position of window display on the X axis of a display screen, and a start position for window display. A Y register that is set on the Y axis of the screen, a CPU that sets the X register and the stored numerical value of the Y register, a memory that stores the image data of the window display, the X counter, the Y counter, the X register, and the Y register. An address generation unit that generates an address for simultaneously reading out image data of N pixels (N is a natural number of 2 or more) stored in the memory from the numerical values held by the registers, and the numerical values held by the X register. Output control means for outputting image data of N pixels with reference to a designated X-axis position, and an image within one frame. Image input means for inputting data for every N pixels and for inputting image data of N pixels output by the output control means, and for synthesizing the respective image data, the X register and the Y register hold An image data combination display device, characterized in that the image data stored in the memory is superposed on the image data of the one frame at a coordinate position corresponding to the numerical value by specifying a position for each pixel. 2. The image data composition display device further comprises parallel / serial conversion means for sequentially converting the image data of each N pixel combined by the image composition means into image data of one pixel and outputting the image data. The image data composition display device according to claim 1, wherein the converted image data for each pixel is displayed in a window. 3. The image data combination display device further comprises a frame memory for storing the image data of the one frame, and the image data for every N pixels of the one frame is read from the frame memory. The image data composition display device according to claim 1 or 2. 4. The image data synthesizing display device according to claim 1, wherein the memory is a bitmap memory for displaying a cursor. 5. The image data of an input video input from the outside is stored in the memory, and the image data of the input video is superimposed on the image data of the one frame and displayed in a window. 4. The image data combination display device according to any one of 4 above.