JPH08327702A - Trigger-signal generating circuit for memory testing pattern - Google Patents

Abstract

PURPOSE: To realize the trigger-signal generating circuit for a memory testing pattern, which can obtain the setting value for each resistor from the testing pattern without the reference with a pattern program and can readily obtain the intended trigger. CONSTITUTION: A counter 20, which is connected to a conventional trigger signal output and counts the number of the trigger signals, is provided. A D resistor 22, which sets the number of the signals generated by an address trigger to the intended trigger signal, is provided. A coincidence circuit 21 generates the trigger signal when the value of the counter 20 is compared with the value of the D resistor 22 and agrees and the trigger signal is generated, is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test pattern trigger signal generation circuit for a memory test pattern generator of a semiconductor test apparatus, which makes it easier to debug the device.

[0002]

2. Description of the Related Art In a memory test, it is general to repeat writing and reading by designating the same address many times in one test. Further, when debugging a device, it is a condition that facilitates debugging that only a trigger signal is generated at a specific address designated for debugging.

FIG. 6 shows a conventional trigger signal generating circuit. This circuit compares a memory address generated from the memory address generator 10 with a preset value of the A register 14A in a matching circuit 13A, and generates an address trigger when they match, an address trigger circuit 30.
A value of PC generated from the PC (program counter) generating section 12 is compared with a preset value of the B register 14B in the coincidence circuit 13B, and a program counter trigger is generated when a coincidence occurs. A pattern count trigger circuit 30C that compares the number of patterns generated from the circuit 30B and the pattern counting unit 11 with a preset value of the C register 14C in the matching circuit 13C and generates a pattern count trigger when they match. The mode register 16 comprises a trigger control circuit 15 for designating a logical combination of the above triggers and generating a trigger signal.

In the memory test, there are various test patterns such as marching and galloping which will be described later.
The same memory address is specified many times to write and read. Therefore, when the address for debugging is set in the A register 14A, the address trigger occurs many times. Debugging is difficult when the trigger signal is generated many times. Therefore, a specific value is set in the B register 14B, a program counter trigger is generated, an address trigger signal is generated when the program counter has a specific value, or a specific value is set in the C register 14C and the pattern count is set. Trigger was generated and at the same time a trigger signal was generated to proceed with debugging.

[0005]

In the above trigger signal generation method, the program counter value is set in the B register 14B and the pattern count value is set in the C register 14C by referring to the pattern program. , Had to set. It is an object of the present invention to realize a memory test pattern trigger signal generation circuit that can obtain a setting value from a test pattern to a register without referring to a pattern program and can easily obtain a target trigger. I am trying.

[0006]

In order to achieve the above object, the trigger signal generating circuit of the present invention is configured as follows. That is, the match circuit 13A compares the memory address generated from the memory address generator 10 with the preset value of the A register 14A,
An address trigger circuit 30A that generates an address trigger when they match, a PC value generated from the PC generator 12, and a preset value of the B register 14B are compared by the matching circuit 13B, and when they match, a program counter A program counter trigger circuit 30B that generates a trigger, the number of patterns generated by the pattern counting unit 11, and a preset value of the C register 14C are compared by a matching circuit 13C, and when they match, a pattern count trigger is generated. Pattern count trigger circuit 30
In the trigger signal generation circuit configured by C and the trigger control circuit 15 that generates a trigger signal by designating the logical combination of the triggers by the mode register 16 as described above,

A counter 20 for counting the number of trigger signals connected to the trigger signal output is provided to set the number of address triggers generated up to the target trigger signal.
A register 22 is provided, and a match circuit 21 is provided which compares the value of the counter 20 with the value of the D register 22 and generates a trigger signal when they match.

In another configuration, a counter 20 for counting the number of address trigger signals connected to the address trigger signal output is provided, and a D register for setting the number of address trigger signals generated by the target trigger signal. Two
2, the value of the counter 20 and the D register 22 are provided.
Is provided and a matching circuit 21 for generating an address count trigger signal when they match is provided.
Thus, the trigger control circuit 25 for generating the trigger signal by designating the logical combination of the triggers is provided.

In still another configuration, since the pattern counting section 11 is used as a counter for counting the number of address trigger signals for the address trigger signal output, a select circuit is provided between the address trigger signal output and the pattern counting section 11. 23 is provided, and a C register 14C is provided for the purpose of setting the number of address trigger signals generated up to the target trigger signal, and when the value of the counter and the value of the C register 14C are compared and they match, an address count trigger A match circuit 13C for generating a signal is provided, and when the pattern count enable signal is selected in the select circuit 23, which is a multiplexer, it is the same as the conventional circuit, and when the address trigger is selected, The circuit is controlled to achieve the object of the present invention,
The mode register 36 for controlling the trigger control circuit 35 for generating a trigger signal by designating a logical combination of the above triggers is provided and configured.

[0010]

In the trigger signal generating circuit configured as described above, the set value to the register can be obtained from the test pattern without referring to the pattern program, and the desired trigger can be easily obtained. , It has the effect of improving the work efficiency of the test engineer during debugging.

[0011]

【Example】

(Embodiment 1) FIG. 1 shows an embodiment of the present invention. This circuit comprises a counter 20 for counting the number of trigger signals connected to a conventional trigger signal output, and a D register 2 for setting the number of address triggers generated before a target trigger signal.
2 and a coincidence circuit 21 for generating a trigger signal when the value of the counter 20 and the value of the D register 22 are compared and coincide with each other.

For example, when a memory having an N address is tested using a galloping pattern, W0 is written as 0, W1 is written as 1, R0 is read as 0, and R0 is written as R.
When 1 is read as 1, reading and writing to each address are performed as shown in FIG.

At this time, the target cell is read (N-1) times, the disturb cell is read 2 (N-1) times during this time, and the target cell read is performed twice by writing 1 and 0 before and after the test 40. , Since 0 is written N times for initialization, when all the patterns when the galloping pattern is executed once are summed, a pattern of N + (3 (N-1) +2) × N = 3N ² is generated. Will be done.

Also, the address N1 of a certain target cell
Pay attention to the access to the
1) times, write before and after 2 times, read as disturb cells 2 (N-1) times, write initialization is 1
Since it is the number of times, it is 1+ (N-1) + 2 + 2 in total.
(N-1) = 3N, which depends on the test method.

Assuming that the address starts from 0, when the write W1 cycle of the address N1 of 1 is triggered, the write of initialization is performed once and the read as a disturb cell is 2 ((N1 + 1) -1) in that cycle.
Since the target write is once, the total is 1 + 2 ((N1 + 1) -1) + 1 = 2 (N1 + 1).
Since it is the next time to generate the N1 address, A in FIG.
N1 in the register 14A and 2 (N1 + in the D register 22
A trigger can be easily applied by setting 1).

Further, for example, when a memory having N addresses is tested by using a marching pattern, writing / reading to / from each address is performed as shown in FIG. At this time, the number of times that the address N1 is generated is 5 times in one execution, which is determined by the test method. When triggering at W1 which is a write cycle of 1, it is sufficient to trigger at the time of address designation corresponding to the third time. Therefore, N1 is set in the A register 14A of FIG.
By setting 3 to 3, it is easy to set W1 of address N1.
You can trigger the cycle.

(Embodiment 2) FIG. 4 shows another embodiment. This circuit is connected to the conventional address trigger signal output,
A counter 20 for counting the number of address trigger signals, a D register 22 for setting the number of address trigger signals generated up to a target trigger signal, and a value of the counter 20 and a value of the D register 22 are compared. A matching circuit 21 that generates an address count trigger signal when they match. Also in this case, the target trigger can be easily set by setting N1 in the A register 14A and the number of triggers in the D register 22 as in the first embodiment.

(Embodiment 3) FIG. 5 shows still another embodiment. This circuit includes a pattern counter 11 connected to a conventional address trigger signal output via a select circuit 23.
Is used as a counter for counting the number of address trigger signals, and the C register 14C for setting the number of address trigger signals generated up to the target trigger signal is compared with the value of the counter and the value of the C register 14C. And a matching circuit 13C that generates an address count trigger signal when they match. The select circuit 23 is a multiplexer controlled by the mode register 36, and when the pattern count enable signal is selected,
The circuit is the same as the conventional circuit, and when the address trigger is selected, the circuit achieves the object of the present invention. When the address trigger is selected, as in the first embodiment, N1 is set in the A register 14A and C register 14 is set.
By setting the number until C is triggered, the target trigger can be easily set.

[0019]

Since the present invention is configured as described above, it has the following effects. In other words, the setting value for each register can be obtained from the test pattern without referring to the pattern program, and the target trigger can be easily obtained, which improves the work efficiency of the test engineer during debugging. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a galloping pattern.

FIG. 3 is an explanatory diagram showing a marching pattern.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing still another embodiment of the present invention.

FIG. 6 is a conventional circuit block diagram.

[Explanation of symbols]

 10 Memory Address Generation Unit 11 Pattern Counting Unit 12 PC (Program Counter) Generation Unit 13A, 13B, 13C, 21 Matching Circuit 14A A Register 14B B Register 14C C Register 15, 25, 35 Trigger Control Circuit 16, 26, 36 Mode Register 20 counter 22 D register 23 select circuit 30A address trigger circuit 30B program counter trigger circuit 30C pattern count trigger circuit 40 target cell read test

Claims (3)

[Claims] 1. A match circuit (13A) compares a memory address generated from a memory address generator (10) with a preset value of an A register (14A), and generates an address trigger when they match. The address trigger circuit (30A), the PC value generated from the PC generator (12), and the preset value of the B register (14B) are compared by the matching circuit (13B), and when they match, the program counter A program counter trigger circuit (30B) for generating a trigger, the number of patterns generated by the pattern counting section (11), and a preset value of the C register (14C) are matched with each other by a matching circuit (13).
The trigger control for designating the logical combination of the above triggers by the pattern count trigger circuit (30C) that generates a pattern count trigger when compared in C) and the mode register (16) and generates the trigger signal. A trigger signal generating circuit composed of a circuit (15) is provided with a counter (20) connected to the trigger signal output and for counting the number of trigger signals, and an address trigger is generated before the target trigger signal. A D register (22) for setting the number is provided, and a matching circuit (21) that generates a trigger signal when the value of the counter (20) and the value of the D register (22) are compared and matched is provided. A memory test pattern trigger signal generation circuit characterized by: 2. A matching circuit (13A) compares the memory address generated from the memory address generation unit (10) with a preset value of the A register (14A), and when they match, an address trigger is generated. The address trigger circuit (30A), the PC value generated from the PC generator (12), and the preset value of the B register (14B) are compared by the matching circuit (13B), and when they match, the program counter A program counter trigger circuit (30B) for generating a trigger, the number of patterns generated by the pattern counting section (11), and a preset value of the C register (14C) are matched with each other by a matching circuit (13).
The trigger control for designating the logical combination of the above triggers by the pattern count trigger circuit (30C) that generates a pattern count trigger when compared in C) and the mode register (16) and generates the trigger signal. A trigger signal generating circuit composed of a circuit (15) and a counter (20) connected to the address trigger signal output, for counting the number of address trigger signals, and to the target trigger signal. Is provided with a D register (22) for setting the number of occurrences, and a match circuit (21) for generating an address count trigger signal when the value of the counter (20) and the value of the D register (22) are compared and matched. , And the logical combination of each trigger is specified by the mode register (26). A trigger signal generation circuit for a memory test pattern, which is provided with a trigger control circuit (25) for generating. 3. A matching circuit (13A) compares the memory address generated from the memory address generation unit (10) with the preset value of the A register (14A), and when they match, an address trigger is generated. The address trigger circuit (30A), the PC value generated from the PC generator (12), and the preset value of the B register (14B) are compared by the matching circuit (13B), and when they match, the program counter A program counter trigger circuit (30B) for generating a trigger, the number of patterns generated by the pattern counting section (11), and a preset value of the C register (14C) are matched with each other by a matching circuit (13).
The trigger control for designating the logical combination of the above triggers by the pattern count trigger circuit (30C) that generates a pattern count trigger when compared in C) and the mode register (16) and generates the trigger signal. In the trigger signal generating circuit configured with the circuit (15), since the pattern counting section (11) is used as a counter for counting the number of address trigger signals for the address trigger signal output, the address trigger signal output and the pattern counting are performed. A select circuit (23) is provided between the unit (11) and a C register (14C) for the purpose of setting the number of address trigger signals generated up to the target trigger signal. An address count trigger signal is generated when the values in the register (14C) are compared and they match. Provided circuits (@ 13 C), the selection circuit is a multiplexer (23),
When the pattern count enable signal is selected, it is the same as the conventional circuit, and when the address trigger is selected, the circuit is controlled so as to achieve the object of the present invention. A trigger signal generating circuit for a memory test pattern, comprising a mode register (36) for controlling a trigger control circuit (35) for designating a logical combination and generating a trigger signal.