JPH08321778A - A/d converter circuit - Google Patents

Abstract

PURPOSE: To obtain the A/D converter circuit in which an output of a high bit is attained at a high speed without increasing the circuit scale even in the case of employing an A/D converter of a low bit output. CONSTITUTION: Two signals included in an input signal are separated and an 8-bit A/D converter 6 inside the circuit is used to convert them into digital signals respectively and the digital signals are latched by two latch circuits 7, 8 as two signals. One latch output is multiplied by a multiple of three by a multiplier and the other output and the multiplied output are added by an adder to obtain a 10-bit signal and latched to be outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a low bit output A / D.
The present invention relates to an A / D conversion circuit configured to perform high-bit output A / D conversion using a converter.

[0002]

2. Description of the Related Art Conventional A / D conversion circuits include parallel comparison type and integration type. The parallel comparison type A / D conversion circuit is
In principle, it comprises 2N comparators for obtaining N-bit resolution, a resistor group for setting the reference value of each comparator, and an encoder for converting the output of each comparator into an N-bit binary code. However, there is an advantage that high-speed conversion can be obtained.

Further, an integration type A / D conversion circuit includes an integrator for integrating an input voltage and a reference voltage, a switch for switching the input voltage and the reference voltage, and a comparison for comparing the output of the integrator with a reference value. And a counter that counts the output signal period of the comparator in principle, and has an advantage that high resolution A / D conversion can be realized with a relatively simple configuration.

[0004]

However, since the parallel comparison type A / D conversion circuit requires 2N comparators to convert the number of N bits, the circuit scale becomes large.
Further, the integration type A / D conversion circuit has a problem that the conversion speed is slow.

An object of the present invention is to provide an A / D conversion circuit which enables high-speed and high-bit output without increasing the circuit scale even when using a low-bit output A / D converter. That is.

[0006]

To this end, a first invention is directed to a signal separation circuit for separating each signal component from an input signal having M signal components, and each signal separated by the signal separation circuit. M sample and hold circuits for sampling and holding, N-bit A / D converters, and signals output to the A / D converters by selectively switching the outputs of the M sample and hold circuits. Switching circuit and above A
Output signals of the M / N converters for latching the output signal of the D / D converter in accordance with the switching timing of the signal switching circuit, and the output signals of the M N-bit first latch circuits Of M multipliers for multiplying the output signals of the M multipliers, N + A bit adders for adding the output signals of the M multipliers, and N + A for latching the output signals of the adder.
And a bit second latch circuit.

In a second aspect based on the first aspect, the input signal is M = 2 as a composite video signal having a luminance signal and a chroma signal, and a multiplication factor of a multiplier for multiplying the digital signal of the luminance signal is The multiplication factor of the multiplier for multiplying the digital signal of the chroma signal is set larger.

[0008]

According to the present invention, M signals included in the input signal are separated and digitized by one internal N-bit A / D converter, and the digital signal is divided by M latch circuits. The signals are divided into M signals and latched, the latch outputs are multiplied by multipliers of different magnifications, then added by an adder, latched, and output to extract a digital signal of N + α bits. By using a high-speed internal A / D converter, high-speed and high-bit output is possible without increasing the circuit scale even if the internal A / D converter has a low bit.

[0009]

Embodiments of the present invention will be described below. FIG. 1 shows an A / D conversion circuit according to an embodiment of the present invention. Here, N
An example of inputting a video composite signal of a TSC television signal and performing A / D conversion will be described.

Reference numeral 1 is an input terminal for inputting the video composite signal, and 2 is a signal separation circuit for separating the luminance signal Y and the chroma signal C from the video composite signal and adjusting the level of each signal. Reference numerals 3 and 4 denote sample hold circuits for sampling / holding the luminance signal Y and the chroma signal C separated by the signal separation circuit 2, respectively. Sampling signal S1 input to one of the sample and hold circuits 3
The sampling signal S2 input to the other sample and hold circuit 4 has the same frequency (chroma signal C
Is about 3 to 5 times the frequency).

Reference numeral 5 denotes a signal switching circuit composed of an analog switch or the like, which includes the sampling signal S1,
It is switched by the switching signal S3 having the same frequency as the frequency of S2, and the outputs of the sample hold circuits 3 and 4 are alternately selected. Reference numeral 6 denotes an A / D converter for A / D converting the hold signal output from the signal switching circuit 5, and an 8-bit parallel comparison type is used.

Reference numerals 7 and 8 denote latch circuits, which latch the output data of the A / D converter 6 by latch signals L1 and L2 having the same frequency as the sampling signals S1 and S2 but opposite phases to each other. To do. Reference numeral 9 is a multiplier that triples the input data. Reference numeral 10 is an adder for adding the data output from the multiplier 9 and the data output from the latch 8 (equivalent to interposing a multiplier of 1 × but no multiplier), and 11 of the adder 10. A latch circuit 12 holds output data as a latch signal L3 (same frequency as the latch signals L1 and L2), and 12 is a digital output terminal.

In this A / D conversion circuit, the signal separation circuit 2 separates the luminance signal Y and the chroma signal C from the composite video signal, and the maximum value of those signals is the A / D converter 6 in the subsequent stage. The levels are adjusted so that the level corresponds to the input full range of. The signals Y and C are alternately sampled and held by the sampling signals S1 and S2 in the sample and hold circuits 3 and 4, respectively. The held signals Y and C are sent to the signal switching circuit 5
Are alternately selected by and are converted into 8-bit digital signals by the A / D converter 6 in the next stage. Although the level of the chroma signal C is considerably smaller than that of the luminance signal Y, the chroma signal C is separated in this way, and the level is adjusted corresponding to the full range of the A / D converter 6 and then A / D converted. The signals C and Y can be represented by the same resolution (8 bits).

Then, the digital signal of the luminance signal Y is selectively latched by the latch circuit 7 side and multiplied by 3 in the multiplier 9. The output digital value of the latch circuit 7 is 2 in decimal notation.
In the case of 55, multiplying this by 3 gives 765 in the decimal system, which can be represented by 10 bits in binary. In this way, the multiplier 9 outputs a luminance signal represented by a 10-bit digital signal.

On the other hand, the digital signal of the chroma signal C is selectively latched by the latch circuit 8 side, and is added to the digital signal output from the multiplier 9 in the adder 10.
In the adder 10, the chroma signal digital value C1 and the luminance signal digital value Y1 are added at a certain sampling time t1, and the previous chroma signal digital value C1 and the next luminance signal digital value Y2 are added at the next sampling time t2. At the next sampling time t3, the next chroma signal digital value C2 and the previous luminance signal digital value Y2 are added, and so on.

Here, the digital value of the chroma signal C is 8 bits (the maximum value is 255 in decimal), and the luminance signal Y
Has a digital value of 10 bits (the maximum value is 76 in decimal).
5), and when these are added, the maximum decimal value is 1020. This can be represented by 10 bits in binary (the maximum value is 1023 in decimal). In this way, the adder 10 outputs a decimal digital signal, which is latched by the latch circuit 11 and the output terminal 1
Output to 2.

Thus, from the output terminal 12 to the input terminal 1
A 10-bit digital signal obtained by A / D converting the composite video signal input to is output. The luminance signal Y and the chroma signal C represented by the digital signal are signals having 8-bit resolution. Since the 8-bit parallel comparison type A / D converter 6 is used internally to obtain this digital signal, this conversion can be realized at high speed.

In the embodiment described above, the digital value of the luminance signal is tripled by the multiplier 9 and the digital value of the chroma signal is left unchanged, but the former is multiplied by 5 and the latter is multiplied by 3. Processing can also be performed. At this time, the number of bits of the digital signal obtained at the output terminal 12 becomes larger than 10 bits.

[0019]

As described above, according to the present invention, even if an A / D converter having a low bit output is used, high speed and high bit output can be performed without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an A / D conversion circuit according to an embodiment of the present invention.

[Explanation of symbols]

1: input terminal, 2: signal separation circuit, 3: 4: sample hold circuit, 5: signal switching circuit, 6: A / D converter,
7, 8: (first) latch circuit, 9: multiplier, 10: adder, 11: (second) latch circuit, 12: output terminal.

Claims (2)

[Claims] 1. A signal separation circuit for separating each signal component from an input signal having M signal components, and M sample and hold circuits for sampling and holding each signal separated by the signal separation circuit, An N-bit A / D converter, a signal switching circuit that selectively switches the outputs of the M sample and hold circuits and outputs the signals to the A / D converter, and an output signal of the A / D converter Of the M number of N-bit first latch circuits for latching the signal in accordance with the switching timing of the signal switching circuit, and the output signals of the M number of N-bit first latch circuits are set to different magnifications of 1 or more. Of M multipliers for multiplying by, the N + α-bit adder for adding the output signals of the M multipliers, and the N + α-bit second latch circuit for latching the output signal of the adder. A / characterized by Conversion circuit. 2. The input signal is a composite video signal having a luminance signal and a chroma signal and M = 2, and the multiplication factor of a multiplier for multiplying the digital signal of the luminance signal is multiplied by the digital signal of the chroma signal. The A / D conversion circuit according to claim 1, wherein the multiplication factor is larger than that of the multiplier.