JPH08321526A - Chip carrier and its manufacture - Google Patents
Chip carrier and its manufactureInfo
- Publication number
- JPH08321526A JPH08321526A JP7128048A JP12804895A JPH08321526A JP H08321526 A JPH08321526 A JP H08321526A JP 7128048 A JP7128048 A JP 7128048A JP 12804895 A JP12804895 A JP 12804895A JP H08321526 A JPH08321526 A JP H08321526A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- tape
- bga
- bumps
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＴＣＰ（Ｔａｐｅ Ｃ
ａｒｒｉｅｒ Ｐａｃｋａｇｅ）型のチップキャリアに
関し、特にＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）
構造のチップキャリア及びその製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to TCP (Tape C
Arranger package) type chip carrier, especially BGA (Ball Grid Array)
The present invention relates to a structured chip carrier and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】半導体技術は、ＯＡ・民生機器の多機能
・高性能化と共に軽薄短小化の要求にともない、半導体
素子の多ピン化・小型化への要求が高まっている。例え
ば、プラスチックＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃ
ｋａｇｅ）型の半導体装置では、多ピン小型化にともな
いプリント基板実装の接続ピッチも０．６５から０．５
mmピッチへと縮小され、すでに０．４mmピッチで２５０
ピン以上が製品化されている。2. Description of the Related Art In semiconductor technology, demands for multi-pins and miniaturization of semiconductor elements are increasing along with the demands for OA and consumer equipment to be multifunctional and high-performance and to be light, thin and short. For example, plastic QFP (Quad Flat Pac)
In the case of the (kage) type semiconductor device, the connection pitch of the printed circuit board mounting is 0.65 to 0.5 as the number of pins is reduced.
Reduced to mm pitch, already 0.4 mm pitch 250
More than pins have been commercialized.
【０００３】しかし、狭ピッチ・多ピンのＱＦＰの実装
は、リードピッチの縮小と共にリード幅が狭くなるため
に、従来の実装装置では困難となり、精度の高い実装装
置が必要となってきている。また、実装時のリード変形
やプリント基板の半田電極形成が困難になるという課題
がある。However, it is difficult to mount a narrow-pitch, multi-pin QFP with a conventional mounting device because the lead width is narrowed as the lead pitch is reduced, and a highly accurate mounting device is required. Further, there is a problem that it becomes difficult to deform the leads during mounting and to form solder electrodes on the printed circuit board.
【０００４】このような課題を解決するため、実装性の
優れたＢＧＡ（Ｂａｌｌ ＧｒｉｄＡｒｒａｙ）が提案
されている。図４は、従来のハンダバンプを用いたＢＧ
Ａ構造の半導体装置を示す断面図である。同図におい
て、１０は半導体素子、１１はＡｌ電極、１３は封止樹
脂、３１はＡｕワイヤ、３２はハンダバンプ、３３はス
ルホール、３４は基板、３５は接着剤、３６は配線リー
ドである。In order to solve such a problem, a BGA (Ball Grid Array) having excellent mountability has been proposed. FIG. 4 shows a BG using a conventional solder bump.
It is sectional drawing which shows the semiconductor device of A structure. In the figure, 10 is a semiconductor element, 11 is an Al electrode, 13 is a sealing resin, 31 is an Au wire, 32 is a solder bump, 33 is a through hole, 34 is a substrate, 35 is an adhesive, and 36 is a wiring lead.
【０００５】同図に示すように従来のＢＧＡ構造の半導
体装置は、基板３４に接着剤３５で固定された半導体素
子１０を封止樹脂１３でパッケージングされた構成にな
っている。基板３４は、上面に配線リード３６と裏面に
ハンダバンプ３２が格子状に形成され、スルホール３３
で電気的に接続されている。基板３４と半導体素子１０
の電気的接続は、半導体素子１０のＡｌ電極１１と基板
３４の配線リード３６をＡｕワイヤ３１でボンディング
されている。As shown in the figure, a conventional semiconductor device having a BGA structure has a structure in which a semiconductor element 10 fixed to a substrate 34 with an adhesive 35 is packaged with a sealing resin 13. The substrate 34 has the wiring leads 36 on the upper surface and the solder bumps 32 on the back surface in a grid pattern.
It is electrically connected with. Substrate 34 and semiconductor device 10
For the electrical connection, the Al electrode 11 of the semiconductor element 10 and the wiring lead 36 of the substrate 34 are bonded by the Au wire 31.
【０００６】ＢＧＡの基板には、ガラスエポキシ基板や
セラミック基板が使用されているが生産性を考慮したＴ
ＡＢテープを用いたＴＡＢ−ＢＧＡも採用されている。Although a glass epoxy substrate or a ceramic substrate is used as the BGA substrate, T in consideration of productivity
TAB-BGA using AB tape is also adopted.
【０００７】[0007]
【発明が解決しようとする課題】一般にＢＧＡのバンプ
形成方法は、半田ペーストを用いたスクリーン印刷法や
電解メッキ法、半田ボール法で行われている。スクリー
ン印刷法は、簡単な装置で量産性の優れたバンプ形成方
法であるが、バンプ高さバラツキが大きく実装時に接続
不良が発生し信頼性に問題がある。電解メッキ法では、
高価な露光装置やメッキ装置等の装備が必要となりコス
トアップになるばかりでなく、パターンニングのための
リソグラフィ工程やメッキ工程が必要になるためバンプ
形成工程も長くなるという課題がある。Generally, a BGA bump forming method is performed by a screen printing method using a solder paste, an electrolytic plating method, or a solder ball method. The screen printing method is a bump forming method that is simple and can be easily mass-produced. However, there is a problem in reliability that bump height variation is large and connection failure occurs during mounting. In the electroplating method,
There is a problem that not only equipment such as an expensive exposure device and a plating device is required to increase the cost, but also a lithographic process and a plating process for patterning are required, so that a bump forming process becomes long.
【０００８】また、半田ボール法は、球状の半田ボール
をプリント基板の裏面の電極にフラックスを用いて、溶
融固着する方法であるが、半田ボールのコストが高く、
ハンドリングが困難のため量産に適さない方法である。Further, the solder ball method is a method of melting and fixing a spherical solder ball to an electrode on the back surface of a printed circuit board by using a flux, but the cost of the solder ball is high.
This method is not suitable for mass production because it is difficult to handle.
【０００９】本発明の目的はこのような課題を解決し、
低コストで生産性が高く、バンプ高さのバラツキが小さ
く高信頼性接続が可能なＢＧＡ構造の半導体装置を提供
することにある。The object of the present invention is to solve these problems.
It is an object of the present invention to provide a semiconductor device having a BGA structure that is low in cost, high in productivity, has a small variation in bump height, and enables highly reliable connection.
【００１０】[0010]
【課題を解決するための手段】本発明のチップキャリア
は、基板となる可塑性樹脂テープにバンプをアレイ状に
形成するＴ−ＢＧＡ（Ｔａｐｅ−Ｂａｌｌ Ｇｒｉｄ
Ａｒｒａｙ）型のチップキャリアにおいて、前記バンプ
は前記可塑性樹脂テープ上の電極パットを突出成形した
ものであることを特徴とする。The chip carrier of the present invention is a T-BGA (Tape-Ball Grid) in which bumps are formed in an array on a plastic resin tape serving as a substrate.
An array type chip carrier is characterized in that the bump is formed by projecting an electrode pad on the plastic resin tape.
【００１１】本発明の半導体装置は、基板となる可塑性
樹脂テープにバンプをアレイ状に形成するＴ−ＢＧＡ
（Ｔａｐｅ−Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型のチ
ップキャリアに搭載された半導体装置において、前記バ
ンプは前記可塑性樹脂テープ上の電極パットを突出成形
したものであることを特徴とする。The semiconductor device of the present invention is a T-BGA in which bumps are formed in an array on a plastic resin tape serving as a substrate.
In a semiconductor device mounted on a (Tape-Ball Grid Array) type chip carrier, the bumps are formed by projecting an electrode pad on the plastic resin tape.
【００１２】本発明の半導体装置は、前記突出成形部が
半田を被覆していることを特徴とする。The semiconductor device of the present invention is characterized in that the protruding molding portion covers the solder.
【００１３】本発明のチップキャリアの製造方法は基板
となる可塑性樹脂テープにバンプをアレイ状に形成する
Ｔ−ＢＧＡ（Ｔａｐｅ−Ｂａｌｌ Ｇｒｉｄ Ａｒｒａ
ｙ）型のチップキャリアの製造方法において、前記バン
プは前記可塑性樹脂テープ上の電極パットの裏面からプ
レス加工を行い塑性変形により突出成形することを特徴
とする。The method of manufacturing a chip carrier of the present invention is a T-BGA (Tape-Ball Grid Arra) in which bumps are formed in an array on a plastic resin tape serving as a substrate.
The y) type chip carrier manufacturing method is characterized in that the bumps are formed by projection from the back surface of the electrode pad on the plastic resin tape by pressing to perform plastic deformation.
【００１４】[0014]
【作用】本発明のＴ−ＢＧＡ型のチップキャリアのバン
プ形成は、電極パッド配列と一致する凸部と凹部を備え
た上型と下型を用いてプレス加工で一括成形を行うこと
により、大きさにバラツキの少ないバンプを一度に多数
作ることができ、複雑な工程が単純化され、かつ高価な
設備が不要になり生産性の向上と低コスト化が可能とな
った。さらに、型精度を制御することでバンプ高さバラ
ツキを小さくすることができ、外部基板との信頼性の高
い接続が可能となった。また、外部基板との接続は、プ
レス加工で突出した電極パッドのバンプに酸化防止用に
被覆した半田を溶融させて、従来のフリップチップ実装
で行われているセルフアライメント方式で行う。従っ
て、バンプ形成のための特別な材料を必要とせず低コス
トの半導体装置が得られる。The bumps of the T-BGA type chip carrier according to the present invention are formed by pressing the upper die and the lower die having the convex portions and the concave portions corresponding to the arrangement of the electrode pads in a batch process. In addition, a large number of bumps with less variation can be created at one time, complicated processes are simplified, expensive equipment is not required, and productivity can be improved and cost can be reduced. Further, by controlling the mold accuracy, it is possible to reduce the bump height variation, and it is possible to achieve highly reliable connection with an external substrate. In addition, the connection with the external substrate is performed by a self-alignment method that is performed by conventional flip-chip mounting by melting the solder that covers the bumps of the electrode pads that are projected by pressing to prevent oxidation. Therefore, a low-cost semiconductor device can be obtained without requiring a special material for bump formation.
【００１５】[0015]
【実施例】以下、本発明の実施例について図面を用いて
詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
【００１６】図１は本発明の半導体装置を示す概略図で
ある。図２は、本発明の半導体装置のバンプ形成方法で
ある。FIG. 1 is a schematic diagram showing a semiconductor device of the present invention. FIG. 2 shows a bump forming method for a semiconductor device according to the present invention.
【００１７】図において、１はＴＡＢテープ、２はテー
プキャリア、３はデバイスホール、４はインナーリー
ド、５はプレスバンプ、６は電極パッド、７はホール、
８はバンプ中空部、９はスプロケットホール、１０は半
導体素子、１１はＡｌ電極、１２はＡｕバンプ、１３は
封止樹脂、２１は上型、２２は凸部、２３は下型、２４
は凹部、２５は位置合せピンである。In the figure, 1 is a TAB tape, 2 is a tape carrier, 3 is a device hole, 4 is an inner lead, 5 is a press bump, 6 is an electrode pad, 7 is a hole,
Reference numeral 8 is a hollow portion of the bump, 9 is a sprocket hole, 10 is a semiconductor element, 11 is an Al electrode, 12 is an Au bump, 13 is a sealing resin, 21 is an upper die, 22 is a convex portion, 23 is a lower die, 24
Is a concave portion, and 25 is an alignment pin.
【００１８】本発明のＴＡＢ−ＢＧＡ型チップキャリア
の構造は、図１に示すように半導体素子１０のＡｌ電極
１１に形成されたＡｕバンプ１２とＴＡＢテープ１のＳ
ｎコートされたインナーリード４が熱圧着あるいは超音
波併用熱圧着で接続され、テープキャリア２のホール７
上にＰｂ／Ｓｎコートされた電極パッド６をプレス加工
によりプレスバンプ５が形成されている。さらに、半導
体素子１０とＴＡＢテープ１は、プレスバンプ５の突出
部が露出するように封止樹脂１３に埋め込まれている。As shown in FIG. 1, the structure of the TAB-BGA type chip carrier of the present invention is such that the Au bump 12 formed on the Al electrode 11 of the semiconductor element 10 and the S of the TAB tape 1 are formed.
The n-coated inner lead 4 is connected by thermocompression bonding or ultrasonic thermocompression bonding, and the tape carrier 2 has a hole 7
Pressed bumps 5 are formed by pressing the Pb / Sn-coated electrode pads 6 on top. Further, the semiconductor element 10 and the TAB tape 1 are embedded in the sealing resin 13 so that the protruding portions of the press bumps 5 are exposed.
【００１９】本発明に使用したＴＡＢテープは、図３に
示すように例えば厚さ１００〜１２５μm 、幅が３５mm
のポリイミド製の長尺のテープキャリア２に半導体素子
を搭載するデバイスホール３とプレスバンプの形成を容
易にするための例えば直径５００μm 、配列ピッチ１．
２５mmで格子状に配列されたホール７が形成されてい
る。さらに、テープキャリア２上には、デバイスホール
３側に突出した例えば幅６０μm 、配列ピッチ１００μ
m のインナーリード４とホール７を覆うように電極パッ
ド６が形成されている。テープキャリア２上のインナー
リード４とバンプ電極５を含む配線パターンは、あらか
じめ例えば３５μm のＣｕ薄膜をテープキャリア２に接
着後、エッチングで形成している。また、インナーリー
ド４と電極パッド６のメッキ方法は、無電解メッキによ
り例えば厚さ０．５μm のＳｎメッキを行い、次にイン
ナーリード４をレジストで被覆し、さらに、電極パッド
６上に無電解メッキで例えば厚さ０．７５μm のＰｂメ
ッキを行う。従って、電極パッド６には、溶融時にＰ
ｂ：Ｓｎ＝６：４の共晶半田が形成される。以上のメッ
キプロセス後インナーリード４のレジストは、リムーバ
によって剥離される。The TAB tape used in the present invention has, for example, a thickness of 100 to 125 μm and a width of 35 mm as shown in FIG.
For facilitating the formation of the device holes 3 for mounting the semiconductor elements and the press bumps on the long tape carrier 2 made of polyimide, for example, the diameter is 500 μm, and the arrangement pitch is 1.
The holes 7 are arranged in a grid pattern of 25 mm. Furthermore, on the tape carrier 2, for example, a width of 60 μm protruding toward the device hole 3 side, an arrangement pitch of 100 μm
Electrode pads 6 are formed so as to cover m inner leads 4 and holes 7. The wiring pattern including the inner leads 4 and the bump electrodes 5 on the tape carrier 2 is formed by etching, after previously adhering a Cu thin film of, for example, 35 μm to the tape carrier 2. The inner leads 4 and the electrode pads 6 are plated by electroless plating, for example, Sn plating having a thickness of 0.5 μm, and then the inner leads 4 are covered with a resist. As the plating, for example, Pb plating having a thickness of 0.75 μm is performed. Therefore, when the electrode pad 6 is melted, P
A eutectic solder of b: Sn = 6: 4 is formed. After the above plating process, the resist of the inner lead 4 is removed by the remover.
【００２０】電極パッド上にはテープキャリア２の幅方
向の両端には、あらかじめテープ位置決め用と搬送用に
等ピッチに規格化されたスプロケットホール９が形成さ
れている。ＴＡＢテープ１と半導体素子１０との接続方
法は、インナーリード４と半導体素子１０のＡｕバンプ
１２を超音波併用の熱圧着で逐次接合によるシングルポ
イントボンディング方法で行った。On both ends of the tape carrier 2 in the width direction of the electrode pad, sprocket holes 9 are standardized at equal pitches for tape positioning and transportation. The connection method between the TAB tape 1 and the semiconductor element 10 was a single point bonding method in which the inner leads 4 and the Au bumps 12 of the semiconductor element 10 were sequentially joined by thermocompression bonding using ultrasonic waves.
【００２１】本発明のＴＡＢテープへのプレスバンプの
形成方法及びＴＡＢ−ＢＧＡの組立方法を詳細に説明す
る。まず、プレスバンプ形成方法は、図２に示すように
プレスバンプ成形位置と一致する位置に形成された。上
型２１の凸部２２と下型２３の凹部２４によってプレス
加工する。まず、下型２３の位置合せピン２５をＴＡＢ
テープ１のスプロケットホール９に挿入し、位置決めを
行う。次に、あらかじめ下型２３と位置合わせされてい
る上型２１をＴＡＢテープ１のホール７側より下降させ
る。上型２１には、凸部２２がＴＡＢテープ１に接触
後、１０Ｋｇｆの荷重を印加する。次に、上型２１を上
昇させ、下型２３の位置合せピン２５よりＴＡＢテープ
１のスプロケットホール９を外す。以上の工程により、
ホール７側にはバンプ中空部８が、電極パッド６側には
プレスバンプ４が形成される。この時の、上型２１の凸
部２２と下型２３の凹部２４の形状及び寸法は、凸部２
２では直径４５０μm 、長さ１mmの円柱形状で、凹部２
３では直径５００μm の半球上の窪みになっている。バ
ンプ形状は、凹部２４の窪み形状がそのまま転写される
ためにバンプ高さ精度や形状に影響する。従って、金型
を十分な精度で加工すれば、バンプ高さのばらつきの無
い安定したバンプ形状が得られる。The method of forming the press bumps on the TAB tape of the present invention and the method of assembling the TAB-BGA will be described in detail. First, in the press bump formation method, as shown in FIG. 2, the press bump was formed at a position corresponding to the press bump forming position. The convex portion 22 of the upper mold 21 and the concave portion 24 of the lower mold 23 are pressed. First, align the alignment pin 25 of the lower mold 23 with TAB.
The tape 1 is inserted into the sprocket hole 9 and positioned. Next, the upper mold 21, which is previously aligned with the lower mold 23, is lowered from the hole 7 side of the TAB tape 1. A load of 10 Kgf is applied to the upper mold 21 after the protrusion 22 contacts the TAB tape 1. Next, the upper die 21 is raised, and the sprocket hole 9 of the TAB tape 1 is removed from the alignment pin 25 of the lower die 23. By the above process,
The bump hollow portion 8 is formed on the hole 7 side, and the press bump 4 is formed on the electrode pad 6 side. At this time, the shapes and dimensions of the convex portion 22 of the upper mold 21 and the concave portion 24 of the lower mold 23 are the same as those of the convex portion 2
2 has a cylindrical shape with a diameter of 450 μm and a length of 1 mm.
In No. 3, it is a depression on a hemisphere with a diameter of 500 μm. The bump shape affects the bump height accuracy and shape because the dent shape of the recess 24 is directly transferred. Therefore, if the die is processed with sufficient accuracy, a stable bump shape without variation in bump height can be obtained.
【００２２】ＴＡＢ−ＢＧＡの組立方法は、図示してい
ないがＴＡＢテープへの半導体素子の実装とプレスバン
プ形成及び電気的動作の確認後、パッケージ外形と同形
状の金型にＴＡＢテープを固定し封止樹脂を流し込み加
熱硬化させる。以上の工程により、本発明の構造のＴＡ
Ｂ−ＢＧＡを製作した。Although not shown, the TAB-BGA is assembled by mounting the semiconductor element on the TAB tape, forming the press bumps, and confirming the electrical operation, and then fixing the TAB tape to a mold having the same shape as the package outline. The sealing resin is poured and cured by heating. Through the above steps, the TA of the structure of the present invention
B-BGA was manufactured.
【００２３】次に、ＴＡＢ−ＢＧＡの基板への実装方法
は、基板を２００℃に加熱し、あらかじめフラックスを
塗布したＴＡＢ−ＢＧＡのプレスバンプ５と基板の電極
を重なり合うように位置合わせし、基板からの熱によっ
て溶融接合を行う。この時のプレスバンプ５と基板電極
との位置合わせは、半田溶融時のセルフアライメント効
果で自動的に位置調整されるため、位置合わせ精度が緩
和される。Next, in the method of mounting the TAB-BGA on the substrate, the substrate is heated to 200 ° C., and the press bumps 5 of the TAB-BGA coated with the flux are aligned with the electrodes of the substrate so as to overlap each other. Fusion bonding is performed by heat from the. Since the position of the press bump 5 and the substrate electrode at this time is automatically adjusted by the self-alignment effect when the solder is melted, the alignment accuracy is relaxed.
【００２４】さらに、ＴＡＢ−ＢＧＡをプリント基板に
搭載後、環境試験として温湿度サイクル試験（ＭＩＬ−
ＳＴＤ−８８３Ｂの試験方法に準ずる）を行った。環境
条件は、温度が２５±２℃〜６５±２℃、湿度が９０〜
９８％、サイクル数が１０サイクル（２４Ｈｒ／サイク
ル）で行った。ＴＡＢ−ＢＧＡの電気的特性は、本試験
前後で変化が生じなかった。Further, after mounting the TAB-BGA on the printed circuit board, a temperature / humidity cycle test (MIL-
According to the test method of STD-883B). Environmental conditions are temperature 25 ± 2 ℃ ~ 65 ± 2 ℃, humidity 90 ~
The cycle was 98% and the number of cycles was 10 (24 Hr / cycle). The electrical characteristics of TAB-BGA did not change before and after this test.
【００２５】以上のように本発明のＴＡＢ−ＢＧＡで
は、簡易なバンプ形成方法で従来のＢＧＡと同等の性能
が得られ、低価格のＢＧＡが実現できた。As described above, in the TAB-BGA of the present invention, the same performance as that of the conventional BGA can be obtained by a simple bump forming method, and a low-cost BGA can be realized.
【００２６】また本実施例ではチップとして半導体素子
を用いたがこれに限られるものではない。Further, although the semiconductor element is used as the chip in this embodiment, it is not limited to this.
【００２７】[0027]
【発明の効果】以上説明したように、本発明の半導体装
置のバンプ形成は、機械的なプレス加工を用いて一括バ
ンプ形成することにより、複雑な工程が単純化され、高
価な設備が不要になり、生産性の向上と低コスト化が可
能となった。さらに、バンプ形状や高さバラツキは、型
形状がバンプ形状に正確に転写されるため、型形状で制
御することができる。従って、同形状の高さバラツキの
小さいバンプにより、外部基板との信頼性の高い接続が
可能となった。また、外部基板との接続は、あらかじめ
電極パッドにメッキコートされている酸化防止用の半田
を溶融させて、従来のフリップチップ実装で行われてい
るセルフアライメント方式で行う。従って、バンプ形成
のための特別な材料を必要とせず低コストの半導体装置
が得られる等の効果がある。As described above, in the bump formation of the semiconductor device of the present invention, the complex steps are simplified by forming the bumps collectively by mechanical press working, and the expensive equipment is not required. It has become possible to improve productivity and reduce costs. Further, the bump shape and height variation can be controlled by the mold shape because the mold shape is accurately transferred to the bump shape. Therefore, the bumps having the same shape and small variations in height enable highly reliable connection with the external substrate. In addition, the connection with the external substrate is performed by the self-alignment method that is performed by the conventional flip-chip mounting by melting the anti-oxidizing solder that is plated on the electrode pad in advance. Therefore, there is an effect that a low-cost semiconductor device can be obtained without requiring a special material for bump formation.
【図１】本発明のＢＧＡ構造の半導体装置を示す断面図
である。FIG. 1 is a cross-sectional view showing a semiconductor device having a BGA structure of the present invention.
【図２】本発明のＢＧＡ構造の半導体装置のバンプ形成
方法を示す断面図である。FIG. 2 is a cross-sectional view showing a bump forming method of a semiconductor device having a BGA structure of the present invention.
【図３】本発明に使用したＴＡＢテープを示す上面図と
Ａ−Ａ′側断面図である。FIG. 3 is a top view showing a TAB tape used in the present invention and a sectional view taken along the line AA ′.
【図４】従来のハンダバンプを用いたＢＧＡ構造の半導
体装置を示す断面図である。FIG. 4 is a cross-sectional view showing a conventional semiconductor device having a BGA structure using solder bumps.
１ ＴＡＢテープ ２ テープキャリア ３ デバイスホール ４ インナーリード ５ プレスバンプ ６ 電極パッド ７ ホール ８ バンプ中空部 ９ スプロケットホール １０ 半導体素子 １１ Ａｌ電極 １２ Ａｕバンプ １３ 封止樹脂 ２１ 上型 ２２ 凸部 ２３ 下型 ２４ 凹部 ２５ 位置合せピン ３１ Ａｕワイヤ ３２ ハンダバンプ ３３ スルホール ３４ 基板 ３５ 接着剤 ３６ 配線リード 1 TAB tape 2 tape carrier 3 device hole 4 inner lead 5 press bump 6 electrode pad 7 hole 8 bump hollow part 9 sprocket hole 10 semiconductor element 11 Al electrode 12 Au bump 13 sealing resin 21 upper mold 22 convex part 23 lower mold 24 Recessed portion 25 Alignment pin 31 Au wire 32 Solder bump 33 Through hole 34 Substrate 35 Adhesive 36 Wiring lead
Claims (4)
レイ状に形成するＴ−ＢＧＡ（Ｔａｐｅ−Ｂａｌｌ Ｇ
ｒｉｄ Ａｒｒａｙ）型のチップキャリアにおいて、前
記バンプは前記可塑性樹脂テープ上の電極パットを突出
成形したものであることを特徴とするチップキャリア。1. A T-BGA (Tape-Ball G) in which bumps are formed in an array on a plastic resin tape serving as a substrate.
In the chip carrier of the "rid Array" type, the bumps are formed by projecting the electrode pads on the plastic resin tape.
レイ状に形成するＴ−ＢＧＡ（Ｔａｐｅ−Ｂａｌｌ Ｇ
ｒｉｄ Ａｒｒａｙ）型のチップキャリアに搭載された
半導体装置において、前記バンプは前記可塑性樹脂テー
プ上の電極パットを突出成形したものであることを特徴
とする半導体装置。2. A T-BGA (Tape-Ball G) in which bumps are formed in an array on a plastic resin tape serving as a substrate.
A semiconductor device mounted on a chip array carrier of a rigid array type, wherein the bump is formed by projecting an electrode pad on the plastic resin tape.
を特徴とする請求項１または２記載の半導体装置。3. The semiconductor device according to claim 1, wherein the protruding molding portion covers the solder.
レイ状に形成するＴ−ＢＧＡ（Ｔａｐｅ−Ｂａｌｌ Ｇ
ｒｉｄ Ａｒｒａｙ）型のチップキャリアの製造方法に
おいて、前記バンプは前記可塑性樹脂テープ上の電極パ
ットの裏面からプレス加工を行い塑性変形により突出成
形することを特徴とするチップキャリアの製造方法。4. A T-BGA (Tape-Ball G) in which bumps are formed in an array on a plastic resin tape serving as a substrate.
In the method of manufacturing a chip carrier of a grid array type, the bumps are formed by protrusion from the back surface of the electrode pad on the plastic resin tape by press working and plastic deformation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7128048A JPH08321526A (en) | 1995-05-26 | 1995-05-26 | Chip carrier and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7128048A JPH08321526A (en) | 1995-05-26 | 1995-05-26 | Chip carrier and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08321526A true JPH08321526A (en) | 1996-12-03 |
Family
ID=14975220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7128048A Pending JPH08321526A (en) | 1995-05-26 | 1995-05-26 | Chip carrier and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08321526A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5081064A (en) * | 1973-11-15 | 1975-07-01 | ||
| JPH03262141A (en) * | 1990-03-12 | 1991-11-21 | Nippondenso Co Ltd | Lead with bump |
-
1995
- 1995-05-26 JP JP7128048A patent/JPH08321526A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5081064A (en) * | 1973-11-15 | 1975-07-01 | ||
| JPH03262141A (en) * | 1990-03-12 | 1991-11-21 | Nippondenso Co Ltd | Lead with bump |
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