JPH08321514A - Manufacture of gaas field effect transistor - Google Patents

Abstract

PURPOSE: To reduce a source resistance and increase a drain withstand voltage by forming a side wall by anisotropic etching after slanting a substrate and depositing an insulating film in such a manner that the film thickness of the side wall at the drain electrode side becomes larger than the film thickness of the side wall at the source electrode side. CONSTITUTION: An operation layer 3 is formed by ion implantation at a predetermined portion of a substrate 1, and a gate metal is deposited on the substrate 1 and processed to a predetermined length, and a gate electrode 4 is formed. Next, reactive ion etching is performed, and side walls 5, 5' comprising insulating films are formed on both the sides of the gate electrode 4. At this time, the deposition of the insulating film 5 is performed by slanting the substrate 1 relative to an SiO2 irradiation source, and the film of the side wall 5 at the drain side is formed thicker than the film thickness of the side wall 5' at the source side. By doing this, the withstand voltage of the drain can be improved and the decrease in source resistance can be made smaller so that the mutual conductance can be enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a self-aligned manufacturing method of a GaAs field effect transistor by an ion implantation method.

[0002]

2. Description of the Related Art A field-effect transistor (Metal-) formed by ion-implanting a donor impurity into a semi-insulating GaAs substrate.
Semiconductor Field Effect Transistor; "MES
"FET") is widely applied not only as a high frequency communication element but also as a digital IC.

Generally, a GaAs field effect transistor (abbreviated as "MESFET") has an LDD (Lightly Doped Drain) structure in order to improve FET characteristics.

In this LDD structure, a gate electrode is formed after an active layer is formed by ion implantation, and a medium concentration (n ') region is formed on both sides of the gate electrode by ion implantation. Then, a predetermined region of the insulating film is opened, and a high concentration (n ⁺ ) region is formed by ion implantation.

By inserting an n'layer having a carrier concentration and an intermediate depth between the operation layer and the n ⁺ layer between the gate electrode and the n ⁺ layer, the MESFET having a high source conductance and a high transconductance (g _m ) is inserted. Is obtained.

In particular, an ME with an LDD structure which becomes a high output element
High breakdown voltage characteristics are required for SFETs. For this reason, an asymmetric LDD structure in which the distance to the n ⁺ region on the drain side with respect to the gate electrode is made larger than the distance to the n ⁺ region on the source side is adopted. Conventionally, for example, as shown in FIGS. 6 and 7. Different forming methods have been used.

That is, through the mask 13, the semi-insulating Ga
A donor such as Si is introduced into the As substrate 12 by ion implantation to form an n-type active layer 14 (see FIG. 6A). Then, a refractory metal compound such as WSi ₂ (tungsten silicide) is formed on the active layer 14. Or CVD the gate electrode 15 made of alloy
(Chemical vapor deposition) or sputter deposition (see FIG. 6B), and a resist mask 16 is applied (see FIG. 6).
(See (c)), donor impurities such as Si are ion-implanted into regions 17 (high-concentration layers) on both sides of the gate electrode 15 through the patterned openings, and masks on both sides of the gate electrode are removed. A donor impurity such as Si is ion-implanted by using 15 as a mask to form a medium concentration layer 18 on both sides of the gate electrode 15.
Are formed (see FIG. 6E).

Further, after the insulating film 19 is deposited and heat-treated to activate the ion-implanted region (see FIG. 7 (f)), a predetermined portion of the insulating film 9 is opened and ohmic metal is covered by a lift-off method or the like. After the deposition, heat treatment is performed to form the source electrode 20 and the drain electrode 21 to form the MESFET (see FIG. 7G). As shown in FIG. 7G, an asymmetric LD in which the distance from the gate electrode 15 to the high concentration layer 17 on the drain side is larger than the distance to the high concentration layer on the source side.
It has a D structure.

[0009]

However, the above-mentioned method for forming an asymmetric LDD structure requires a large number of exposure steps. In particular, in the formation of the medium-concentration region after the gate electrode is formed, there is a problem in uniformity and reproducibility due to misalignment, and the degree of freedom in dimension setting such as shortening the gate length has been hindered.

Therefore, the present invention solves these problems, has a small source resistance and a high drain breakdown voltage.
It is an object of the present invention to provide a manufacturing method for forming an As field effect transistor with high uniformity and reproducibility.

[0011]

In order to achieve the above object, the present invention is an anisotropic method in which a gate electrode is formed on a semi-insulating GaAs substrate and then an insulating film is deposited on the semi-insulating GaAs substrate. GaAs including a step of forming sidewalls made of the insulating film on both sides of the gate electrode by reactive etching
In the method of manufacturing a field effect transistor, after the insulating film is deposited by inclining the substrate so that the thickness of the side wall on the drain electrode side is larger than the thickness of the side wall on the source electrode side, A method for manufacturing a GaAs field effect transistor, characterized in that the sidewall is formed by the anisotropic etching.

In the present invention, anisotropic etching such as RIE is obliquely performed on the substrate so that the thickness of the side wall on the drain electrode side is larger than the thickness of the side wall on the source electrode side. You may do it.

[0013]

The operation and principle of the present invention will be described below.

According to the present invention, the semi-insulating GaAs substrate is tilted with respect to the ion irradiation direction, or the semi-insulating G is used.
This is to utilize the effect (shading effect) of forming a shadow between the source or drain contact regions by using the gate electrode by performing reactive ion etching (RIE) on the aAs substrate from an oblique direction. Due to this effect, according to the present invention as set forth in claim 1, a shadow is generated between the gate and the source region, and the ion forming the irradiated insulating film is thick between the gate and the drain, and on the other hand, between the gate and the source. Deposit thinly.
Further, according to the present invention described in claim 2, the gate-
A shadow is formed between the drain regions, and the side wall on the drain region side can be formed thicker than the side wall on the source region side in RIE.

According to the present invention, the n ⁺ region on the drain side is separated from the gate electrode in a self-aligned manner, the electric field concentration generated at the drain end of the gate electrode is relaxed, the drain breakdown voltage is improved, and the source by the n ⁺ region is formed. The mutual conductance g _m is improved by reducing the resistance of the resistor.

Further, according to the present invention, since the medium concentration region and the high concentration region are formed in a self-aligning manner, misalignment in the exposure process can be reduced, and the asymmetric LDD structure can be easily and reproducibly formed. The MESFET can be formed, and the manufacturing process can be simplified and the cost can be reduced.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

[0018]

Embodiment 1 An embodiment of the present invention will be described with reference to FIGS. 1 (a) to 2 (h) schematically show diagrams for explaining the present embodiment in the order of steps.

First, an operating layer 3 is formed on a predetermined portion of a semi-insulating GaAs substrate 1 by ion implantation (see FIG. 1A), and a gate metal such as WSi is deposited on the substrate 1 by a sputtering method. The gate electrode 4 is formed into a predetermined length (see FIG. 1B).

Next, for example, a silicon dioxide film SiO ₂ is deposited as the insulating film 5 on the substrate 1 by the sputtering method (see FIG. 1C). At this time, as shown in FIG. 5A, the substrate 1 is tilted with respect to the SiO ₂ irradiation source so that the film thickness of the drain side insulating film is larger than that of the source side insulating film. . That is, as shown in the enlarged view of FIG. 5B, the ions are accumulated from the direction oblique to the surface of the substrate 1 (see the arrow).

Next, reactive ion etching (RIE)
The side walls 5 made of an insulating film on both sides of the gate electrode 4,
5'is formed (see FIG. 1 (d)). At that time, as described above, due to the effect of the shape of the insulating film 5, the sidewall 5 on the drain side is formed.
Can be formed thicker than the film thickness of the side wall 5'on the source side.

Then, ion implantation is performed using the gate electrode 4 and the side walls 5 and 5'as a mask to form an n ⁺ (high concentration) layer 7 in the source and drain regions (see FIG. 1E).

Further, the side walls 5 and 5'are removed, and ion implantation is performed using the gate electrode 4 as a mask to form an n'layer 8 (see FIG. 2 (f)).

Next, the insulating film 9 is formed on the entire surface by thermal CVD.
For example, a silicon dioxide film SiO ₂ is deposited and heat treatment is performed to activate the ion implantation region (see FIG. 2G).

Next, a predetermined portion of the insulating film 9 is opened, an ohmic metal is deposited by a lift-off method, and a heat treatment is performed.
Forming the source electrode 10 and the drain electrode 11 to form the MES
An FET is formed (see FIG. 2 (h)).

[0026]

Second Embodiment A second embodiment of the present invention will be described with reference to FIGS. 3 (a) to 4 (h) schematically show diagrams for explaining the present embodiment in the order of steps.

An operating layer 3 is formed on a predetermined portion of the semi-insulating GaAs substrate 1 by ion implantation (see FIG. 3A), and then a gate metal, for example, WSi is deposited on the substrate 1 by a sputtering method, and then a predetermined layer is formed. Is processed to form the gate electrode 4 (see FIG. 3B).

Then, for example, a silicon dioxide film is deposited as the insulating film 5 on the substrate 1 by using the sputtering method (see FIG. 3C).

Next, reactive ion etching (RIE)
The side walls 5 made of an insulating film on both sides of the gate electrode 4,
5'is formed (see FIG. 3 (d)). At that time, RIE is performed in an oblique direction on the substrate 1 so that the insulating film on the drain side is formed thicker than that on the source side.
5'is formed. At this time, due to the shadow effect of the gate electrode 4, the film thickness of the side wall 5 on the drain side can be formed larger than that of the side wall 5'on the source side.

Next, ion implantation is performed using the gate electrode 4 and the side walls 5 and 5'as a mask to form an n ⁺ layer 7 in the source and drain regions (see FIG. 3E).

Further, the side walls 5 and 5'are removed, and ion implantation is performed using the gate electrode 4 as a mask to form an n'layer 8 (see FIG. 4 (f)).

Next, the insulating film 9 is formed on the entire surface by thermal CVD.
For example, a silicon dioxide film is deposited and heat treatment is performed to activate the ion implantation region (see FIG. 4G).

Then, a predetermined portion of the insulating film 9 is opened, an ohmic metal is deposited by a lift-off method, and a heat treatment is performed to form a source electrode 10 and a drain electrode 11, and ME is formed.
The SFET is formed (see FIG. 4 (h)).

[0034]

As described above, according to the present invention, the n ⁺ region on the drain side is separated from the gate electrode in a self-aligning manner.
This has the effect of alleviating the electric field concentration generated at the drain end of the gate electrode, improving the drain breakdown voltage, and improving the mutual conductance g _m by reducing the resistance of the source resistance due to the n ⁺ region.

Further, according to the present invention, since the medium-concentration region and the high-concentration region are formed in a self-aligning manner, misalignment in the exposure process can be reduced, and the MESFET having the asymmetric LDD structure can be easily and reproducibly provided. Can be formed, and it has the effect of simplifying the manufacturing process and achieving cost reduction.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an example of the present invention in the order of manufacturing steps.

FIG. 2 is a diagram for explaining one embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a diagram for explaining the second embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a diagram for explaining the manufacturing process in the order of processes according to the second embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating a method of depositing an insulating film in an example of the present invention.

FIG. 6 is a diagram for explaining a conventional method of manufacturing a GaAs MESFET in the order of steps.

FIG. 7 is a diagram for explaining a conventional GaAs MESFET manufacturing method in the order of steps.

[Explanation of symbols]

 1 semi-insulating GaAs substrate 2 mask 3 working layer 4 gate electrode 5 insulating film 6 mask 7 high concentration layer 8 medium concentration layer 9 insulating film 10 source electrode 11 drain electrode 12 semi-insulating GaAs substrate 13 mask 14 working layer 15 gate electrode 16 mask 17 high concentration layer 18 medium concentration layer 19 insulating film 20 source electrode 21 drain electrode

Claims (4)

[Claims] 1. A gate electrode is formed on a semi-insulating GaAs substrate, an insulating film is deposited on the semi-insulating GaAs substrate, and sidewalls made of the insulating film are formed on both sides of the gate electrode by anisotropic etching. In a method of manufacturing a GaAs field effect transistor including a step of forming the substrate, the substrate is tilted so that the thickness of the sidewall on the drain electrode side is larger than the thickness of the sidewall on the source electrode side. A method of manufacturing a GaAs field effect transistor, characterized in that after the deposition, the side wall is formed by the anisotropic etching. 2. A gate electrode is formed on a semi-insulating GaAs substrate, and then an insulating film is deposited on the semi-insulating GaAs substrate, and side walls made of the insulating film are formed on both sides of the gate electrode by anisotropic etching. GaA including the step of
s In the method of manufacturing a field effect transistor, anisotropic etching is performed on the substrate obliquely so that the thickness of the side wall on the drain electrode side is larger than the thickness of the side wall on the source electrode side. Characteristic Ga
Method for manufacturing As field effect transistor. 3. The method of manufacturing a GaAs field effect transistor according to claim 1, wherein the anisotropic etching is reactive ion etching. 4. The GaAs according to claim 1, wherein the substrate is tilted at a predetermined angle with respect to the ion irradiation direction and the insulating film is deposited on the substrate by a sputtering method.
Method for manufacturing field effect transistor.