JPH0831972A - Substrate for ic packaging - Google Patents

Abstract

PURPOSE:To achieve both a high-frequency electrical wiring function and a thermal diffusion function by allowing Si substrate to have a region where dielectric layers are laminated, a region where an electrical wiring region and the dielectric layer are not laminated, and an element mounting region. CONSTITUTION:A buffer consisting of a dielectric layer 2 is laminated on Si substrate 3 where a projecting part for mounting an IC substrate 4 is formed and a signal line 1a of an electrical wiring path (coplanar line) and a ground 1b of the coplanar line are formed on the dielectric layer 2. Further, the IC substrate 4 is provided on the coplanar line 1a via a solder bump 5. Especially, the Si substrate 3 is a region where the dielectric layer 2 is laminated, is an electrical wiring region where the coplanar line is provided and a region where the dielectric layer 2 is not laminated, and is provided with an element mounting region for directly mounting an IC element, thus achieving both a low-loss high-frequency electrical wiring function and a thermal diffusion function.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC mounting substrate on which a semiconductor element such as an integrated circuit (IC) applied to an electronic system such as an electronic device, a computer, an information processing system and a communication system is mounted. Is.

[0002]

2. Description of the Related Art In recent years, there has been a demand for an increase in information processing capacity as information processing speeds or communication speeds in information processing systems, communication systems, etc. have become higher and higher in performance. Therefore, ultra-high integration of silicon ICs has been attempted. On the other hand, development of a wiring technology for high-density mounting of them, an IC mounting substrate, and the like is also requested. The conditions required for this IC mounting substrate are (1) the dielectric loss (tan δ) is small in order to provide high-frequency wiring,
(2) Good heat dissipation, (3) Cheap and excellent productivity, and the like. Since the amount of heat generation increases as the speed of the IC element increases, the above conditions (1) and (2) tend to be particularly required along with the recent increase in the speed and performance of information processing. Therefore, conventionally, an alumina-based ceramic material has been mainly used as the IC mounting substrate material that satisfies the above conditions.

[0003]

However, the above-mentioned alumina-based ceramic material, and the substrate made of beryllia, sapphire, and silicon, which replaces it, have the following problems.

Table 1 shows the dielectric loss (tan) of various materials.
δ; loss tangent) and thermal conductivity K.

[0005]

[Table 1]

As is clear from this table, although alumina almost satisfies the above conditions, it has a drawback that the heat dissipation of (2) is small and the heat conductivity is not sufficient.
Therefore, when heat dissipation is an important factor, beryllia and sapphire, which have excellent heat dissipation, have been used. But,
These materials are expensive, and there is a problem in that they do not meet the demand side demand for lowering the price of products that has been conventionally demanded.

On the other hand, the silicon (Si) substrate has the above (1)
It is suitable for the conditions of (2) and (2), and particularly for the heat dissipation of the condition (2), the thermal conductivity is as large as three times that of alumina (see Table 1). Further, since the material of the highly integrated IC is the same silicon, the coefficient of thermal expansion is matched with that of the IC. Further, it has a track record of mass production as a substrate for semiconductors, and the process for forming an LSI has been well studied, and it would be a great advantage if Si can be used as a substrate for mounting ICs. However, since silicon is a semiconductor and its specific resistance is as small as 1 kΩ · cm at most, dielectric loss tan δ
Is as large as 0.005 (10 GHz) (Table 1), and there is a drawback that the above condition (1) is not satisfied, that is, there is a problem that a loss is large when the high frequency electric wiring is formed on the Si substrate.

Therefore, as described above, there is no known IC mounting board using a material having excellent electrical characteristics for high frequency wiring and an excellent heat dissipation function.

Therefore, an object of the present invention is to solve a problem that a low loss electric wiring for high frequency cannot be formed on a Si substrate, and to realize a new IC having excellent high frequency electric wiring function and heat dissipation function. It is to provide a mounting substrate.

[0010]

In order to solve the above problems, an IC mounting substrate according to the present invention has a Si substrate and a dielectric layer laminated at a predetermined position on the Si substrate. In the IC mounting substrate, the Si substrate is
An electric wiring region in which the dielectric layer is laminated and an electric wiring path is arranged; and a region in which the dielectric layer is not laminated and an element mounting region for directly mounting an IC device. Characterize.

Preferably, the electric wiring path is a coplanar line composed of a signal line and a ground, or a microstrip line composed of a signal line and a ground.

Preferably, the Si substrate has a concave portion in which the electric wiring region is provided and a convex portion in which an element mounting region is provided.

As the dielectric of the electric wiring part,
Insulators such as quartz glass and induced polymer materials can be used.

Further, it is possible to form a multilayer wiring which has already been established with copper polyimide or the like on these electric wiring portions. As a result, the range of application of the IC mounting substrate using this Si substrate can be expanded.

In addition, a Si substrate such as an alumina substrate is used.
A C mounting board can also be incorporated. As a result, in the part where heat dissipation is particularly required, the IC by this Si substrate
If the substrate for chemical mounting is used, the disadvantage of the alumina substrate which has already been put into practical use, which is inferior to the heat dissipation function, can be compensated, and the application range can be further expanded.

[0016]

In order to eliminate the influence of the Si substrate and obtain good high frequency characteristics, it is only necessary to insert a dielectric having a sufficient thickness between the electric wiring layer having the coplanar wiring and the Si substrate. , A well-known fact.

However, even if the IC element is mounted not on the surface of the Si substrate but on a thick dielectric, the IC element and the Si substrate do not come into thermal contact with each other, and the advantage that the heat dissipation of the Si substrate is excellent cannot be utilized. . Therefore, the Si substrate has hardly been used as an IC mounting substrate.

In the present invention, since the Si substrate is also used as the substrate for the low-loss high-frequency electric wiring, a dielectric layer is formed as a buffer layer in the electric wiring region of the Si substrate, and the coplanar is formed thereon. Forming an electrical wiring layer of wiring,
In the element mounting region of the Si substrate, the dielectric layer is removed, that is, the Si substrate is thermally exposed, and the IC element is mounted while thermally contacting the IC element and the Si substrate surface. As a result, both the low-loss high-frequency electric wiring function and the heat dissipation function can be realized.

Further, in the above example, a Si substrate having a concave portion and a convex portion may be used, and the concave portion may be used as an electric wiring region and the convex portion may be used as an element mounting region. Just like the low loss high frequency electric wiring function and heat dissipation function are satisfied.

Furthermore, a microstrip line can be used instead of the coplanar line in the above two examples. That is, a thin electrode layer serving as the ground of the microstrip line is formed in the electric wiring region of the Si substrate, a dielectric layer is formed on the entire surface thereof, and a signal line of the microstrip line is formed on the dielectric layer. In the element mounting region, the dielectric layer may be removed to expose the Si substrate thermally, and the IC element may be mounted while thermally contacting the surface. In this case as well, both the low-loss high-frequency electric wiring function and the heat dissipation function can be realized regardless of whether the Si substrate has a flat surface or a concave convex portion.

With such a structure, the Si substrate, which has a large high frequency loss and has hardly been used as an IC mounting substrate in the past, is used as an IC mounting substrate which has an excellent high frequency electric wiring function, is inexpensive, and has good heat dissipation. be able to.

[0022]

EXAMPLE An IC mounting board of the present invention is an IC mounting board in which an electric wiring region and an element mounting region are formed on a Si substrate, and the electric wiring region is provided on the Si substrate. And an electric wiring path made up of a signal line and a ground is disposed on the dielectric layer, and the element mounting area includes an IC element on the Si substrate without the dielectric layer. It consists of an area for direct mounting.

That is, in the high-frequency electric wiring, a buffer layer of a dielectric layer having a small dielectric loss (tan δ) is formed in the electric wiring area, and, for example, a coplanar line is formed on the buffer layer. It is possible to realize electric wiring with less influence and less high frequency loss. As for the element mounting region, an element such as an IC is mounted on a Si substrate having a high thermal conductivity while keeping thermal contact. For that I
The heat generated in C can be efficiently radiated through the Si substrate.

Further, using a Si substrate having irregularities, using a concave portion of the Si substrate as an electric wiring region, performing wiring similar to the above example, and using a convex portion of the Si substrate as an element mounting region, an IC element The same effect can be expected even if the same is installed.

A microstrip line may be used as the high frequency electric wiring. In this case, set the ground plane to Si
By placing it on the substrate, it is possible to prevent an electric field vector from penetrating into the Si substrate, so that a good high-frequency line that is not affected by the Si substrate can be realized.

With this structure, the Si substrate, which has a large high-frequency loss and has hardly been used as an IC mounting substrate in the past, is used as an IC mounting substrate that has an excellent high-frequency electrical wiring function, is inexpensive, and has good heat dissipation. Can be

Hereinafter, referring to the drawings, I according to the present invention will be described.
The C mounting board will be described in detail.

(Embodiment 1) FIGS. 1 to 3 are for explaining the construction of an embodiment of an IC mounting substrate according to the present invention. FIG. 1 is a perspective view and FIG. A cross-sectional view taken along line AA '(high-frequency electric wiring portion), and FIG.
FIG. 7 is a sectional view taken along line BB ′ of FIG.

This IC mounting substrate has a dielectric layer 2 on a Si substrate 3 on which a convex portion for mounting an IC substrate 4 is formed.
And a buffer 1a of the coplanar line and a ground 1b of the coplanar line are laminated on the dielectric layer.
And the IC substrate 4 is provided on the coplanar line 1a via solder bumps. That is, since the Si substrate 3 is used as a substrate for low-loss high-frequency electrical wiring, the dielectric layer 2 is formed as a buffer layer in the electrical wiring region of the Si substrate 3. Then, an electric wiring layer including the coplanar wirings 1a and 1b is formed thereon. Si
In the IC element 4 mounting area (convex portion) of the substrate 3, the dielectric layer 2
Is removed, that is, the convex portion of the Si substrate 3 is thermally exposed, and the IC element 4 is mounted while thermally contacting the IC element 4 and the surface of the Si substrate 3. As a result, both the low-loss high-frequency electric wiring function and the heat dissipation function can be realized.

The main parameters affecting the high frequency characteristics of the coplanar line are the thickness h of the dielectric buffer layer 2 between the coplanar line 1a and the Si substrate 2, the width w of the signal line 1a of the coplanar line, It is a gap interval s between the signal line 1a and the ground 1b. Tables 2 and 3 show the relationship between these parameters and the S parameter (S ₂₁ ) representing the transmission loss of the coplanar line (cpw line) at high frequencies. However, here, the Si substrate has a specific resistance of 1 kΩ · cm,
A dielectric loss tan δ = 0.005 (10 GHz) is used. Further, as the dielectric layer, quartz glass (tan δ
~ 0.0001) is used. Regarding the width w and the gap interval s, the reproducibility / reliability is 10 μm.
Although it is set to m or more, it goes without saying that the same effect can be expected in a combination of (w, s) smaller than this.

Table 2 shows the dependency of the S parameter on the buffer layer thickness, while Table 3 shows the dependency of the S parameter on the cpw line structure parameter.

[0032]

[Table 2]

[0033]

[Table 3]

First, with the buffer layer thickness h = 30 μm, the gap interval s was set to 10 μm and the width w of the signal line was changed. As a result, as shown in Table 2, w = 10 μ
S ₂₁ is the smallest at m, and even if s is made larger than 10 μm, the influence of the Si substrate becomes relatively large and the high frequency characteristics deteriorate, so (w, s) = (10, 10 μm)
Each value in Table 3 was determined as

For reference, Table 3 also shows the high frequency characteristics of the coplanar line formed on the alumina substrate. As described above, when quartz glass is used as the dielectric layer and the thickness h of the buffer layer is 10 μm or more, the transmission loss at 10 GHz is 1.0 dB / cm or less, which is a sufficiently small value. When h ≧ 30 μm, the value of the transmission loss does not change even if the Si substrate is changed to the alumina substrate, and it can be seen that the influence of the Si substrate is almost weakened by the dielectric layer.

In this embodiment, as shown in FIG. 3, a Si substrate having an IC element mounting portion 4 and irregularities formed in the vicinity thereof is used. The convex portion of the Si substrate, which is the mounting portion of the IC element 4, will be described. In the IC element 4, the electrode portion is mounted face down on the convex portion of the Si substrate by the solder bump 5. The solder bump 5 is the signal line 1 of the coplanar line.
The heat generated in the IC element 4 is electrically connected to the places corresponding to a and the ground 1b and is transferred to the lower Si substrate convex portion. The surface of the convex portion of the Si substrate is electrically insulated by forming a thermal oxide film or an insulator such as polyimide in a thickness of 0.3 μm. Then, an electrode pattern corresponding to the electrode portion of the IC element 4 is formed thereon, and the electric wiring portion and the electrode portion of the IC element are electrically connected by using solder bumps. It was confirmed that this structure dissipates heat efficiently when driving the IC.

By using such a structure, an IC or the like can be mounted on the IC mounting board as shown in FIG. In a substrate having such a structure, an IC
A high frequency signal of 10 GHz could be transmitted with a very small loss in the meantime, and good operation was confirmed.

Further, even if an induced polymer material or the like is used as the dielectric layer instead of quartz glass, the same effect can be obtained as long as tan δ is small, that is, if it is insulating. Absent.

(Embodiment 2) In this embodiment, in the IC mounting substrate of the above Embodiment 1, an induced polymer material is used as a dielectric layer instead of quartz glass. Table 4 shows the relative permittivity of typical induced polymer materials.

[0040]

[Table 4]

Thus, the relative dielectric constant of the organic dielectric is about 2.
It is within the range of 1 to 3.2, and the quartz glass (4.
The difference with 0) is not so large. Table 5 and Table 6 show data corresponding to Tables 2 and 3 of the above-mentioned Example 1 in which polyimide was used as a representative example as the dielectric layer.

[0042]

[Table 5]

[0043]

[Table 6]

As described above, data similar to that when quartz glass was used was obtained, reflecting the closeness of the values of the relative permittivity. Thus, the same effect can be obtained by using an induced polymer material as the dielectric layer instead of quartz glass.

Example 3 In Example 1 or 2, I
The electrode portion of the C element is face-up bonded to the convex portion of the Si substrate with a conductive adhesive having good thermal conductivity, and the ground post 6 and the gold ribbon wire 7 are used to electrically connect the electrode portion of the IC element and the substrate. Example 3 is one in which and are connected. The high-frequency wiring part is omitted because it is common to FIG. FIG. 4 shows a sectional view of the IC element mounting portion (corresponding to the sectional view taken along the line BB 'in FIG. 1).

In this way, the ground post 6 is mounted on the electrode so that the gold ribbon wire 7 is a horizontal straight line with the shortest distance. As a result, the reactance L of the coupling portion between the IC element and the coplanar line was reduced and good high frequency characteristics were obtained. Further, as in the case of Example 1, heat dissipation of the IC element was confirmed.

(Embodiment 4) FIGS. 5 to 7 are for explaining the construction of a fourth embodiment of an IC mounting substrate according to the present invention. FIG. 5 is a perspective view and FIG. C-of 5
FIG. 7 is a sectional view taken along line C ′, and FIG. 7 is a sectional view taken along line DD ′ of FIG.

The IC mounting substrate of this embodiment is the same as that of the first embodiment except that the electric wiring is changed from a coplanar line to a microstrip line (mic line) 8 and the other structures are all the same. Regarding the structural parameters of the substrate used in FIG. 5, the high frequency electrical wiring portion C of FIG.
It will be described with reference to FIG. 6 having the same structure as the cross-sectional view of -C '(the other one of the microstrip lines is omitted). In FIG. 6, 8a is a signal line of a microstrip line, 8b is a ground, 2 is a dielectric layer,
3 is a Si substrate. The main parameters that affect the high frequency characteristics of the microstrip line are the width w of the signal line 8a and the thickness h of the dielectric layer 2. Tables 7 and 8 show the relationship between these parameters and the S parameter (S ₂₁ ) representing the transmission loss of the microstrip line at high frequencies.
Shown in Here, quartz glass is used as the dielectric layer 2. Further, the width w of the mic line signal line is set to 5 μm or more, which has sufficient reproducibility / reliability, but it goes without saying that the same effect can be expected when w is smaller than this.

Table 7 shows that the buffer layer thickness is constant,
It shows the result of examining the change of the S parameter when the structural parameter W of the mic line is changed.
Table 8 shows the results when the thickness of the buffer layer was changed.

[0050]

[Table 7]

[0051]

[Table 8]

First, w was changed while h = 30 μm. As a result, as shown in Table 7, S at w = 20 μm
₂₁ is the smallest. Thus, depending on the value of h, appropriate w
Exists.

Next, Table 8 shows an example of S ₂₁ when h is changed. As for w, an appropriate value that makes S ₂₁ small is selected. For reference, the high frequency characteristics of the microstrip line formed on the alumina substrate are also shown. Thus, when quartz glass is used as the dielectric layer, when h is 5 μm or more, the transmission loss at 10 GHz is 1.0 dB / cm or less, which is a sufficiently small value. Since the electric field does not enter the Si substrate side, the value of the transmission loss does not change even if the Si substrate is changed to the alumina substrate.

The convex portion of the Si substrate, which is the mounting portion of the IC element, is exactly the same as that of FIG. 3 of the first embodiment except that the electric wiring portion is changed from the coplanar line to the microstrip line. D- in FIG. 5, including the element mounting part
FIG. 7 is a sectional view of D ′. As in Example 1, it was confirmed that the heat when driving the IC was efficiently dissipated.

Using such a structure, as shown in FIG.
An IC or the like can be mounted on the C mounting board. In this substrate, a high frequency signal of 10 GHz could be transmitted between ICs with a very small loss, and favorable operation was confirmed.

Similar to the first embodiment, the same effect can be obtained as long as the dielectric layer is made of an insulating polymer instead of quartz glass, as long as it has an insulating property (S).
₂₁ characteristics table omitted).

(Embodiment 5) FIG. 8 shows I according to the present invention.
FIG. 9 is a cross-sectional view for explaining the configuration of the fifth embodiment of the C-type mounting substrate and is a cross-sectional view corresponding to the IC element mounting portion (cross-sectional view taken along the line D-D ′ of FIG. 5) of the fourth embodiment.

In the IC mounting substrate of Example 4, I
Example 5 is a case in which the C element 4 is bonded with the electrode surface upward, that is, face-up to the convex portion of the Si substrate with a conductive adhesive and connected to the electrical wiring by the ground post 6 and the gold ribbon wire 7. The high-frequency wiring section has the same structure as that shown in FIG. As shown in FIG. 8, the ground post 6 is mounted on the electrode so that the gold ribbon wire 7 is horizontally straight and has the shortest distance. As a result, the reactance L of the coupling portion between the IC element and the microstrip line is reduced, and good high frequency characteristics are expected. As in Example 1, it was confirmed that heat when driving the IC was efficiently dissipated.

(Embodiment 6) FIG. 9 shows I according to the present invention.
FIG. 10 is a cross-sectional view corresponding to an IC element mounting portion (cross-sectional view taken along the line BB ′ of FIG. 1) of the first embodiment, for explaining the configuration of the sixth embodiment of the C-mounted board. .

The difference from Example 1 is that in this Example, a flat Si substrate 3 having no unevenness was used, and an IC element was mounted by making a hole so that the IC element could be fitted into the dielectric layer 2.
For high frequency wiring, coplanar lines 1a, 1b
2 is used and has the same structure as in FIG. I
FIG. 9 shows a sectional view of the C element mounting portion. A hole into which the IC of reference numeral 4 is fitted is formed in the dielectric layer of reference numeral 2 by dry etching. The IC element 4 is fitted with the electrode surface upward, that is, face-up, and is connected to the cpw line signal line 1a formed on the buffer layer 2 by the height matching ground post 6 and the gold ribbon 7. As in the second embodiment, the reactance L of the gold ribbon is reduced and good high frequency characteristics are expected.

(Embodiment 7) In the IC mounting substrate of Embodiment 6, the IC element and the dielectric layer have the same height (FIG. 10). This eliminates the need for ground posts.

According to the structure of the sixth or seventh embodiment, it is possible to perform the first to fifth embodiments without forming the concavo-convex pattern on the Si substrate.
The high-frequency wiring function and the heat dissipation function described above can be provided.

(Embodiment 8) An embodiment 8 (not shown) uses a microstrip line in place of the coplanar line in the electric wiring portion in the embodiment 6 or 7. The structure of the microstrip line portion is the same as that shown in FIG.

(Embodiment 9) FIG. 11 is a view for explaining the configuration of an embodiment of an IC mounting board according to the present invention. The IC element mounting portion of Embodiment 1 (BB in FIG. 1). It is a cross-sectional view corresponding to (a cross-sectional view taken along the line ').

In this embodiment, as in Embodiment 6 or 7, a flat Si substrate 3 is used, and a hole is formed so that an IC element can be fitted in the dielectric layer 2 as shown in FIG.
The C element was mounted with the electrode surface down, that is, face down. The high-frequency wiring section uses the same coplanar lines 1a and 1b as in the first embodiment and has the same structure as in FIG. Sectional drawing of an IC element mounting part. The dielectric layer 2 was dry-etched to form a hole into which the IC element 4 was fitted. The IC element 4 is fitted with the electrode surface downward, that is, facedown, and is connected to the cpw line signal line 1a and the ground 1b formed on the dielectric layer 2 by the solder bumps 5. If the coplanar line is formed by a normal gold plating process, the step between the upper surface of the dielectric layer and the element mounting portion can be easily electrically connected. Similar to the sixth embodiment, the high-frequency wiring function and the heat dissipation function described in the first to fifth embodiments can be provided without processing the Si substrate in a concavo-convex shape.

(Embodiment 10) A microstrip line was used in place of the coplanar line in the electric wiring portion of the ninth embodiment. FIG. 12 shows a sectional view of the IC element mounting portion and the electric wiring portion. The sectional view of the microstrip line portion has the same structure as that in FIG. In FIG.
After removing the dielectric layer of the element mounting part by etching,
By forming a thin insulating layer, indicated by the black layer, I
It is possible to prevent an electrical short between the ground of the microstrip line and the signal line without impairing heat conduction from the C element to the Si substrate.

(Embodiment 11) FIG. 13 is a perspective view for explaining the structure of an embodiment of an IC mounting board according to the present invention.

In the eleventh embodiment, a flat Si substrate is used, an electric wiring portion is a microstrip line, and an IC is used.
The IC element is mounted on the Si substrate of the element mounting portion with the electrode surface facing up, that is, face up. Then, a multilayer electrode is formed in the electric wiring portion by using a technique such as the multilayer electrode 8c and the through hole 9. The technology of such a multi-layer electrode has been established with a copper-polyimide substrate or the like, and it is possible to fabricate it as in this embodiment. By making the layers multi-layered in this way, the application range of the electric wiring portion can be expanded.

(Embodiment 12) FIGS. 14 to 15 are for explaining the structure of an embodiment of an IC mounting substrate according to the present invention. FIG. 14 is a perspective view and FIG. 15 is FIG.
3 is a cross-sectional view (IC element mounting portion) taken along line EE ′ in FIG.

The twelfth embodiment is the S described in the first to eleventh embodiments.
This is an example in which an IC mounting board formed on an i substrate is incorporated into a conventional alumina IC mounting board 10.

An IS element having a large heat generation amount is mounted on a Si substrate as in the fifth embodiment, and a hole is fitted into the alumina substrate 10 for the entire Si substrate. The electric wiring on the Si substrate and the alumina substrate are connected by a gold ribbon wire. By placing the whole on the heat dissipation plate 11, it is possible to utilize the excellent heat dissipation function of the Si substrate while using the IC mounting substrate established on the conventional alumina substrate as it is. With such a structure, it becomes possible to use an IC that cannot be used only with the conventional alumina IC mounting board 10 because the heat generation is large.

[0072]

As described above, the IC mounting substrate of the present invention has a high dielectric loss at high frequencies due to Si.
The defects of the substrate are solved by using a dielectric layer having an appropriate thickness, and in order to take advantage of the characteristic of the Si substrate that the thermal conductivity is large, the Si substrate surface is thermally exposed to the IC element mounting portion and thermally. Mounted while maintaining contact. Therefore, we have realized an inexpensive IC mounting board with excellent high-frequency wiring function and heat dissipation function.

Specifically, a Si substrate having an electric wiring region and an element mounting region is used, a dielectric layer is formed in the electric wiring region to form an electric wiring portion, and an IC element and a Si substrate are formed in the element mounting region. While keeping thermal contact with the IC element,
It is mounted on the board. Here as high frequency electrical wiring,
A coplanar line or a microstrip line can be used.

Further, an Si substrate having a convex portion of a concave portion is used, a dielectric layer is formed by using the concave portion as an electric wiring portion to form an electric wiring portion, and the convex portion serves as an element mounting portion, and an IC element is used as a Si substrate. It may be mounted while maintaining thermal contact with. Also here, a coplanar line or a microstrip line can be used as the high-frequency electrical wiring.

[Brief description of drawings]

FIG. 1 is a perspective view for explaining the configuration of an embodiment of an IC mounting substrate according to the present invention.

FIG. 2 is a cross-sectional view (high-frequency electric wiring portion) taken along the line AA ′ in FIG.

3 is a cross-sectional view taken along the line BB ′ of FIG.

FIG. 4 is a cross-sectional view for explaining the configuration of a third embodiment of the IC mounting substrate according to the present invention.

FIG. 5 is a perspective view for explaining the configuration of a fourth embodiment of the IC mounting substrate according to the present invention.

6 is a cross-sectional view taken along the line CC ′ of FIG.

7 is a cross-sectional view taken along the line DD ′ of FIG.

FIG. 8 is a cross-sectional view for explaining the configuration of a fifth embodiment of the IC mounting substrate according to the present invention.

FIG. 9 is a sectional view for explaining the structure of a sixth embodiment of an IC mounting substrate according to the present invention.

FIG. 10 is a sectional view for explaining the configuration of a seventh embodiment of the IC mounting substrate according to the present invention.

FIG. 11 is a cross-sectional view for explaining the configuration of a ninth embodiment of an IC mounting substrate according to the present invention.

FIG. 12 is a cross-sectional view of an IC element mounting portion and an electric wiring portion when a microstrip line is used instead of the coplanar line in the electric wiring portion of the IC mounting substrate according to the present invention.

FIG. 13 is a perspective view for explaining the configuration of an embodiment of an IC mounting substrate according to the present invention.

FIG. 14 is a perspective view for explaining the configuration of an embodiment of an IC mounting substrate according to the present invention.

15 is a cross-sectional view (IC element mounting portion) taken along line EE ′ of FIG.

[Explanation of symbols]

 1a Coplanar line (signal line) 1b Coplanar line (ground) 2 Dielectric layer 3 Si substrate 4 IC element 5 Solder bump 6 Ground post 7 Gold ribbon line 8a Microstrip line (signal line) 8b Microstrip line (ground) 8c Multilayer wiring embedded electrode 9 Through hole 10 Alumina IC mounting substrate 11 Heat sink

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yuji Akahori 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (4)

[Claims] 1. An IC mounting substrate having a Si substrate and a dielectric layer laminated at a predetermined position on the Si substrate, wherein the Si substrate is a region where the dielectric layer is laminated, And an electric wiring area in which an electric wiring path is provided, and an element mounting area in which the dielectric layer is not laminated and on which an IC element is directly mounted.
C mounting board. 2. The IC mounting board according to claim 1, wherein the electrical wiring path is a coplanar line including a signal line and a ground. 3. The IC mounting board according to claim 1, wherein the electrical wiring path is a microstrip line including a signal line and a ground. 4. The IC mounting substrate according to claim 1, wherein the Si substrate has a concave portion in which the electric wiring region is provided and a convex portion in which an element mounting region is provided. A substrate for mounting as an IC, which is characterized by the following.