JP3409767B2 - High frequency circuit board - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency circuit board used in millimeter wave / microwave band.

[0002]

2. Description of the Related Art When flip-chip mounting a plurality of circuit elements on a high frequency circuit board, a coplanar line is often used as a connecting line. In the coplanar line, the signal line and the ground are on the same plane, and it becomes possible to reproducibly connect the semiconductor element and the coplanar line with low inductance when flip-chip mounting. This example is Hirose
(T. Hirose et al., "A FLIP-CHIP DESIGN WITH
CPW TECHNOLOGY IN THEW-BAND ", IEEE MTT-S, INTERNA
TIONAL MICROWAVE SYMPOSIUM, DIGEST, PP.525-528, 19
1998).

FIG. 11 (a) is a plan view of a conventional high frequency circuit board in which a coplanar line is formed. On the high-frequency circuit board 1, a coplanar line 2 having a signal line width W and a signal line-ground gap S is formed. Bumps 4 necessary for flip chip mounting are formed on the coplanar line 2. FIG. 11B is a sectional view of a circuit board on which semiconductor elements are flip-chip mounted.
The semiconductor element 8 is connected to the coplanar line 2 formed on the conductor layer 6 via the bump 4.

When using a coplanar line for high frequencies,
W + 2S (hereinafter,
It is desirable to reduce the distance between grounds).
The change in the propagation characteristics due to the size of the ground distance is
L etc. (WH Haydl et al., "DESIGN DATA FOR MILL
IMETER WAVE COPLANAR CIRCUITS ", 23RD EUROPEAN MICR
OWAVE CONFERENCE, DIGEST, PP.223-228), etc., but it is desirable to reduce the distance between the grounds in order to realize propagation that can approximate the TEM mode. More specifically, it is described that the upper limit of the ground distance is approximately 1/10 of the signal wavelength as a condition for realizing the propagation that can be approximated to the TEM mode. Also, by reducing the distance between the grounds, high-density wiring becomes possible. Furthermore, when the distance between the grounds is increased, the coupling with the unnecessary transmission mode in the board increases, and the transmission loss increases.
There arises a problem that radiation loss increases at discontinuous portions such as bends, branches, and feedthroughs due to the coplanar line. The conductor loss tends to increase as the distance between the grounds decreases, but the reasons described above are the main causes.
A coplanar line with a distance between grounds of about 500 micrometers or less is used.

[0005]

On the other hand, in a coplanar line formed on a high frequency circuit board by using thick film wiring or thin film wiring technology, the distance between grounds that can be formed limits the pattern accuracy (or resolution). receive. According to the commonly used pattern forming technique, the minimum value of the distance between grounds is about 250 micrometers for thick film wiring and about 100 micrometers for thin film wiring.

By the way, the relative permittivity of a commonly used high frequency circuit substrate is about 2 to 12, but when a coplanar line having a characteristic impedance of 50 ohms is formed on this substrate, the gap becomes smaller than the signal line width. . Therefore, the gap is limited in pattern accuracy. For example, when a coplanar line having a characteristic impedance of 50 ohms is formed on a ceramic substrate having a relative dielectric constant of 7.1, the ground-to-ground distance of 350 μm is as follows: the signal line width W is 200 μm and the gap S is 75 μm. It becomes a micrometer. Generally, when a pattern is formed by the thick film wiring technique, the minimum required line width / spacing is about 100 micrometers, so the above 75
Coplanar lines with micrometer gaps either become unformable or lead to a significant reduction in manufacturing yield. Furthermore, this tendency becomes more remarkable as the relative dielectric constant becomes smaller. Even if the thin film wiring technique is used, it is hard to say that sufficient pattern accuracy can be secured, which causes a decrease in yield and an increase in cost.

The present invention has been made in order to solve the above problems, and provides a coplanar line having a small ground distance and a large gap, which solves the above-mentioned yield reduction due to wiring formation. It is an object of the present invention to provide a high-frequency circuit board having the same.

[0008]

In order to achieve the above object, the high frequency circuit board of the present invention has at least a first dielectric layer, a conductor layer, and a second dielectric layer from below. The conductive layers form a coplanar line having a signal line and a ground, and the second dielectric layer is partially removed to form an opening exposing a part of the coplanar line. It is characterized in that a semiconductor element is mounted thereon and is electrically connected to the coplanar line.

The semiconductor element may be flip-chip mounted on the coplanar line via bumps so that the height of the upper surface of the second dielectric layer is lower than the height of the upper surface of the semiconductor element. Or, flip chip mounting a semiconductor element whose plane dimension is larger than that of the opening,
The opening provided in the second dielectric layer may be closed by a semiconductor element. Also, the second dielectric layer may be formed of an organic resin material. Further, the semiconductor element may be sealed with a resin material.

Alternatively, the semiconductor element may be flip-chip mounted on the coplanar line via bumps so that the upper surface of the second dielectric layer and the upper surface of the semiconductor element have the same height. Good. In that case, the semiconductor element may be flip-chip mounted on the coplanar line, the substrate may be placed on the upper surface of the semiconductor element, and the opening of the second dielectric layer may be closed by the substrate.

[0011]

Further, in all of the above high frequency circuit boards, it is preferable that the ground forming the coplanar line has a finite width.

In the conventional high-frequency circuit board structure, the semiconductor element is mounted on the conductor layer and the dielectric layer is not present on the coplanar line, whereas in the high-frequency circuit board structure of the present invention, the signal is The second dielectric layer will be present on the coplanar line having the line and ground. The presence of the second dielectric layer can increase the effective permittivity or the electric flux density between the signal line and the ground, so that the gap between the signal line and the ground can be expanded. As a result, even if the ground distance of the coplanar line is set to 1/10 or more of the signal wavelength, sufficiently excellent transmission characteristics can be obtained. Further, from the viewpoint of transmission characteristics or processing, the thickness of the second dielectric layer is set to 1
It is desirable to make it 1/0 or more, and it is desirable to use the same material for the first dielectric layer and the second dielectric layer.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described with reference to FIG. Figure 1
A plan view of a high-frequency circuit board in which the coplanar line of the present embodiment is formed is shown in (a). On the high-frequency circuit board 1, a coplanar line 2 having a signal line width W and a signal line-ground gap S is formed. Bumps 4 necessary for flip chip mounting are formed on the coplanar line 2.

FIG. 1B shows a high-frequency circuit board 1 on which semiconductor elements are flip-chip mounted, which is indicated by X in FIG. 1A.
A sectional view taken along the line -X 'is shown. The first dielectric layer 5, the conductor layer 6, and the second dielectric layer 7 are laminated in this order. The coplanar line 2 is formed on the conductor layer 6,
In the dielectric layer 7, the region where the semiconductor element 8 is mounted is partially removed, and the opening 3 is formed. In the opening 3, the coplanar line 2 is partially exposed and the bump 4 is formed. The semiconductor element 8 is connected to the coplanar line 2 formed on the conductor layer 6 via the bump 4. Further, the thickness H of the second dielectric layer 7 is determined by the semiconductor element 8
Is smaller than the thickness T.

FIG. 1C shows a high frequency circuit board 1 on which a semiconductor element is flip-chip mounted.
A sectional view taken along the line -Y 'is shown. The signal line 18 of the coplanar line 2 and the ground 9 are formed using the conductor layer 6.

FIG. 2 shows a coplanar line having a ground distance of 350 micrometers in the present embodiment.
Second when (Characteristic impedance 50 ohm) is formed
The relationship between the thickness H of the dielectric layer 7 and W and S is shown. The structure of the conventional example shown in FIG. 11 corresponds to the case where the thickness H of the second dielectric layer 7 is 0 micrometer. As the thickness H of the second dielectric layer 7 increases, W decreases while S increases, for example, when H is 80 micrometers, W is 150 micrometers and S is 100 micrometers. . That is, the minimum line width / spacing in this case is 10
It becomes 0 micrometer, which can be increased from the conventional 75 micrometer, and the required pattern accuracy can be relaxed.

The expansion of the gap S by providing the second dielectric layer 7 is realized by increasing the effective dielectric constant or the electric flux density between the signal line 18 and the ground 9. In order to sufficiently obtain this effect, it is desirable that the thickness H of the second dielectric layer 7 be equal to or larger than the gap S in the case where the second dielectric layer 7 is not provided.

FIG. 3 shows a process diagram for mounting the semiconductor element 8 on the high-frequency circuit board 1 according to the present embodiment.
First, attach the semiconductor element 8 to the bonding tool 11.
(FIG. 3A), thermocompression bonding is performed on the bumps 4 formed in the openings 3 (FIG. 3B). Mounting is completed by stopping the suction and removing the bonding tool 11 (see FIG. 3).
(C)). In FIG. 3B, since the thickness H of the second dielectric layer 7 is smaller than the thickness T of the semiconductor element 8, a gap G is secured between the bonding tool 11 and the second dielectric layer 7. To be done. Therefore, the semiconductor element 8 having a size smaller than the suction surface of the bonding tool 11 can be freely handled. That is, it is not necessary to replace the bonding tool 11 according to the size of the semiconductor element 8. In the present embodiment, the relationship between the thickness T of the semiconductor element 8 and the thickness H of the second dielectric layer 7 is more strictly taken into consideration in consideration of the height of the bump 4 and the like. It is limited to the secured range.

[Second Embodiment] A second embodiment of the present invention will be described with reference to FIG. In FIG. 4 (a),
The top view of the high frequency circuit board in which the coplanar line | wire of this Embodiment was formed is shown. On the high-frequency circuit board 1, a coplanar line 2 having a signal line width W and a signal line-ground gap S is formed. Bumps 4 necessary for flip chip mounting are formed on the coplanar line 2.

FIG. 4B shows a cross-sectional view of the high-frequency circuit board 1 on which semiconductor elements are flip-chip mounted. The first dielectric layer 5, the conductor layer 6, and the second dielectric layer 7 are laminated in this order. The coplanar line 2 is formed on the conductor layer 6. A through hole 12 in which a conductor is embedded is formed in the second dielectric layer 7, and a bump 4 is formed on the through hole 12. The semiconductor element 8 is connected to the coplanar line 2 formed on the conductor layer 6 via the bump 4 and the through hole 12. In this case, the through hole 12 also serves as an electrode pad.

Also in this embodiment, as in the first embodiment, the minimum line width / interval can be increased,
The required pattern accuracy can be relaxed. Further, unlike the first embodiment, since there is no opening in the second dielectric layer 7, there is no limitation on the relationship between the thickness T of the semiconductor element 8 and the thickness H of the second dielectric layer. A semiconductor element having a size smaller than the suction surface of the bonding tool can be freely handled.

[Third Embodiment] A third embodiment of the present invention will be described with reference to FIG. In FIG. 5 (a),
The top view of the high frequency circuit board in which the coplanar line | wire of this Embodiment was formed is shown. On the high-frequency circuit board 1, a coplanar line 2 having a signal line width W and a signal line-ground gap S is formed. In the case of the present embodiment, the ground width WG of the coplanar line 2 has a finite value. Bumps 4 necessary for flip chip mounting are formed on the coplanar line 2.

FIG. 5B shows the high frequency circuit board 1 on which the semiconductor element is flip-chip mounted, which is indicated by X in FIG. 5A.
A sectional view taken along the line -X 'is shown. The first dielectric layer 5, the conductor layer 6, and the second dielectric layer 7 are laminated in this order. The coplanar line 2 is formed on the conductor layer 6,
In the dielectric layer 7, the region where the semiconductor element 8 is mounted is partially removed, and the opening 3 is formed. In the opening 3, the coplanar line 2 is partially exposed and the bump 4 is formed. The semiconductor element 8 is connected to the coplanar line 2 formed on the conductor layer 6 via the bump 4. The thickness H of the second dielectric layer 7 is smaller than the thickness T of the semiconductor element 8.

FIG. 5 (c) shows Y in FIG. 5 (a) of the high frequency circuit board 1 on which the semiconductor element is flip-chip mounted.
A sectional view taken along the line -Y 'is shown. The signal line 18 of the coplanar line 2 and the ground 9 are formed using the conductor layer 6. Here, in the two glands 9 and 9, the distance (W + 2S + 2WG) between the outer edges of the glands is at least W.
It is preferably + 4S or more, and is preferably smaller than half the wavelength of the signal passing through the coplanar line 2.

Also in this embodiment, as in the first embodiment, the minimum line width / interval can be increased,
The required pattern accuracy can be relaxed. On the other hand, unlike the first embodiment, the ground width WG of the coplanar line 2 has a finite value. This is for the following reason. Second dielectric layer 7 introduced according to the invention
In the structure in which the second dielectric layer 7 is formed on the ground 9, the thickness of the second dielectric layer 7 is set as described in, for example, Misao Haneishi, latest planar antenna, published by Sogo Gijutsu Center, page 63. When H exceeds the thickness of equation (1) below,
Surface waves appear. H> c / {4f · √ (εr-1)} (1)

Here, c is the speed of light, f is the operating frequency, and ε is the relative permittivity of the material forming the second dielectric layer. The surface wave is a factor of leakage for signal transmission in the coplanar line and leads to an increase in transmission loss. In a coplanar line having a ground with a finite width, the surface wave mode does not exist in the region without the ground, so that leakage of signal transmission can be suppressed. Therefore, in the case of forming a low-loss coplanar line, in the first embodiment, the thickness H of the second dielectric layer 7 needs to be thin so that surface waves are not generated. The thickness H of the second dielectric layer 7 is not limited in the present embodiment. The coplanar line having the ground with a finite width can be applied to the example shown in the second embodiment, and the same effect can be obtained.

[Fourth Embodiment] A fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 shows a cross-sectional view of a high-frequency circuit board on which semiconductor elements are flip-chip mounted. The first dielectric layer 5, the conductor layer 6, the second dielectric layer 7, and the third dielectric layer 13 are laminated in this order. A coplanar line is formed in the conductor layer 6, a region of the second dielectric layer 7 where the semiconductor element 8 is mounted is partially removed, and an opening 3 is formed. Opening 3
Then the coplanar line is partially exposed and bump 4
Are formed. Further, the third dielectric layer 14 is opened wider than the opening 3, and the cavity 17 is formed. The semiconductor element 8 has the conductor layer 6 via the bumps 4.
It is connected to the coplanar line formed in. The thickness H of the second dielectric layer 7 is smaller than the thickness T of the semiconductor element 8.
Further, the cavity 17 can be sealed by covering it with the lid 14.

The present embodiment is characterized in that the same effects as in the first embodiment can be obtained and that sealing can be performed. The size of the suction surface of the bonding tool must be smaller than that of the cavity 17, but can be larger than that of the semiconductor element 8. Therefore, if the cavity size is large, it is not necessary to replace the bonding tool according to the size of the semiconductor element 8.

[Fifth Embodiment] A fifth embodiment of the present invention will be described with reference to FIG. FIG. 7 shows a cross-sectional view of a high-frequency circuit board on which semiconductor elements are flip-chip mounted. The first dielectric layer 5, the conductor layer 6, and the second dielectric layer 7 are laminated in this order. A coplanar line is formed in the conductor layer 6, a region of the second dielectric layer 7 where the semiconductor element 8 is mounted is partially removed, and an opening 3 is formed. In the opening 3, the coplanar line is partially exposed, and the bump 4 is formed. The semiconductor element 8 is connected to the coplanar line formed on the conductor layer 6 via the bump 4. In the case of the present embodiment, the sum H of the thickness of the second dielectric layer 7 and the thickness of the conductor layer 6 is set equal to HB which is the sum of the thickness of the semiconductor element 8, the bump height and the pad thickness. As a result, the heights of the second dielectric layer 7 and the mounted semiconductor element 8 are equal.

In the present embodiment, the bonding tool used for flip chip mounting comes into contact with the second dielectric layer 7 during thermocompression bonding and stops at that position, so that the bump height can be easily controlled. The material forming the second dielectric layer 7 is not limited, but a relatively flexible material such as an organic resin is desirable from the viewpoint of protecting the bonding tool.

[Sixth Embodiment] A sixth embodiment of the present invention will be described with reference to FIG. FIG. 8 shows a cross-sectional view of a high-frequency circuit board on which a semiconductor substrate is flip-chip mounted. The first dielectric layer 5, the conductor layer 6, and the second dielectric layer 7 are laminated in this order. A coplanar line is formed in the conductor layer 6, a region of the second dielectric layer 7 where the semiconductor element 8 is mounted is partially removed, and an opening 3 is formed. In the opening 3, the coplanar line is partially exposed, and the bump 4 is formed. In the present embodiment, the semiconductor element 8 is mounted on the back surface (the top surface in the figure, in flip-chip mounting, the front surface side on which the circuit is formed faces downward (board side), so the top surface becomes the back surface). The back substrate 15 is adhered. The semiconductor element 8 is connected to the coplanar line formed on the conductor layer 6 via the bump 4. By making the sum H of the thickness of the second dielectric layer 7 and the conductor layer 6 equal to HB, which is the sum of the thickness of the semiconductor element 8, the bump height and the pad thickness, the second dielectric The heights of the body layer 7 and the mounted semiconductor element 8 are made equal.

In the case of the present embodiment, the back substrate 15 is used as the second dielectric layer 7 during the thermocompression bonding process of flip chip mounting.
Since it contacts with and stops at that position, high controllability of the bump height is secured. It is also possible to seal the back substrate 15 with a resin or the like, and at this time, since the resin does not enter the opening 3, the high frequency characteristics are not impaired. The material of the back substrate 15 is not limited, but if a material having a high thermal conductivity such as metal is used, a heat dissipation effect can be expected.

[Seventh Embodiment] A seventh embodiment of the present invention will be described with reference to FIG. FIG. 9 shows a cross-sectional view of a high-frequency circuit board on which semiconductor elements are flip-chip mounted. The first dielectric layer 5, the conductor layer 6, and the second dielectric layer 7 are laminated in this order. A coplanar line is formed in the conductor layer 6, a region of the second dielectric layer 7 where the semiconductor element 8 is mounted is partially removed, and an opening 3 is formed. In the opening 3, the coplanar line is partially exposed, and the bump 4 is formed. In the case of the present embodiment, the semiconductor element 8 is larger than the size of the opening 3 and is connected to the coplanar line formed in the conductor layer 6 via the bump 4. The sum H of the thickness of the second dielectric layer 7 and the thickness of the conductor layer 6 is set to be the sum of the bump height after mounting and the pad thickness.

In the case of the present embodiment, since the semiconductor element 8 comes into contact with the upper surface of the second dielectric layer 7 and stops at that position during pressure bonding during flip-chip mounting, the controllability of the bump height is high. Is secured. The material forming the second dielectric layer 7 is not limited, but a relatively flexible material such as an organic resin is preferable in that the semiconductor element 8 is not damaged.

[Eighth Embodiment] An eighth embodiment of the present invention will be described with reference to FIG. FIG. 10 shows a cross-sectional view of a high frequency circuit board on which a semiconductor substrate is flip-chip mounted. The first dielectric layer 5, the conductor layer 6, and the second
The dielectric layer 7 is laminated in this order. The conductor layer 6
A coplanar line is formed in the second dielectric layer 7, a region of the second dielectric layer 7 where the semiconductor element 8 is mounted is partially removed, and an opening 3 is formed. In the opening 3, the coplanar line is partially exposed, and the bump 4 is formed. The semiconductor element 8 is larger than the size of the opening 3 and is connected to the coplanar line formed on the conductor layer 6 via the bump 4. The sum H of the thickness of the second dielectric layer and the thickness of the conductor layer 6 is set to be the sum of the bump height after mounting and the pad thickness.

In the case of the present embodiment, as in the case of the seventh embodiment, the semiconductor element 8 comes into contact with the second dielectric layer 7 at the time of pressure bonding during flip-chip mounting and stops at that position. High controllability of bump height is ensured. Further, in the present embodiment, the semiconductor element 8 is covered with the sealing resin 16. Since the sealing resin 16 does not enter the opening 3, the performance of the high frequency circuit is not impaired.

[Ninth Embodiment] A ninth embodiment of the present invention will be described with reference to FIG. FIG. 12 shows a cross section of a coplanar line formed on a high frequency circuit board. Similar to FIG. 1C in the first embodiment, the signal line 18 of the coplanar line and the ground 9 are formed on the first dielectric layer 5, and the second dielectric layer 7 is further laminated. There is. However, in the present embodiment, the back surface ground 20 is formed. A via hole 19 connecting the grounds 9 and 20 is formed along the coplanar line for the purpose of preventing an increase in propagation loss due to the parallel plate structure formed of the ground 9 and the backside ground 20. Therefore, signal propagation may occur due to the waveguide structure surrounded by both grounds 9 and 20 and the via hole 19.
This problem can be avoided by reducing the distance between the via holes 19 and setting the cutoff frequency of the waveguide higher than the signal frequency. The thickness of the second dielectric layer 7 is 10 times the distance between grounds.
Make at least one-third. On the other hand, the thickness of the second dielectric layer 7 is
It is desirable to limit it to a range in which the surface wave described by the above equation (1) does not appear.

Next, in the conventional example and the example (in the structure described in the first embodiment, the distance between grounds is 350 micrometers, and the thickness of the second dielectric layer is 80 micrometers). FIG. 13 shows the frequency dependence of the group velocity (dω / dβ, ω is the angular velocity, and β is the phase constant). From this figure, it can be seen that the frequency dependence (frequency dispersion) of the group velocity is small in the example. FIG. 14 shows the relationship between the ratio of the thickness of the second dielectric layer to the distance between the grounds and the amount of change in group velocity at 100 GHz when DC is used as a reference. If the ratio of the thickness of the second dielectric layer to the distance between the grounds is 0.1 or more (if the thickness of the second dielectric layer is 1/10 or more of the distance between the grounds), the dielectric layer Compared with the conventional example where the thickness is zero, the change in group velocity is 3
It can be reduced to less than a factor of one. If the second dielectric layer does not have a large difference from the relative dielectric constant of the first dielectric layer, the amount of change in group velocity does not change that much. Note that if the dielectric constant of the second dielectric layer is within ± 50% of the dielectric constant of the first dielectric layer, the effect of suppressing frequency dispersion is remarkably obtained. Further, when manufacturing a multi-layer substrate, it is better to use the same material for the first dielectric layer and the second dielectric layer so that there is no problem of the coefficient of thermal expansion. Particularly, in the case of a ceramic substrate, co-firing is possible. It is possible and has many advantages such as low cost.

As described above, in all the embodiments of the present invention, the effective dielectric constant or electric flux between the signal line 18 and the ground 9 is provided by providing the second dielectric layer 7 covering the coplanar line. The density is increased and the transmission characteristics can be improved as compared with the conventional one. Therefore, according to the literature by Haydl et al. Exemplified in the "Prior Art" section, it was necessary to set the ground distance to 1/10 or less of the signal wavelength in order to realize the propagation that can be approximated to the TEM mode. According to the configuration of the present invention, the ground distance is set to 1/10 or more of the signal wavelength, and excellent transmission characteristics can be obtained even if a coplanar line having a pattern accuracy (resolution) that is relatively gentle as compared with the prior art is formed. You can

Although the via hole 19 is provided in FIG. 12, this is not a constituent of the present invention. For example, the via hole may not be provided when an increase in propagation loss is allowed, or when the back surface ground is not provided and the first dielectric layer is thin enough not to generate a surface wave. Further, also in the present embodiment, as in the first embodiment and the like, the minimum line width / interval can be increased, and the required pattern accuracy can be relaxed.

A small frequency dispersion characteristic in the transmission line is indispensable especially in wideband digital signal transmission applications. Further, also in other applications, since the frequency dispersion of the transmission characteristics is small, it is possible to provide a high-frequency circuit board which can be easily designed over a wide band.

The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the description of the above embodiment, the substrate material is not particularly limited, but the present invention is a multilayer substrate using alumina, glass ceramics, aluminum nitride, etc., a multilayer organic substrate, or a polyimide resin or BCB (Benzo) for various substrates. -
Cyclo-Buthene) can be applied to a wide range of multilayer substrates such as laminated.

[0044]

As described above in detail, according to the present invention, a coplanar line having a small ground-to-ground distance can be easily formed. Even if a coplanar line with the same ground distance as the conventional one is formed, the minimum line width /
It is possible to make the distance larger than the distance with a margin, and it is possible to reduce the cost and improve the manufacturing yield. Further, even in flip-chip mounting, which was an advantage of using a coplanar line as a connection line, it becomes possible to apply a semiconductor element having a size smaller than the suction surface of the bonding tool regardless of its size.

[Brief description of drawings]

1A and 1B are diagrams showing a high-frequency circuit board according to a first embodiment of the present invention, in which FIG. 1A is a plan view, FIG. 1B is a sectional view taken along line XX ′ in FIG. ) (A) is a sectional view taken along the line YY '.

FIG. 2 is a diagram illustrating changes in the signal line width and the gap with respect to the thickness of the second dielectric layer according to the present invention.

FIG. 3 is a process diagram for explaining a flip-chip mounting process of the high-frequency circuit board according to the same embodiment.

4A and 4B are diagrams showing a high-frequency circuit board according to a second embodiment of the present invention, in which FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along line XX ′ in FIG. .

5A and 5B are diagrams showing a high-frequency circuit board according to a third embodiment of the present invention, in which FIG. 5A is a plan view, FIG. 5B is a sectional view taken along line XX ′ of FIG. ) (A) is a sectional view taken along the line YY '.

FIG. 6 is a sectional view showing a high-frequency circuit board according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view showing a high-frequency circuit board according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view showing a high-frequency circuit board according to a sixth embodiment of the present invention.

FIG. 9 is a sectional view showing a high-frequency circuit board according to a seventh embodiment of the present invention.

FIG. 10 is a sectional view showing a high frequency circuit board according to an eighth embodiment of the present invention.

11A and 11B are diagrams showing a high-frequency circuit board on which a conventional coplanar line is formed, in which FIG. 11A is a plan view and FIG.
It is sectional drawing which follows the XX 'line of (a).

FIG. 12 is a sectional view showing a high-frequency circuit board according to a ninth embodiment of the present invention.

FIG. 13 is a graph comparing the frequency dependence of the group velocity between the conventional example and the example.

FIG. 14 is a graph showing the relationship between the ratio of the thickness of the second dielectric layer to the distance between the grounds and the amount of change in group velocity at 100 GHz when DC is used as a reference.

[Explanation of symbols]

1 high frequency circuit board 2 coplanar tracks 3 openings 4 bumps 5 First dielectric layer 6 conductor layers 7 Second dielectric layer 8 Semiconductor elements 9 grand 11 Bonding tool 12 through holes 13 Third dielectric layer 14 Lid 15 Back substrate 16 Sealing resin 17 cavities 18 signal lines 19 beer hall 20 Back side ground

─────────────────────────────────────────────────── ─── Continued Front Page (56) References JP-A-7-147352 (JP, A) JP-A-2000-22409 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23/12 H01P 5/08

Claims (11)

(57) [Claims] 1. At least a first dielectric layer, a conductor layer,
A second dielectric layer is laminated in this order from the bottom, a coplanar line having a signal line and a ground is formed by the conductor layer, and a part of the second dielectric layer is removed to form the coplanar line. A high-frequency circuit board, characterized in that an opening is formed to expose a part of the substrate, a semiconductor element is mounted on the opening and is electrically connected to the coplanar line. 2. The semiconductor element is flip-chip mounted on the coplanar line via a bump, and the height of the upper surface of the second dielectric layer is lower than the height of the upper surface of the semiconductor element. The high frequency circuit board according to claim 1, wherein the high frequency circuit board is provided. 3. A semiconductor element having a planar dimension larger than that of the opening is flip-chip mounted on the coplanar line via a bump, and the opening provided in the second dielectric layer is formed. The high frequency circuit board according to claim 1, wherein the high frequency circuit board is closed by the semiconductor element. 4. The high frequency circuit board according to claim 3, wherein the second dielectric layer is formed of an organic resin material. 5. The high frequency circuit board according to claim 3, wherein the semiconductor element is sealed with a resin material. 6. The semiconductor element is flip-chip mounted on the coplanar line via bumps, and the height of the upper surface of the second dielectric layer is the same as the height of the upper surface of the semiconductor element. The high frequency circuit board according to claim 1. 7. The semiconductor element is flip-chip mounted on the coplanar line via bumps, a substrate is placed on the upper surface of the semiconductor element, and an opening provided in the second dielectric layer is provided. The high frequency circuit board according to claim 6, which is closed by a board. 8. The high frequency circuit board according to claim 1, wherein the ground forming the coplanar line has a finite width. 9. The ground-to-ground distance of the coplanar line is
9. The high frequency circuit board according to claim 1, wherein the high frequency circuit board has a signal wavelength of 1/10 or more. 10. The high frequency circuit board according to claim 1, wherein the thickness of the second dielectric layer is 1/10 or more of the distance between the grounds. 11. The high frequency circuit board according to claim 1, wherein the same material is used for the first dielectric layer and the second dielectric layer.