JPH0831967B2 - Clock phase control circuit - Google Patents

Description

The present invention relates to a clock phase control circuit applied to a television receiver for receiving and demodulating a subsampled television signal.

(Prior Art) A sub-sample transmission method that enables high-definition television signals to be transmitted even in a transmission path with a limited band (The Institute of Electronics and Communication Engineers, Vol.J68-D, No.4 P .647,198
There is 5).

In the sub-sampling transmission method, an analog television signal is sampled at a constant sub-sampling clock, and the obtained sample value is thinned and transmitted. The receiving side reproduces the same sampling clock as the transmitting side and resamples the received signal to obtain a reproduced television signal.

The clock used for the re-sampling is reproduced by the PLL circuit in synchronization with the horizontal synchronizing signal of the television signal. However, the PLL circuit has an equivalent input S / N due to a small wide-range spectrum component of the horizontal synchronizing signal.
It is impossible to completely remove the steady-state error due to the deterioration of, the minute waveform distortion, and the like. Therefore, the clock of the optimum sampling phase is not always reproduced.
When the sample phase is shifted, as shown in FIG. 3, when one pulse is transmitted, ringing appears at sample points other than the peak point of the pulse.

By the way, a necessary condition for properly transmitting the sampled value is that the ringing of the pulse does not appear except at the peak point. In order to satisfy this, the pulse waveform is accurately performed by the matching filter in the sub-sample transmission method. However, even if this pulse shaping is performed correctly, if the phase of the resampling clock is deviated as described above, interference occurs between the information of sample values. This interference spreads spillover between adjacent sample points and the image suffers significant ringing interference.

Conventionally, the clock phase is manually adjusted so that the ringing is minimized.

(Problems to be Solved by the Invention) It is extremely difficult to properly perform the above-described conventional manual ringing avoidance if there is a change in the characteristics of the transmission line. That is, in terrestrial broadcasting, if the transmission line characteristics fluctuate momentarily due to ghost interference, manual control becomes impossible, and in the case of cable transmission, transmission line (cable) reflection causes However, since the ringing state changes, manual adjustment is still difficult.
Further, the phase shift that causes the ringing is also caused by the circuit variation when manufacturing the receiving device, and therefore, manual adjustment is required even when the product is shipped so that the characteristics of the device are aligned. This adjustment is very troublesome because it needs to be performed for each device.

Even if the phase adjustment is finished, the S /
When N is small and noise is large, the phase fluctuation near the adjustment point becomes significant. This clock phase jitter is
It causes image deterioration.

The present invention has been made to solve the above-mentioned conventional problems, and provides a clock phase control circuit capable of automatically adjusting the phase of a resampling clock and eliminating phase jitter after control convergence. The purpose is to do.

[Structure of the Invention] (Means for Solving Problems) A clock phase control circuit according to the present invention uses a reference signal for detecting waveform distortion information inserted in a transmission signal, and uses a ringing amount of a reception signal. And a loop control for changing the clock phase so as to minimize the detected ringing amount.

Then, this phase control is performed only for a fixed time after the clock phase is locked, and then held. Furthermore, after convergence, in order to deal with the phase shift due to fluctuations in transmission characteristics, etc., the detected ringing amount is leak integrated, and when this leak integration value exceeds a certain threshold value, that is, the phase fluctuation is unacceptable. When that happens, the phase control is restarted.

(Operation) With the above configuration, the ringing amount of the received signal is automatically controlled so as to be minimized. Further, the jitter of the phase after the phase is converged is eliminated, and a stable reproduced image can be obtained.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In this embodiment, the transmission signal is assumed to have a pulse waveform inserted in its vertical synchronizing signal as a reference signal for detecting waveform distortion information such as ghost disturbance.

The input television signal (1) is sampled and digitized by the A / D converter (2) using the sampling clock (3). The A / D converter (2)
The digital television signal (4) output by is transmitted to the phase detector (5) and the waveform memory (6). The phase detector (5) detects the phase difference between the horizontal synchronizing signal in the television signal (4) and the previous sampling clock (3). The detected phase difference output (7) is supplied to the loop filter (9) via the adder (8) and integrated. The integrated output (10) of the loop filter (9) is the D / A converter (1
It is converted to a DC analog voltage by 1) and supplied as an oscillation control voltage (13) to the voltage controlled oscillator (VCO) (12) at the next stage. The VCO (12) changes the phase of the output of the sampling clock (3) according to the value of the control voltage (13). With the 1PLL control system described above, the sampling clock (3) is phase-synchronized with the horizontal synchronizing signal, but its phase is not yet controlled so that ringing is minimized.

The automatic control system, which is the main part of the present invention, will be described below. The waveform memory (6) to which the digital television signal (4) is supplied has a pulse sample value xk (k = -M, ..., -1,) included in the vertical synchronizing signal of the television signal.
0, 1, ..., M) are sequentially updated and stored every time a pulse arrives. As shown in FIG. 4, the pulse has a waveform such that x0 = 1 and xk = 0 (k ≠ 0) if the sample phase is proper.

The sample value xk of the pulse output from the waveform memory (6) is led to the peak detector (14) and the error calculator (15). The peak detector (15) inputs the maximum value x0 and removes this value from the sample value xk.
Using (k ≠ 0), one of the following sums of absolute values is obtained.

E A1 = Σ | xk |, E A2 = Σ | xk-xk-1 | E M1 = Σxk ² , E M2 = Σ (xk-xk-1) ² Above E A1 and E A2 are the sum of the absolute values of ringing amount , E M1, E
M2 corresponds to the sum of squared ringing values, both of which are indicators of the ringing amount. In particular, since E A2 and E M2 calculate the difference between the ringing components, the detection amount is not affected by the DC component, which is preferable. Below, E A1, E A2, EM
1 and E M2 are collectively referred to as an error signal E.

The error signal E output from the error calculator (15) is supplied to the comparator (16) and the register (17). Register (1
7) supplies to the comparator (16) the previous error signal E'which it has stored with respect to the supplied error signal E. A comparator (16) compares the values of both error signals E and E ', determines a correction value d based on the polarity of a correction value d'described later, and outputs it to an accumulator (18) and a register (19). . The modified value d'is the previous modified value stored by itself output from this register (19). The value of the modified value d is determined as follows.

+ Δ: (E <E ′ and d ′> 0) or (E> E ′ and d ′ <0) d = 0: E = E ′ −Δ: (E <E ′ and d ′ <0) or (E > E ′ and d ′> 0) where Δ is a fixed minute amount. As is apparent from the above, the value of the correction value d changes by Δ while maintaining the same polarity as before so as to maintain the conventional control direction when E <E ′, that is, when the amount of ringing decreases as a result of control. To do. Further, when E> E ', that is, when the control result is in the direction of being deteriorated, the polarity is changed from that in the past and the value is changed by Δ in the opposite direction.

Such a modified value d is accumulated by the accumulator (18) every time a pulse arrives, and the accumulated value D is the above-mentioned adder (8).
At the phase difference output (7). As a result, an offset proportional to the cumulative value D is generated in the phase of the output clock (3) of the VCO (12) in the PLL control system described above. Since the error signal E also changes in accordance with the change in the phase offset, loop control eventually works and the accumulated value D oscillates by ± Δ due to input noise, but finally it reaches a value that minimizes the error signal E. , Reach equilibrium.

Now, how to deal with the case where the phase fluctuation occurs after the equilibrium state is reached will be described below. The phase detector (5) supplies a lock / unlock signal (a) indicating the locked state of the clock recovery loop to the controller (20). The lock / unlock signal (a) is "1" when locked and "0" when unlocked as shown in FIG.
Pulse signal. The controller (20) outputs the phase gate signal (b) which is “1” during the period T0 from the rising of the signal (a). The accumulator (18) supplied with the gate signal (b) operates only while the gate signal (b) is "1", stops its operation during the "0" period, and accumulates the accumulated value D.
Hold. The above T0 is set to a time sufficient for the clock phase values to converge.

On the other hand, the correction value d is guided to the integrator (21). The integrator (21) executes the following leak integration.

yi + 1 = (1-β) yi + αdi The output y of the integrator (21) is supplied to the comparator (22) and compared with the threshold value y thr. The comparator (22) outputs to the controller (20) a phase fluctuation detection signal (c) which becomes "1" when y exceeds y thr. The state in which the phase variation detection signal (c) becomes "1" is a state in which the automatically adjusted and optimized clock phase exhibits unacceptable variation.

That is, since the ringing amount decreases as the phase control progresses, the correction value d also decreases. Therefore, the value of the output y of the integrator (21) becomes lower than the threshold value y thr at a certain point in time when the phase optimization is advanced, and the phase fluctuation detection signal (c) becomes “0”. However, when the optimum phase becomes a conventional one due to fluctuations in the transmission path characteristics, ringing occurs and the integral value y starts to increase. At some point when this state is maintained, the integral value y exceeds the threshold value y thr, and the phase fluctuation detection signal (c) becomes “1”. That is, the state in which the detection signal (c) is "1" indicates that the phase is out of phase. Therefore, the controller (2
0) means that when the phase fluctuation detection signal (c) becomes "1",
The phase control gate signal (b) is set to "1" for the period of T0 again,
Start phase control. This makes it possible to eliminate clock phase jitter.

[Effects of the Invention] As described above, according to the present invention, when receiving and demodulating a sub-sampled television signal, ringing caused by the resampling phase shift is automatically minimized. Can be As a result,
It is possible to automatically eliminate the phase shift without manual adjustment, which was impossible or difficult to perform.

Furthermore, while monitoring the ringing amount by leak integration,
Since the clock phase control is repeatedly executed and stopped, the phase jitter can be prevented and the reproduced image can always be kept in a good state.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a clock phase control circuit of the present invention, FIG. 2 is a waveform diagram of various control signals used in the present invention, and FIG. 3 is a diagram for explaining a phase shift of sampling. It is a pulse waveform diagram. (1) …… TV signal, (2) …… A / D converter,
(3) …… Sampling clock, (4) …… Digital television signal, (5) …… Phase detector, (6) ……
Waveform memory, (14) …… Peak detector, (15) …… Error calculator, (16) …… Comparator, (18) …… Accumulator, (20)
...... Controller, (21) …… Integrator, (22) …… Comparator, (a) …… Lock / unlock signal, (b) …… Phase control gate signal, (c) …… Phase fluctuation detection signal .

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seiichi Koshi 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the broadcasting technology laboratory of Japan Broadcasting Corporation (72) Inventor Yu Sakurai 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Address Company Home Appliance Technology Laboratory, Toshiba Corporation Yokohama Works (56) Reference JP-A-63-46073 (JP, A) JP-A-61-163783 (JP, A)

Claims (1)

[Claims] 1. An A / D converter, into which a reference signal for detecting waveform distortion information is inserted in a vertical synchronization section and which inputs an analog television signal whose sample value is transmitted, and the A / D converter.
Inputs a television signal digitized by the A / D converter, supplies a phase-controlled sampling clock to the A / D converter, and outputs a lock / unlock signal indicating whether the system is in a locked state PLL control system, a waveform memory that sequentially updates and stores the reference signal each time it arrives, and an error that calculates an absolute value sum or square value sum based on the reference signal supplied by the waveform memory as an error signal. Calculating means, comparing means for comparing the error signals that are sequentially output by the error calculating means, and a correction value for increasing or decreasing the value according to the increase or decrease state of the error signal detected by the comparison result of the comparing means Means, an accumulator that accumulates the correction value and outputs the accumulated value as a phase control signal, an integrator that leak-integrates the correction value, and an output of the integrator has a predetermined threshold. A comparator that outputs a phase fluctuation detection signal when exceeding the above, a constant enough to optimize the clock phase by inputting the lock / unlock signal and starting the accumulator at the time of shifting from the unlock state to the lock state. An automatic control system having control means for holding and outputting the phase control signal after operating for a period of time and for operating the accumulator again for the fixed period when the phase fluctuation detection signal is input, In addition to the PLL control system, the clock phase control circuit controls the phase of the sampling clock by the phase control signal.