JPH0537962A - Method for synchronizing clock - Google Patents

Abstract

PURPOSE:To correct a clock phase deviation by forming a signal for correcting the phase deviation of a reference signal oscillator from a difference between the 1st and 3rd data out of the 1st to 3rd data on an impulse signal peak value and sampling points before and after the peak value. CONSTITUTION:A horizontal synchronizing pulse fetching circuit 4 fetches a horizontal synchronizing pulse from an output signal outputted from an A/D conversion circuit 1 and a phase detecting circuit 5 detects a phase error. An adder 6 corrects a residual offset value in the error signal and sends the corrected signal to a reference signal oscillation circuit 7 to accurately lock a clock phase. On the other hand, a VIT signal fetching circuit 2 fetches a VIT signal from the output signal of the circuit 1, and if the clock phase is deviated a residual offset detecting circuit 3 detects asymmetry of a waveform from a peak value and sampling points before and after the peak value. The circuit 3 generates a signal D for canceling the difference or sum between the asymmetry data and sends the formed signal D to the adder 6 to automatically adjust the residual offset. Thus a clock phase deviated can be corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronization method for automatically and stably locking a phase of a system clock.

[0002]

2. Description of the Related Art As a technique for band-compressing a high-definition video signal, a multiple sub-Nyquist sampling encoding method (MUSE method) (Multiple Sub-Nyq) is used.
UistSampling Encoding) is N
Developed by HK (Japan Broadcasting Corporation), it is regularly broadcast by satellite broadcasting.

The MUSE system is a band compression system for transmitting a high-definition video signal on one channel of satellite broadcasting having a bandwidth of 27 MHz. In this MUSE system, a high-quality video signal is subjected to sub-Nyquist sampling processing by a band compression encoder and converted into a band compression signal having a bandwidth of 8.1 MHz.

The MUSE system is introduced in the following documents.

(A) NHK Technology Research, 1987, No. 3
Volume 9 Volume 2 Volume 172 18 (76) to 53 (11
1) Page Ninomiya, Otsuka, Izumi, Koshi, Iwadate, "MUSE
Method development ”(B) Magazine“ Nikkei Electronics, November 2, 1987, No.433 ”published by Nikkei McGraw-Hill, Inc. 1
Pp. 89-212, Ninomiya, "Transmission system MUSE for high-definition broadcasting using satellites" The waveform equalization of this MUSE signal will be described.

In the MUSE signal, a training signal for waveform equalization is preliminarily inserted and added on the transmitting side.

This training signal is a VIT signal (V
optical Interval Test Sign
al) (VITS) (VIT pulse).

On the receiving side, this MUSE signal is converted from analog to digital, then the response waveform of the VIT signal is taken in, and the characteristics of the equalizing filter on the receiving side are set so as to reduce the error from the ideal impulse response. By operating, the characteristics of the transmission path are equalized.

Regarding the waveform equalization technique for the MUSE signal, "1989 IEICE Spring National Convention Proceedings Volume 3 3-290 Lecture No. B-584""SANYO TECHNICAL REVIEW (Sanyo Denki Giho) Vol. 22, No. 2, No. 45, June 1, 1990, 48P-58P "MUSE signal transmission waveform equalizer"".

It has been considered that the residual offset adjustment of the system clock is performed by using the impulse VIT signal for waveform equalization.

That is, since the residual offset component is directly detected from the resample deviation of the VIT signal which is an impulse, if the VIT signal is taken in, the residual offset adjustment can be performed quickly and accurately.

If the system has a built-in waveform equalizer, the circuit is not added because the VIT signal waveform is fetched and the CPU performs the waveform equalization process.

For example, as shown in FIG. 2, the relationship of the values of the sampling data (x1) (x2) (x3) at three points in the VIT signal portion differs between the phase shift (A) and the normal time (B). Therefore, it is considered to detect this and correct the phase shift of the clock synchronization circuit. Also, JP-A-63-
Clock phase control is also shown in 292884 (H04N7 / 13).

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for simply correcting this phase shift amount.

[0015]

According to the present invention, the reference signal oscillator (from the first, second and third data (x1, x2, x3) of the peak value of the VIT signal (impulse signal) and sampling points before and after the peak value is used. A correction signal (D) for correcting the phase shift of 7) is created.

[0016]

In the present invention, the phase shift is corrected by the data of 3 points.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIG.

(1) is an A / D conversion circuit. (2) is a VIT signal acquisition circuit. Although not shown, the VIT signal fetch circuit (2) is for waveform equalization processing.

(3) is a residual offset detection circuit which is a feature of the present invention. This detection circuit (3) has three points (x) near the peak value in the data of the VIT signal acquisition circuit (2).
The residual offset is detected from the data (1, x2, x3) and the correction signal (D) is output.

(4) is a horizontal sync pulse fetch circuit. (5) is a phase detection circuit for detecting a clock phase shift from the data of the horizontal synchronizing portion. This circuit (4)
(5) is for correcting the clock phase, for example,
JP-A-59-221091 (H04N 7/1
It operates like 3).

(6) is an adder.

(7) is a reference signal oscillator circuit for outputting a clock signal.

The above operation will be briefly described.

The signal digitally converted by the A / D conversion circuit (1) is used as a horizontal synchronizing pulse acquisition circuit (4).
Causes the horizontal sync pulse to be captured. The captured horizontal synchronizing pulse is sent to the phase detection circuit (5) to detect a phase error.

The detected error signal has its residual offset value corrected by the adder (6) and is then sent to the reference signal oscillation circuit (7) to accurately lock the clock phase.

On the other hand, the digitally converted signal is VI
The V signal is also fetched by the T signal fetch circuit (2).

If the clock phase is correctly locked, the sample point will have a symmetrical waveform from the peak value as shown in B of FIG. 2. However, if the clock phase shifts, it will be asymmetrical as shown in A of FIG. Become.

The residual offset detection circuit (3) detects the asymmetry of the waveform from the peak value and the sampling points before and after the peak value, obtains the residual offset, and sends a signal (D) to cancel it to the adder (6). Therefore, the residual offset is automatically adjusted.

The operation of the residual offset detection circuit (3) will be described.

That is, in the normal state, x1-x3 = 0.

Therefore, control may be performed so that x1−x3 = 0.

That is, | x1−x3 | = d1 is set, and when Expression 1 x1−x3> 0, the value of the output signal (D) is slightly increased according to the value of (d1).

That is,       D = D + f (d1) Formula 2 And

When x1−x3 <0, the value of the output signal (D) is slightly reduced according to the value of (d1).

That is, D = D-f (d1) Equation 3 is used. The value of the value (d1) is squared, and increase / decrease of the output signal (D) is controlled by a value corresponding to the squared value. Is also good.

In the above embodiment, d1 is used for control, but the present invention is not limited to this.

For example, the following equations hold for regular VIT signals.

X1 + x3 = 0 Expression 4 x2-x1 = x2-x3 Expression 5 (x2-x1) + (x2-x3) = 2 Expression 6 (x1-x1 ′) + (x2-x2 ′) + (x3-x3 ') = 0 Equation 7 However, x1', x2 ', and x3' in Equation 7 each represent a data value when the ideal VIT signal is input.

That is, x1 + x3 = d2 Equation 8 may be used, and this d2 may be used in place of the d1.

In addition,       | (X2-x1)-(x2-x3) | = d3 Formula 9 The d3 may be used instead of the d1.

Also, | (x2-x1) + (x2-x3) -2 | = d4 Formula 10 may be used, and this value d4 may be used instead of d1.

In addition,     | (X1-x1 ') + (x2-x2') + (x3-x3 ') | = d5 Equation 1 This value d5 may be used as 1 instead of d1.

In this embodiment, since the residual offset value is directly detected from the resample deviation of the VIT signal, this VI
If the T signal is captured, the residual offset can be adjusted quickly and accurately. If the receiver has a built-in waveform equalization circuit, the VIT waveform is captured and C
Since the waveform equalization processing is performed by the PU, the residual offset can be detected without adding a circuit.

[0044]

According to the present invention, the phase shift of the resample clock can be obtained by a simple calculation, and the clock phase shift can be easily corrected.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining one embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation.

[Explanation of symbols]

3 Residual offset detection circuit, 7 Reference signal oscillator circuit, x2 VIT signal peak value data, x1, x3 Data before and after the peak value of the VIT signal.

Claims (5)

[Claims] 1. A peak value of an impulse signal and first, second and third data (x1, x2, x) of sampling points before and after the peak value.
From 3), in the clock synchronization method for creating the correction signal (D) for correcting the phase shift of the reference signal oscillator (7), the difference data (d1) of the first and third data is obtained, and the correction is performed from this data. A clock synchronization method for creating a signal (D). 2. The first, second and third data (x1, x2, x) of the peak value of the impulse signal and sample points before and after the peak value.
From 3), in the clock synchronization method for creating the correction signal (D) for correcting the phase shift of the reference signal oscillator (7), the sum data (d2) of the first and third data is obtained, and the correction is performed from this data. A clock synchronization method for creating a signal (D). 3. The first, second, and third data (x1, x2, x) of the peak value of the impulse signal and the sampling points before and after the peak value.
3) A clock synchronization method for generating a correction signal (D) for correcting a phase shift of the reference signal oscillator (7) according to the third difference, the first difference data between the second and first data (x2, x1), and the first difference data. The second difference data of the second and third data (x2, x3) is obtained, and the difference (d3) between the first and second difference data is obtained.
And a clock synchronization method for creating the correction signal (D) from the difference data (d3). 4. A peak value of an impulse signal and first, second and third data (x1, x2, x) of sampling points before and after the peak value.
From 3), in the clock synchronization method for creating the correction signal (D) for correcting the phase shift of the reference signal oscillator (7), the first difference between the second and first data values (x2, x1),
The second difference between the second and third data values (x2, x3) is calculated, the sum of the first and second differences is calculated, and the difference (d4) between the sum data and a predetermined numerical value is calculated. A clock synchronization method for obtaining the correction signal (D) from the difference data (d4). 5. The first, second and third data (x1, x2, x) of the peak value of the impulse signal and sample points before and after the peak value.
From 3), in the clock synchronization method for creating the correction signal (D) for correcting the phase shift of the reference signal oscillator (7), the first, second and third data (x1, x2, x3),
A value (d5) obtained by adding the respective differences between the ideal waveforms of the first, second, and third data and the first, second, and third data (x'1, x'2, x'3) , This value (d
5) A clock synchronization method for generating the correction signal (D) from 5).