JPH0831836B2 - Staff multiplex reception circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stuff multiplex receiving circuit for receiving a signal in which digital data is stuff-multiplexed on a high-speed transmission path and separating the digital data from the signal. .

[Conventional technology]

Conventionally, when digital data is stuff-multiplexed on a high-speed transmission line and separated, a separate read / write counter is provided as a control of the elastic memory, and a comparison circuit for monitoring the output state of both counters, underflow, and overflow. A control circuit and a control circuit are used.

[Problems to be solved by the invention]

The above-mentioned conventional stuff circuit has a drawback that the configuration is complicated, the hardware scale is large, and the power consumption is large because the reading and writing counters are required for controlling the elastic memory.

An object of the present invention is to provide a stuff multiplex reception circuit having a simple and small-scale circuit configuration.

[Means for solving problems]

According to the present invention, in a stuff multiplex receiving circuit that receives digital data, stuff-multiplexed on a high-speed transmission line in units of N bits, and separates the digital data from the signal, the stuff multiplex reception circuit from the transmission line is used. A signal is received, a clock bit-synchronized with the signal is reproduced, stuff control information of logic "1" immediately before the N-bit digital data is detected, and a time slot position immediately after the N-bit digital data is detected. To a serial-parallel conversion pulse, an N-stage shift register for parallelly expanding the signal into N-phases by the clock, and an N-phase parallel expansion output of the N-stage shift register for serial-parallel conversion. An N-bit register for taking in only the N-bit digital data as N-bit parallel data by a pulse; A delay circuit that delays the parallel conversion pulse and outputs a write timing pulse that matches the phase of the N-bit parallel data output from the N-bit register, and N-bit parallel data output from the N-bit register from the delay circuit. A FIFO memory for fetching the write data by the write timing pulse and outputting the N-bit parallel data by the read timing pulse;
A FIFO control circuit for monitoring the memory overflow and underflow and controlling the supply of the read timing pulse to the FIFO memory; and a parallel-serial conversion pulse,
A parallel-serial conversion circuit that performs parallel-serial conversion of the N-bit parallel data of the FIFO memory by a low-speed clock input from the terminal and outputs serial digital data;
A N-divider counter that divides the low-speed clock by N, and an output of the N-divider counter to decode the read timing pulse and the parallel-series conversion for setting a load timing to the parallel-series conversion circuit. It is possible to obtain a stuff multiplex reception circuit characterized by having a decoding circuit which outputs a pulse and a pulse.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of an embodiment of the present invention.

The stuff multiplex circuit according to the embodiment of the present invention shown in FIG.
The high speed data a shown in a of FIG. 2 is received. 2a
In the above, D1 to D7 represent N-bit digital data in one stuff unit, and in this embodiment, N bits are 7 bits. Also, i-1, i, i + 1 are
An arbitrary stuff unit number, S is a stuff control information bit, and when the stuff control information bit S is logical "1", N bits (7 bits) data immediately after that are valid data (that is, in FIG. 2). staff unit numbers i-1 and i of a
When the stuff control information bit S is logical "0", the N-bit (7-bit) data immediately after that is invalid data. Invalid data is the second
Corresponding to the shaded part of the staff unit number i + 1 in a of the figure,
This is the data to be removed in the stuff multiplex reception circuit of FIG.

In this way, the high-speed data a has the stuff control information 1 bit S of logic "1" added to the specific 7 bits (D1 to D7 of a in FIG. 2) into which digital data can be inserted, Digital data immediately after the 1 "staff control information
D1 to D7 are intermittently multiplexed signals (hereinafter referred to as stuff multiplexing).

2A to 2G show the signals a to g in FIG. 1, and m, p, h, i, l, and n in FIG. 3 show the signals m, p, h, i, in FIG. 1 and n are shown. Below, the first
The operation of the figure will be described with reference to FIGS. 2 and 3.

The high-speed data a is input from the high-speed transmission line to the separation circuit 2 through the input terminal 1 and reproduces the continuous clock b bit-synchronized with the high-speed data a, and the digital data 4D
The stuffing control information S of logic "1" of 1 to D7 is detected, and the serial-parallel conversion pulse c is output at the position of the time slot immediately after the 7-bit digital data D1 to D7. On the other hand, the high-speed data is parallel-expanded to 7 bits by the continuous clock b in the 7-stage shift register 3 and the parallel expansion data d
Is output. The parallel expanded data d is taken in by the 7-bit register 5 by the inversion pulse e of the logical product of the inversion pulse of the continuous clock b and the serial-parallel conversion pulse c, and only the digital data is taken in every 7 bits to obtain the 7-bit parallel Data f
Is output. Further, the write timing pulse g of the FIFO memory 6 to be described later is supplied by inverting the serial-parallel conversion pulse c in the delay circuit 4 by delaying it by one time slot of the continuous clock b. A FIFO (First-In First-Out) memory 6 inputs 7-bit parallel data f at a high speed of data by a write timing pulse g in the FIFO memory 6 and outputs digital data by a data read timing pulse h of the FIFO memory 6. 7-bit FIFO output parallel data i converted to speed is output.

Further, the FIFO control circuit 7 monitors and detects underflow and overflow of the FIFO memory 6, outputs a reset pulse j to the FIFO memory 6, and outputs the reset pulse j.
The output data read timing pulse h is stopped or released by the control pulse k. The 7-bit FIFO output parallel data i is output every 7 bits by the parallel-serial conversion circuit 8 by the parallel-serial conversion pulse 1 from the decoding circuit 9 described later and the low-speed clock m input from the input terminal 12 on the terminal side. Is loaded into the output terminal 11 and is converted from parallel to serial to output continuous digital data n from the output terminal 11. The low-speed clock m is 7
The frequency is divided by 7 by the frequency dividing counter 10, and the 3-bit output signal P
Is decoded by the decoding circuit 9 and outputs an inversion pulse q of the read timing pulse h of the FIFO memory 6 and a parallel-serial conversion pulse l to the parallel-serial conversion circuit 8.

FIG. 2 shows the operation up to the point where the stuff control information S of the digital data stuff-multiplexed with the high-speed data a from the transmission line is detected and only the digital data is written into the FIFO memory 6 at the rising edge of the write timing pulse g. 2 is a time chart showing FIG.

FIG. 3 shows that the digital data written in the FIFO memory 6 at a high speed is read at the falling edge of the read timing pulse h generated by the low-speed clock m input from the terminal side, and the continuous digital data n 3 is a time chart showing the operation up to the point where the output is output from the output terminal 11. It should be noted that in FIG. 2, N bits (7
Since the stuff control information bit S of the invalid data (the shaded portion of the stuff unit number i + 1 in a of FIG. 2) is “0”, the separation circuit 2 uses the stuff unit as shown in c of FIG. The serial / parallel conversion pulse c is not generated in the portion corresponding to the number i + 1, and therefore the stuff unit number i + 1
The 7-bit fetch pulse e and the write timing pulse g are not generated in the portion corresponding to the above. Therefore, the invalid data in the shaded portion of the stuff unit number i + 1 in FIG.
It is not written to the memory 6 and is removed.

〔The invention's effect〕

As described above, according to the present invention, the use of the FIFO memory eliminates the need for the read / write counter. As a result, the digital data stuff-multiplexed on the high-speed transmission line can be obtained with a simple and small-scale circuit configuration. Can be separated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
FIG. 3 is a diagram for explaining the operation of FIG. In the figure, 1: input terminal, 2: separation circuit, 3: 7-stage shift register, 4: delay circuit, 5: 7-bit register, 6: FIFO, 7: FIFO control circuit, 8: parallel-series switching circuit, 9 : Decode circuit, 10: 7 frequency division counter, 11: Output terminal, 12: Input terminal, a: High-speed data, b: Continuous clock, c: Serial-parallel conversion pulse, d: Parallel expanded data, e: 7-bit acquisition Input pulse, f: FIFO input parallel data, g: Write timing pulse, h: Read timing pulse, i:
FIFO output data, j: reset pulse, k: control pulse, l: parallel-serial conversion pulse, m: low-speed clock, n: continuous digital data, P: divide-by-7 counter output signal, S: stuff control information bit, D1 ~ D7: 7-bit digital data in the stuff unit.

Claims (1)

[Claims] 1. A stuff multiplex receiving circuit for receiving stuff-multiplexed digital data in units of N bits on a high-speed transmission line, and separating the digital data from the signal, the signal from the transmission line. Received,
A clock bit-synchronized with the signal is reproduced, stuff control information of logic "1" immediately before the N-bit digital data is detected, and serial-parallel is provided at the time slot position immediately after the N-bit digital data. A separation circuit for outputting a conversion pulse; an N-stage shift register for parallelly developing the signal into N phases by the clock;
The N-phase parallel expanded output of the stage shift register is delayed by the serial-parallel conversion pulse and the N-bit register which takes in only the N-bit digital data as N-bit parallel data, and the serial-parallel conversion pulse. A delay circuit that outputs a write timing pulse that matches the phase of the N-bit parallel data output from the N-bit register, and the N-bit parallel data output from the N-bit register is fetched and read by the write timing pulse from the delay circuit. A FIFO memory that outputs the N-bit parallel data with a timing pulse, and a FI that monitors the overflow and underflow of the FIFO memory and controls the supply of the read timing pulse to the FIFO memory.
A FO control circuit, a parallel-serial conversion pulse, and a parallel-serial conversion circuit that performs parallel-serial conversion of the N-bit parallel data of the FIFO memory by a low-speed clock input from the terminal and outputs serial digital data. A N-division counter for dividing the low-speed clock by N, and a read-out timing pulse for decoding the output of the N-division counter.
A stuff multiplex reception circuit, comprising: a decode circuit for outputting the parallel-to-serial conversion pulse for setting a load timing to the parallel-to-serial conversion circuit.