JPH0831795B2 - Digital-to-analog converter - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital-analog converter for converting a digital signal into an analog current signal, and more particularly to a digital-analog converter capable of high-speed conversion.

<Prior Art> FIG. 7 shows the configuration of a 3-bit digital-analog converter. In FIG. 7, 1 to 3 are constant current sources, into which currents I, 2I and 4I respectively flow. Reference numerals 4 to 6 denote current switches, to which the constant current sources 1 to 3 are respectively connected. The current switch 4 is composed of transistors 41 and 42. The emitters of these transistors are connected to the constant current source 1,
The collector of the transistor 41 is connected to the first line 7 and the collector of the transistor 42 is connected to the second line 8. In addition, the threshold voltage V _TH
Is applied, and the base of the transistor 42 is connected to the terminal D ₀ . This bit is the first bit of the digital signal to be converted
Applied to D ₀ . The current switches 5 and 6 have the same structure, and the second and third bits of the digital signal are applied to the terminals D ₁ and D ₂ , respectively.

In such a configuration, the low level of the digital signal is sufficiently lower than the threshold voltage V _TH ,
High levels are made high enough. The current switch whose input digital signal is at a high level causes the output current of the connected constant current source to flow through the second line 8, and the low level current switch causes a current to flow through the first line 7. Therefore, when the input digital signal has a negative logic, the value of the current flowing through the first line 7 is proportional to the digital signal to be converted, and the digital signal is converted into an analog signal.

<Problems to be solved by the invention> However, such a digital-analog converter is
It suffices if the individual bits of the input digital signal are perfectly synchronized, but if they are not synchronized, glitches occur. FIG. 8 shows the relationship between the input digital signal and the output current, and (A) is the digital signal,
Reference numerals D _{0 to} D ₂ represent digital signals applied to the terminals D _{0 to} D ₂ of FIG. 1, respectively. (B) is a change in the output current flowing through the first line 7. The digital signals corresponding to D _{0 to} D ₂ do not change at the same time, but change at t _{1 to} t ₃ , respectively. Therefore, as shown in (B), a current transiently flows and a glitch occurs. Since the effect of glitches due to this timing shift increases as the number of bits of the digital signal increases, it has been difficult to increase the conversion speed especially in a multi-bit digital-analog converter.

<Object of the Invention> The present invention is to provide a digital-analog converter capable of high-speed conversion by eliminating the influence of glitch.

<Means for Solving the Problems> In order to solve the above problems, according to the present invention, the weighted output currents of a plurality of constant current sources are controlled by a current switch connected to each of the constant current sources. Railroad and second
Selectively flow on the railway. This current switch is controlled by a digital signal which is to be converted into an analog signal. In such a configuration, the output current of the constant current source is bypassed to the second line by a switching element which is connected in parallel with the current switch and driven by a common signal.

<Embodiment> FIG. 1 shows an embodiment of a digital-analog converter according to the present invention. The same elements as those in FIG. 7 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1, reference numerals 10 to 12 are transistors, the bases of which are commonly connected to form a terminal OF.
Connected to F. The signal V _OFF is applied to this terminal OFF. The collectors of the transistors 10 to 12 are connected to the second line 8, and their emitters are the constant current sources 1 to 1, respectively.
3 and the current switches 4 to 6 are connected.

Next, the operation of this embodiment will be described. When the signal V _OFF becomes a low level sufficiently smaller than the threshold voltage V _TH, all the transistors 10 to 12 are turned off, and the same operation as the digital-analog converter explained in FIG. 7 is performed. That is, the digital signal is converted into the magnitude of the current value which is an analog signal. When V _OFF becomes a high level sufficiently larger than the threshold voltage V _TH, all the transistors 10 to 12 are turned on, and the output currents of the constant current sources 1 to 3 are irrespective of the operation of the current switches 4 to 6. Flow to 8, first
No current flows through the line 7. That is, the output of the digital-analog converter becomes zero. It is possible to prevent the occurrence of glitches by setting the signal V _OFF to a high level before all the bits of the input digital signal change and setting the signal V _OFF to a low level after the change.

FIG. 2 shows an example in which a high-speed digital-analog converter is configured by using the two digital-analog converters shown in FIG. In FIG. 2, 13 and 14 represent the digital-analog converters shown in FIG. 1, respectively. Digital signal 1 is applied to the terminals D _{0 to} D ₂ of the digital-analog converter 13, and the terminals are turned off.
A signal V _OFF is applied to the inverter via the inverter 15. Further, the digital signal 2 is applied to the terminals D _{0 to} D ₂ of the digital-analog converter 14, and the signal V _OFF is applied via the buffer 16 to the terminal _OFF.
Is applied. The first line 7 is connected and becomes an output,
The second line 8 is connected to the common potential point.

Next, the operation of this embodiment will be described based on the time chart of FIG. The same elements as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 3, the digital signals 1 and 2 have a period T, and their data are updated with a shift of T / 2 from each other. At that time, the data of the digital signal 1 is updated, and the data of the digital signal 2 is stable. Immediately before this, when V _OFF is made low, only the digital-analog converter 14 becomes active and the transistors 10 to 12 are activated.
A current corresponding to the digital signal 2 appears on the first line 7 in a short time when the switch turns off. That is, the digital signal 2 is converted into an analog signal. At this time, the data of the digital signal 2 changes, and V _OFF becomes high level immediately before that, so that only the digital-analog converter 13 becomes active and the digital signal 1 is converted into an analog signal. By doing so, digital-analog conversion can be performed in a short time in which the transistors 10 to 12 are turned on and off, regardless of the time when each digital signal becomes stable and the conversion time of the digital-analog converters 13 and 14.

FIG. 4 shows another embodiment. In this embodiment, a constant output and an analog output corresponding to a digital signal are alternately output at high speed. The same elements as those in FIGS. 1 and 2 are designated by the same reference numerals, and the description thereof will be omitted. FIG. 4 (A) is a configuration diagram, and 17 is a constant current source into which I _OFF current flows. This constant current source 17 is a digital-analog converter
It is connected to the first line 7 which is the output of 13. (B) is a time chart, and V _OFF is supplied so that the digital signal input to the digital-analog converter 13 becomes high level when the digital signal changes. As shown in this figure, since the output of the digital-analog converter 13 becomes zero when V _OFF is at a high level, the output of this embodiment is only the output I _OFF of the constant current source 17, and V _OFF is low. At the level, the output will be the current value corresponding to the digital signal input to I _OFF .

In the embodiment of FIG. 1, the digital-analog converter is
Although it consisted of NPN transistor,
It can also consist of FET. FIG. 5A shows an example of PNP transistors, and FIG. 5B shows an example of FETs. The same elements as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The configuration is basically the same even if it is composed of PNP transistors and FETs.

Also, the output of the digital-analog converter can be taken out as a voltage signal. This embodiment is shown in FIG. Resistance 18
Is connected between the output of the digital-analog converter 19 and the positive power supply V ₊ , thereby performing current-voltage conversion. Output is resistance 18
Take from both ends of.

Further, although the input digital signal is 3 bits in these embodiments, the other bits can be similarly configured by adding the current switch, the transistor and the constant current source in parallel.

<Effects of the Invention> As specifically described above based on the embodiments, according to the present invention, a current switch for selectively flowing the current of the constant current source to the first or second line in accordance with the input digital signal. A switching element is connected in parallel with the above, and the current of the constant current source is forced to flow through the second line. Therefore, the output can be set to zero at a timing different from the digital signal switching timing, so that there is an effect that a glitch due to the digital signal switching can be prevented without affecting the conversion time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital-analog converter according to the present invention, FIGS. 2 and 4 are block diagrams showing an application example of the digital-analog converter according to the present invention, and FIG. FIG. 5 is a diagram for explaining the operation of the application example, FIGS. 5 and 6 are diagrams showing another embodiment, FIG. 7 is a configuration diagram showing the configuration of a conventional digital-analog converter, and FIG. It is a characteristic curve figure. 1-3, 17 ... Constant current source, 4-6 ... Current switch, 7 ...
… First line, 8 …… Second line, 10 to 12 …… Transistor, 13,14,19 …… Digital-analog converter, 15 …… Inverter, 16 …… Buffer.

Claims (1)

[Claims] 1. A plurality of constant current sources to which output currents are respectively weighted, and a first or a first output current corresponding to a plurality of constant current sources connected to the plurality of constant current sources to be converted into analog signals. And a switching element connected in parallel to the current switch and driven by a common signal to bypass the output current of the constant current source to the second line. Is a digital-to-analog converter.