JPS612428A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To improve a nonlinear error or monotonousness without increasing chip size of the area of an IC by connecting a buffer amplifier group between an R-2R ladder consisting of low-order n bits and a current switch group or changing the ratio of the resistance values of the uppermost two resistors of an R-2R ladder resistor consisting of upper m bits so that the nonlinear error (monotonousness) is improved. CONSTITUTION:The buffer amplifiers 4 having the same shape are inserted between the R-2R ladder consisting of the low-order n bits and the current switches as shown in a broken line. Consequently, the nonlinear error is not deteriorated even if the high-order n bits are switched. The resistance values of two resistors R1, R2 shown in the broken line out of the R-2R ladder resistor consisting of upper m bits are set to a specific ratio.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a digital-to-analog converter (hereinafter referred to as a DA converter), and is particularly suitable for use in a single-chip IC, and is suitable for high-speed DA conversion with a signal band of 200 MHz or more. Concerning vessels.

[Background of the invention]

As a conventional DA converter, for example, an R-2R resistance ladder type or an equal current addition type is used. In particular, as shown in FIG. 1, a compromise type in which the upper m bits are of the current addition type and the lower n bits are of the R-2R ladder type is often used from the viewpoint of high speed and low glitch. In the figure, (m+n) bits of digital input are added and an analog output is taken out. The upper m-bit digital input is processed by segment decoder 1 as (
2"-1) current switches are sequentially switched from off to on. Analog output is obtained according to the digital input cover turn. The lower n-bit digital input has the same delay time as the higment decoder. The n current switches are arbitrarily switched from the off state to the on state via the buffer 2. Depending on the digital input cover turn, an analog output is obtained via the R-2R ladder resistor network. The advantages of this DA converter are as follows.

(1) The buffer between the R-2R ladder resistance network and the upper 2n-1 current switches connects the ladder resistance network to (2”
-1) The time constant determined by the parasitic capacitance of the transistors of the current switches can be reduced, and the speed can be increased.

(2) Glitches can be reduced due to segment current addition.

On the other hand, since the base current of the buffer amplifier is mixed in, an error occurs in switching between the upper m bits and the lower n bits.
This has the disadvantage that non-linearity errors become worse and monotonicity breaks down.

[Purpose of the invention]

An object of the present invention is to improve the nonlinearity error or monotonicity of a high-speed DA converter using a buffer amplifier without increasing the chip size or IC area.
The purpose of the present invention is to provide an A converter.

[Summary of the invention]

The buffer amplifier is the cause of poor monotonicity in high-speed DA converters using buffer amplifiers. The buffer amplifier described above is provided between the R-2R ladder of lower n bits and the current switch to improve non-linearity error (monotonicity). Alternatively, non-linearity error (monotonicity) can be improved by changing the ratio of the two most significant resistors R1 and R2 of the R-2R ladder resistors of the lower n bits.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. Before that, the principle will be explained with reference to FIG.

The amplification factor is shown at the buffer amplifier 3 in the figure. Therefore, it becomes as follows.

Here, if the R-2R ladder is evenly divided, the lower n bits 2n''L, S, B are i6R, but the upper m bits 2''L, S, B are i6R. Therefore, each time the upper m bits change, it will deviate by the ideal value. Therefore, every time the upper m bits change, a nonlinear error will occur, and the monotonicity will be changed to ±-!-L, S, B, it becomes impossible to press within 2n°1〉(β+1), monotonicity is ±
IL, S, B.

That's all. The cause of this is the base current ib flowing into the buffer amplifier.

Since it is impossible to increase the current amplification factor β infinitely,
The monotonicity (nonlinearity error) is improved by the method described below. In FIG. 2, a buffer amplifier 4 having the same shape is inserted between the R-2R ladder of the lower n bits and the current switch, as shown by the broken line. With each buffer amplifier,
Make sure that the relationship in Equation 1 holds true. At this time, the upper m bits of 2h''IL, S, B, and the lower n bits of 2n''
'L, S, B.

Even if the cut is switched, the nonlinearity error will not worsen.

As another improvement method, R of the upper m bits in FIG.
- Of the 2R ladder resistors, R2 and R2 shown within the broken line
Let the following relationship hold.

At this time, the upper m bits of 2n''L, S, B, and the lower n bits of 2n+1L, S, B become i, XR,
Even if the upper m bits are switched, the nonlinearity error does not get worse. (Formula 3) is rewritten as (Formula 4).

〔Effect of the invention〕

According to the present invention, deterioration of monotonicity (non-linearity error) caused by a buffer amplifier aiming at high speed can be solved by changing the ratio of R-2R or by changing the ratio of the buffer amplifier without increasing the IC chip size. This can be prevented by insertion.

[Brief explanation of the drawing]

FIGS. 1 and 2 are diagrams showing circuits of a DA converter according to the present invention. R, R2...Resistance to compensate for monotonicity (non-linear error).

Claims (1)

[Claims] Of the (m+n) bits of digital input signal, the upper m bits are processed by a current output type segment type DA converter, and the lower n bits are processed by an R-2R ladder type DA converter.
A conversion circuit, between which a buffer amplifier consisting of one transistor, whose emitter is connected to the m-bit current output terminal, whose collector is connected to the output terminal of the lower n-bit R-2R ladder, and whose base is connected to an appropriate potential (Vo), is installed. In the combined digital-to-analog conversion means provided, the basic unit of digital-to-analog conversion of the upper m bits (2^n^+
^1L, S, B, L, S, B=Least Signi
fi-cant Bit) and the basic unit of digital-to-analog conversion of the lower n bits (2^n^+^1L, S, B,
) between each R-2R ladder of the lower bits and each current switch, the emitter is connected to the current switch. (2) A buffer amplifier consisting of a transistor whose collector is connected to an R-2R resistor and whose base is connected to the above potential, or (2) two current switches between the current switch of the upper m bits and the current switch of the lower n bits. resistance (R_1 and R_2)
The ratio of R_1/R_2=β-1/β+1 (β is the current amplification factor of the above buffer amplifier) and R_4+R_2=2R
(R: R resistance of R-2R resistance).